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path: root/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
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* gpu: nvgpu: Put debugfs dependencies inside #ifdefTerje Bergstrom2017-04-24
| | | | | | | | | | | | | | | | | | | Put all debugfs dependencies inside #ifdef CONFIG_DEBUG_FS. This includes some functions in allocators that were used only for debugging. Remove include of linux/debugfs.h on files that do not deal with debugfs. linux/debugfs.h implicitly included linux/fs.h, which we relied on. Add explicit include of linux/fs.h for all files where this is the case. Change-Id: I16feffae6b0e3a2edf366075cdc01ade86be06f9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1467897 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add support for GM20B GPC PLL C1 revAlex Frid2017-04-20
| | | | | | | | | | | | | | | | Separated parameters for GM20B GPC PLL revisions B1 (default), and C1 (new, not characterized, yet). For now, used C1 spec settings. Skipped PL divider glitch WAR, since revision C1 is glitchless. Bug 1851797 Bug 1867980 Change-Id: I12dc101d002a41230e9323c47af234f6bae8e034 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/1461680 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Make gm20b clk_ops struct staticPeter Boonstoppel2017-04-20
| | | | | | | | | | | | | | Fixing Sparse warning. Rename clk_ops struct to gm20b_clk_ops and declare static. Bug 200067946 Change-Id: Ice9e42ee71edb35acafd6fd06d6fb6712f695b47 Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1464909 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Use new delay APIsTerje Bergstrom2017-04-13
| | | | | | | | | | | | | | | Use platform agnostic delay functions instead of Linux kernel APIs. This allows removing dependency to Linux header linux/delay.h. At the same time remove #include lines for other unused Linux headers. JIRA NVGPU-16 Change-Id: I05df9d72edaf4bb061febe0cb40fc8a7cf9f51c7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1460114 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: Add wrapper nvgpu/bug.hTerje Bergstrom2017-04-13
| | | | | | | | | | | | | Add wrapper header file nvgpu/bug.h. It #includes <linux/bug.h> in Linux. JIRA NVGPU-13 Change-Id: I7bf02ba554333f7cbd79d72bd1cb423c81ebcb49 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1461545 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Wrappers for checking platform typeTerje Bergstrom2017-04-11
| | | | | | | | | | | | | | | | | Add nvgpu_* wrappers for determining if we're running in simulation or silicon, and if we're running in hypervisor. The new wrappers require struct gk20a pointer, and gk20a_fence_wait() did not have access to one. Add struct gk20a pointer as the first parameter. JIRA NVGPU-16 Change-Id: I73b2b8f091ca29fb1827054abd2adaf583710331 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1331565 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gm20b: Use new error macrosTerje Bergstrom2017-04-07
| | | | | | | | | | | | | | | gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: Ic27fb98e03a982e5a1cf672cb4e8f87ecea10a5b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1457345 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in clk codeDeepak Nibade2017-03-30
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in clk_gk20a.c/clk_gm20b.c/clk_gp106.c - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: If6ddc2c924e1ab13274b857f904859033722479a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1321293 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove unnecessary use of dev_name()Terje Bergstrom2017-03-28
| | | | | | | | | | | | | | | Move the name field from struct gpu_ops up to struct gk20a. The field is not a function op, so it doesn't belong in gpu_ops. Replace all uses of dev_name() with use of g->name when possible. JIRA NVGPU-16 Change-Id: Ic6e99e39258cbf3bb7c806962cbbd7de5126688f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1328534 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pass gk20a struct to gk20a_busyDavid Nieto2017-03-24
| | | | | | | | | | | | | | | | | After driver remove, the device structure passed in gk20a_busy can be invalid. To solve this the prototype of the function is modified to pass the gk20a struct instead of the device pointer. bug 200277762 JIRA: EVLR-1023 Change-Id: I08eb74bd3578834d45115098ed9936ebbb436fdf Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1320194 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: use common nvgpu mutex/spinlock APIsDeepak Nibade2017-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using Linux APIs for mutex and spinlocks directly, use new APIs defined in <nvgpu/lock.h> Replace Linux specific mutex/spinlock declaration, init, lock, unlock APIs with new APIs e.g struct mutex is replaced by struct nvgpu_mutex and mutex_lock() is replaced by nvgpu_mutex_acquire() And also include <nvgpu/lock.h> instead of including <linux/mutex.h> and <linux/spinlock.h> Add explicit nvgpu/lock.h includes to below files to fix complilation failures. gk20a/platform_gk20a.h include/nvgpu/allocator.h Jira NVGPU-13 Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1293187 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use gm20b.gbus instead of gpcclkSrikar Srimath Tirumala2017-01-30
| | | | | | | | | | | | | | DVFS constraints for GPU are applied on gbus not on gpcclk. Make T210 K4.4 use gm20b.gbus to change the GPU clk rates and use its parent clock gbus while querrying DVFS constraints for the GPU. Bug 200233943 Change-Id: I2bad3266d6b8f8f3806a0d4249d9b40308c2ee6a Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1275926 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix gm20b round rate opsSrikar Srimath Tirumala2017-01-30
| | | | | | | | | | | | | Make the clk_round_rate ops consider the max rate supported by DVFS while calculating the max frequency. Bug 200233943 Change-Id: Ib36a40a29cb16231dd1442aa652a20819e0f4016 Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1281552 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move gpcclk sw init to probe timeSrikar Srimath Tirumala2017-01-30
| | | | | | | | | | | | | | Move the sw initialization of gpcclk to probe time so that gpcclk is ready to use before first rail ungate. Change is applicable only for platforms with CCF enabled. Bug 200233943 Change-Id: I7b322215041c0b88e9e2a37567af408fbbc31dc1 Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1280830 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: fix round_rate ops for CCF"Srikar Srimath Tirumala2017-01-30
| | | | | | | | | | | | This reverts commit 34d8421ab4e9ecd0af09f7fefe71b9a1d8781061. Bug 200233943 Change-Id: Id03b7922c955d252aff54e6bbd8163926bdc65fb Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1280828 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: fix gpcclk for K4.4"Srikar Srimath Tirumala2017-01-30
| | | | | | | | | | This reverts commit a918003694984b6fca9e6b6c07fd7cdf3503055e. Change-Id: Idf39cc0946c5c4df82c7c4b6afa225b1f8d5a923 Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1280827 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* drivers: gpu: nvgpu: Use soc/tegra/fuse.h for fuse headerLaxman Dewangan2017-01-19
| | | | | | | | | | | | | | | | The fuse headers are unified and moved all the content of linux/tegra-fuse.h to the soc/tegra/fuse.h to have the single fuse header for Tegra. Use unified fuse header soc/tegra/fuse.h. bug 200260692 Change-Id: Icab3ba5c3dbcd3fa831455c2f336942d356ff5ac Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1287498 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move gm20b HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gm20b HW headers to a new directory specially for them: include/nvgpu/hw/gm20b And change the code to include like so: #include <nvgpu/hw/gm20b/hw_fb_gm20b.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: I0765e2f6bcd5aa1e803efd250056de3cf9bfa7ed Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1244791 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Check reference clock before useTerje Bergstrom2017-01-04
| | | | | | | | | | | We use GPU reference clock as a divider. Check before division that reference clock is not zero. Change-Id: Ie453a78b422b2e740daeb7c12ce5b06faa52ba76 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1275743 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
* gpu: nvgpu: Cast det_out to u64 for 64-bit calcTerje Bergstrom2017-01-04
| | | | | | | | | | | voltage_get() defines det_out as u32. That variable is used to calculate a 64-bit result, so cast det_out to u64. Change-Id: I054ec299a4c7961cb38dd5ac0cbf0ac173b09efb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1267692 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
* gpu: nvgpu: fix round_rate ops for CCFSrikar Srimath Tirumala2016-12-21
| | | | | | | | | | | | | | | | | Make round_rate return max freq when called with a value greater than the max clock frequency. Bug 200233943 Change-Id: Id128611f2d09b17a0a0edfefd4b526fd8c215bce Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1272305 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> Tested-by: Jonathan Hunter <jonathanh@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
* gpu: nvgpu: fix gpcclk for K4.4Srikar Srimath Tirumala2016-12-20
| | | | | | | | | | | | | | | Move the sw initialization of the gpcclk from gpu rail ungate path to the nvgpu probe path. This allows gpcclk to register itself successfully with CCF and makes it discoverable for other clients early on during boot. Bug 200233943 Bug 200259437 Change-Id: I88d94542092f92e68dc63c40444a70991d1f6129 Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1265549 Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
* gpu: nvgpu: gm20b pass correct clk to tegra_dvfsPeter Boonstoppel2016-12-20
| | | | | | | | | | | | | | | | | | | Restoring original behavior. Use gbus instead of gpu_ref clk as the argument to tegra_dvfs_get_fmax_at_vmin_safe_t(). Bug was introduced due to refactoring in 01e61860fafbc0ee045c2db931a79f6c0d5300aa, changing behavior when nvgpu is compiled with CONFIG_TEGRA_CLK_FRAMEWORK. Bug 200233943 Change-Id: Id2deec0107bd0c26a12feb511db22fc69e09a985 Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1269848 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> Tested-by: Jonathan Hunter <jonathanh@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
* gpu: nvgpu: Enable signed versus non-signed errorsTerje Bergstrom2016-12-08
| | | | | | | | | | | Fix a few trivial signed versus unsigned problems, and enable compilation flag to treat them as errors. Change-Id: I68cc327885ef1efb12db7f347a2699a65415f889 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1265291 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: register clkdev for DVFS purposesPeter De Schrijver2016-11-29
| | | | | | | | Change-Id: I354d4bbddb2aba2a1a668cc0401437f1e2403b79 Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-on: http://git-master/r/1259495 GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com>
* gpu: nvgpu: gm20b expose gpcclk through CCFPeter Boonstoppel2016-11-15
| | | | | | | | | | | | | Register gpcclk with Common Clock Framework to expose GPCPLL frequency control Bug 200233943 Change-Id: Id6f7bbaca15f22157b91b092c2a035af933fa71e Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1236979 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Support new fuse driver for gm20bPeter Boonstoppel2016-11-15
| | | | | | | | | | | | Tegra fuse driver no longer supported on k4.4 Bug 200233943 Change-Id: I31b58d947436a51ff57b16f7903e9ef8daaf66fc Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1242480 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use device instead of platform_deviceTerje Bergstrom2016-04-08
| | | | | | | | | Use struct device instead of struct platform_device wherever possible. This allows adding other bus types later. Change-Id: I1657287a68d85a542cdbdd8a00d1902c3d6e00ed Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120466
* gpu: nvgpu: Combine delays with GM20B parametersAlex Frid2015-05-18
| | | | | | | | | | | | | | | | | Added delays definitions to GPCPLL parameters structure: - locking timeout delay (applied to locking in fixed frequency mode and to PLL dynamic ramp in any mode) - lock delay for GPCPLL NA mode - IDDQ exit delay in any mode Specified delay parameters for GM20B PLL, and used this data instead of hard-coded numbers. Change-Id: I63ce0abc9ee900c36ec34b8641513db3cbb6f7d5 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/732094 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Add GPU voltage debug accessAlex Frid2015-05-18
| | | | | | | | | | | | | | - Added GPU voltage debug print to the initial locking of GPCPLL under bypass (available only when GPCPLL is in NA mode). - Added /sys/kernel/debug/gpu.0/voltage debugfs node to read voltage through GPCPLL (available only when GPCPLL is in NA mode). Change-Id: I6643ad4d1b228ec4cbc4ff5e8716cce3ef9dccfc Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/731572 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Add Fmax at Vmin debugfs nodeAlex Frid2015-04-04
| | | | | | | | | Change-Id: I547cc02a544d117a4c76bf2541b9594d0769c2ef Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/682822 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Remove hard-coded GPU name stringsAlex Frid2015-04-04
| | | | | | | | | | | | Removed hard-coded GPU name strings. Instead retrieved GPU name via device name access interfaces. Change-Id: Iefb41cc610e92e870d4664951c3599df2bb83020 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/682671 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: fix sparse warningsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | Fix below sparse warnings : kernel/drivers/gpu/nvgpu/gm20b/mm_gm20b.c:283:5: warning: symbol 'gm20b_mm_get_big_page_sizes' was not declared. Should it be static? kernel/drivers/gpu/nvgpu/gm20b/clk_gm20b.c:1055:12: warning: symbol 'gm20b_clk_get' was not declared. Should it be static? Bug 200032218 Change-Id: Id199b4b1853b3c933c91509fd550c7b5538cff29 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/660133 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* dvfs: tegra21: Rename predict interfacesAlex Frid2015-03-18
| | | | | | | | | | | Renamed predict voltage interfaces to clarify temperature dependencies accounted for each interface. Change-Id: Ic76b25a6a8b22f9268d4b3e4186c53b6c3461192 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/562194 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Add GPCPLL DVFS state to debug printsAlex Frid2015-03-18
| | | | | | | | | Bug 1555318 Change-Id: I80655e047963619b5a3d7e9155db13c9396417fe Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/598970 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* dvfs: tegra21: Don't allow NA mode on certain partsAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | GM20b GPCPLL NA mode should not be enabled on Tegra21 parts with speedo revision 0 or 1, even when CONFIG_TEGRA_USE_NA_GPCPLL is set. Respectively, in this case non-NA GPU DVFS table must be selected. To accommodate this restriction added GPU speedo id 1, and mapped parts with revision 2 and above to this new speedo id. Kept speedo id 0 for parts with revision 0 or 1. Only non-NA DVFS table is selected for speedo id 0. Either non-NA or NA mode DVFS table can be selected by CONFIG_TEGRA_USE_NA_GPCPLL setting for parts with speedo id 1. GM20b GPCPLL mode selection procedure is updated accordingly, so that NA mode is disabled for speedo id 0, and selected for speedo id 1 by CONFIG_TEGRA_USE_NA_GPCPLL. The latter takes precedence over GPCPLL ADC calibration fuses - if config option is set, and part has speedo id 1, NA mode is enabled even if calibration fuses are not burnt (less accurate s/w self-calibration is used in this case). Bug 1555318 Change-Id: I3948cb945206d0bc0f9f2bb6da5505c50ffc2af1 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/594718 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Add GPCPLL parameters to GM20b debugfsAlex Frid2015-03-18
| | | | | | | | | Bug 1555318 Change-Id: I0338e5d46c7f7d910faada0205dccf28aa62d6c2 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/594746 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Protect GM20b clock init from div-by-0Alex Frid2015-03-18
| | | | | | | | | | | | Protected GM20b clock initialization from div-by-0 in case when safe fmax at Vmin is not known, and the respective interface returns zero. Change-Id: I2064a3182c93f283c7e85c247601203dd1f71af4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/559059 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* dvfs: tegra21: Rename thermal safe maximum frequencyAlex Frid2015-03-18
| | | | | | | | | | Renamed field and function operated on thermal safe maximum frequency to make it clear that it is fmax at Vmin (not global fmax). Change-Id: Ie2b5234e87dc5dc03ccdaeb2916f0b776e56b640 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/559058 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Override GM20b RAM SVOP PDP fusesAlex Frid2015-03-18
| | | | | | | | | | | | | | | Override GM20b RAM SVOP PDP fuses with 0x2 setting during clock initialization. Bug 1550997 Change-Id: I9a873b892a2db4af384a9a7af4470562cdcb1572 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/499554 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Update GM20b GPCPLL NA mode settingsAlex Frid2015-03-18
| | | | | | | | | | | | | - Updated DFS_COEFF slope/intercept parameters - Specified VCO control gain - Increased safe DVFS margin to 10% Bug 1555318 Change-Id: I619704b7ba029d77ea1019a86003c3e8d80d04d8 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/552446 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Change quantize order in GPCPLL NA modeAlex Frid2015-03-18
| | | | | | | | | | | | When calculating fractional divider in GPCPLL NA mode quantize voltage before (used to do it after) applying DFS_COEFF, to follow h/w order. Bug 1555318 Change-Id: I37be2bc73cd1f849695b94acc4ff21caf26e8b97 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/552741 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Update GM20b clock initializationAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | - Removed unnecessary static "initialized" variable (sw_ready flag is protecting from multiple initializations, anyway). - Used max frequency at min voltage to set initial configuration of GPCPLL in both NA and non-NA mode. For backward compatibility made sure initial PLL output rate do not exceed 1/3 of VCO minimum. Bug 1555318 Change-Id: If970c27442ea1109d4503a322998a6a26159c345 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/552370 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Prepare for GPCPLL NA data integrationAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | In preparation for GM20B GPCPLL NA data integration: - Added VCO control initialization code (no data, yet) - Replaced absolute safe margin with relative percentage (preliminary 8%) - Retrieved maximum safe frequency at minimum voltage from GPU DVFS table, instead of hard-coded macro (also fix the name of the limit: maximum instead of minimum) - Updated comments Bug 1555318 Change-Id: I49a7a90cc4bc29e181065ebd2cf9d214edae6465 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/542462 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Change GPCPLL NA rate in flightAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added support for GM20b GPCPLL frequency change in NA mode outside of bypass. In this case the respective PLL DVFS detection settings are updated in flight. The implemented algorithm relies on characterization providing two frequency limits at the same voltage: max frequency on the F/V curve (Fmax@V) in NA mode with characterized DVFS coefficient, and safe frequency under the curve when DVFS coefficient is zero (Fsafe@V, which is effectively the same as Fmax@V in legacy/non-DVFS mode). Transition between two Fmax@V points on the curve includes: - Lowering frequency to Fsafe@V for the minimum V of the transition end-points - Setting DVFS coefficient to zero - Changing DVFS calibration point to the new voltage - Setting DVFS coefficient characterized for the new voltage - Setting final target frequency Note that voltage is changed by Tegra SoC DVFS before (when voltage increases), or after (whet voltage decreases) the above procedure. This commit kept NA mode disabled. Bug 1555318 Change-Id: Ib5620aaa113dc1caa69ecd402d9c6f68e39c472c Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/501042 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Support GPCPLL dynamic ramp in NA modeAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | Added support for GM20b GPCPLL dynamic ramp in NA mode that requires ramping of both integer NDIV and fractional SDM_DIN controls. If NA mode is enabled, dynamic ramp is used only for transition to / from disabled state. PLL frequency in NA mode is still changed under bypass only. This commit kept NA mode disabled. Bug 1555318 Change-Id: I91f5722a485d1b66b6113aa9c35a2fe36c38ea80 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/500637 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Add GM20b GPCPLL NA mode basic supportAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | Added basic support for GM20b GPCPLL noise-aware(NA) mode. In this mode PLL internal DVFS mechanism is engaged, and output frequency is scaled with voltage automatically. The scaling coefficients in this commit are preliminary, pending characterization. If NA mode is enabled, any frequency change is done under PLL bypass, with no dynamic ramp allowed. This commit kept NA mode disabled. Bug 1555318 Change-Id: I8d96a10006155635797331bae522fb048d3dc4a0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/499488 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Change GM20B post-divider in flightAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Restored changing GM20B GPCPLL post-divider in flight with the following limitation: post divider transition is glitch-less only if there is common "1" in binary representation of old and new settings. Transitions that may create glitch are implemented in glitch-less steps with minimum possible interim divider value (for example, 1 <=> 2 transition has interim value 3: 1 <=> 3 <=> 2). Steps allowed for glitch-less transitions may not always have frequency jump at/below VCO min/2 (in the example above 1st step jumps 2/3 of VCOmin). Enabled external linear divider at 1:2 during such steps. Used extra write of the same data when changing GM20b linear divider. Bug 1552225 Change-Id: Ie8fba2fbe44afd34ca68f5f355bd302b7426a632 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/496319 (cherry picked from commit bdd21e0003032fe664bd20f163dbab9942fd1d1d) Reviewed-on: http://git-master/r/499193 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Update GM20B GPCPLL bypass operationsAlex Frid2015-03-18
| | | | | | | | | | | | | | | - Skipped PLL re-locking if only post-divider is changing under bypass - Added 1us delay after switch to bypass clock source - Changed wait for lock under bypass resolution from 2us to 1us Change-Id: I259581c00c417752263ef3b2ea057200bb78ecbf Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/495473 (cherry picked from commit d90a19b8bf59c608a2a3a891b34ca714dfe990e9) Reviewed-on: http://git-master/r/499192 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Bypass for GM20B post-divider changeAlex Frid2015-03-18
| | | | | | | | | | | Switch GM20b GPCPLL under bypass when changing post-divider setting (for now, don't assume that post-divider is glitch-less). Change-Id: I62b1285c035de0913207a86c41f37b7765da3893 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/495300 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-25 22:18:18 -0400