| Commit message (Collapse) | Author | Age |
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1. Register tegra-throttle cooling device as a
platform driver.
2. Obtain all the platform data (throtlle table
info) for all instances of blanced-throtlled cdev
from device tree and register them.
Change-Id: Ie92685eea3eb5cb18068b195adc9ab5f83762399
Signed-off-by: Arun Kumar Swain <arswain@nvidia.com>
Reviewed-on: http://git-master/r/449104
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
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Updated GM20B GPCPLL programming sequence to utilize new glitch-less
post divider:
- No longer bypass PLL for re-locking if it is already enabled, and
post divider as well as feedback divider are changing (input divider
change is still under bypass only).
- Use post divider instead of external linear divider to introduce
(VCO min/2) intermediated step when changing PLL frequency.
Bug 1450787
Signed-off-by: Alex Frid <afrid@nvidia.com>
Change-Id: I4fe60f8eb0d8e59002b641a6bfb29a53467dc8ce
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Setup GPCPLL dynamic ramp coefficients based on update rate (instead
of hard-coding), since on GM20B high reference clock 38.4MHz allows
to use several update rates within supported range.
Bug 1450787
Change-Id: I0e14bcb8e3f65cc164fbb66b4adc688fcee9e2d6
Signed-off-by: Alex Frid <afrid@nvidia.com>
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Moved GPCPLL locking under bypass procedure into separate function.
Added SYNC_MODE control during locking.
Bug 1450787
Change-Id: I8dbf9427fbdaf55ea20b6876750b518eb738de1b
Signed-off-by: Alex Frid <afrid@nvidia.com>
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Updated GPCPLL parameters according to GM20b specification.
Modified PLL programming, since on GM20b PLL post divider value is
equal to divider setting (which was not the case on GK20a this code
was inherited from).
Bug 1450787
Change-Id: Ia455ac49040047a3dbcd5d5211f2fbc71dc332ae
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/447751
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Tested-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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- Set initial output rate to 1/3 of VCO minimum.
- Cleared global BYPASSCTRL to get ready for enabling PLL (this
won't bring PLL out of bypass, since SEL_VCO register is cleared).
- Added debugfs nodes for BYPASSCTRL and SEL_VCO state.
Bug 1450787
Change-Id: I10b068b006b7e9fbdf7854eff0cfd5cfdc1dd546
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/447750
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Tested-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Made GK20A and GM20B clock operations static, since they are invoked
only via HAL interfaces.
Bug 1450787
Change-Id: Ia30218ad4244bd8790b5ef96d1963678d0ba39e1
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/441710
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
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Bug 1450787
Change-Id: Id28bd49eadae7b2310410c1676d73b37f57d1443
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/441543
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
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Bug 1450787
Change-Id: Id7fb699d9129a272286d6bc93e0e95844440a628
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/440536
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Split clk_ops for GK20A and GM20B into different files
Bug 1450787
Change-Id: I34d16c54ac40c70854e80588475434c9e50b51a5
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/437771
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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