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* gpu:nvgpu:gm20b: disable irqs when hs pmu executesVijayakumar2015-03-18
| | | | | | | | | | | | | bug 200040021 polling halt irq to check for hs bin completion keep irqs disabled to avoid executing irq handler Change-Id: Ic245d89580444dcbf1cf5ec34bfe0f8b0c5bbc0f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/554659 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: fix dbg msg from secure pmuVijayakumar2015-03-18
| | | | | | | | | | dma params for dbg msgs not passed correctly Change-Id: Ic4ba2bf282b8c339a8c8f6fecd297394fd5771dd Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/552073 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: rename gpu ioctls and structs to nvgpuKonsta Holtta2015-03-18
| | | | | | | | | | | | | | To help remove the nvhost dependency from nvgpu, rename ioctl defines and structures used by nvgpu such that nvhost is replaced by nvgpu. Duplicate some structures as needed. Update header guards and such accordingly. Change-Id: Ifc3a867713072bae70256502735583ab38381877 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542620 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Fix build warningsTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | Fix build warnings by removing the unused variables, functions and duplicated code. Enable -Werror to prevent new build warnings. Change-Id: Ifd73344a6e12497e6dca595ac7a6edd7ca698f88 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/497374 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Fixes in dupe freeSupriya2015-03-18
| | | | | | | | | | | | | gr_gk20a.c : railgating path the crash was seen with multiple frees happening acr_gm20b.c : failure path, kernel panic was seen, with multiple frees Change-Id: Ifc5e78c0ee74799c7f78e6030c02d1a27d545a1e Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/494161 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Support for falctraceSupriya2015-03-18
| | | | | | | | | | | | Adding support for falc_trace for ACR Change-Id: Iad638b0de72ff122f43f2250dce6a37adab4cecb Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/494162 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove redundant lockDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | "isr_enable_lock" was used to protect pmu's isr_enabled flag and pmu enable/disable calls Instead of this extra lock, we can reuse "isr_mutex" for this purpose Bug 200014542 Bug 200014887 Change-Id: Ifbb7d6108effc132266a20517820e470d52a7110 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/453348 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gm20b: Changes for recovery pathSupriya2015-03-18
| | | | | | | | | | | | Bug 200006956 Change-Id: I54b8ead007f8d671bcc731f73377986b880b9082 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/449343 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: new gpmu ucode compatibilitySupriya2015-03-18
| | | | | | | | | | | | | | For LS PMU new ucode needs to be used. Ucode has interface header file changes too. This patch also has fixes for pmu dmem copy failure Bug 1509680 Change-Id: I8c7018f889a82104dea590751e650e53e5524a54 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/441734 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: Modify ACR host to use physical trancfgSupriya2015-03-18
| | | | | | | | | | | | | | | | | PMU ucode and ACR ucode need 0th ctx dma to be programmed for Physical access. To stay in sync with ucodes, modified 0th transcfg to be physical access, and suitably modified all other ctx dma's sent. Bug 1509680 Change-Id: Ib3a24ebb8478488af57bb465d782e4045ca7d0d0 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/432084 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Boot FECS to secure modeTerje Bergstrom2015-03-18
| | | | | | | | | | Boot FECS to secure mode if ACR is enabled. Bug 200006956 Change-Id: Ifc107704a6456af837b7f6c513c04d152b2f4d3a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424251
* gpu: nvgpu: Separate PMU firmware load from initTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Separate the code to load PMU firmware from the software init. This allows folding ACR and non-ACR PMU software initialization sequences. Bug 200006956 Change-Id: I74b289747852167e8ebf1be63036c790ae634da4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424768 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Remove extra g field in pmu_gk20aTerje Bergstrom2015-03-18
| | | | | | | | | | | pmu_gk20a has a pointer to struct gk20a *. As pmu_gk20a is part of gk20a, there's no need to have the circular dependency. Bug 200006956 Change-Id: I6d5d10a93b2fba4a26a1e28b3c5206506dc6cc04 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424767
* nvgpu: Host side changes to support HS modeSupriya2015-03-18
GM20B changes in PMU boot sequence to support booting in HS mode and LS mode Bug 1509680 Change-Id: I2832eda0efe17dd5e3a8f11dd06e7d4da267be70 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/423140 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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