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path: root/drivers/gpu/nvgpu/gk20a
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* gpu: nvgpu: falcon copy to DMEM supportMahantesh Kumbar2017-06-27
| | | | | | | | | | | | | | | - Added falcon interface/HAL copy to DMEM method. JIRA NVGPU-99 Change-Id: I783f8046e96d9e47091afb943697256c289ebab6 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1506576 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use nvgpu_flcn_copy_from_dmem()Mahantesh Kumbar2017-06-27
| | | | | | | | | | | | | | - replace usage of pmu_copy_from_dmem() with nvgpu_flcn_copy_from_dmem() - delete nvgpu_flcn_copy_from_dmem() JIRA NVGPU-99 Change-Id: If0919187078f95a165d6a152f180549ac121beaa Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1506534 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon copy from DMEMMahantesh Kumbar2017-06-27
| | | | | | | | | | | | | | | | | - Added interface/HAL method for falcon to support copy from dmem - Method to read dmem size - Method to check error on input parameters JIRA NVGPU-99 Change-Id: Id27b2b7f4f338196fc3b187555718543445d35bd Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1506525 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move sysfs dependencies from HAL to LinuxTerje Bergstrom2017-06-27
| | | | | | | | | | | | | Move sysfs dependencies from gk20a/ and gp10b/ to common/linux. At the same time the gk20a and gp10b variants are merged into one. JIRA NVGPU-48 Change-Id: I212be8f1beb8d20a57de04a57513e8fa0e2e83b4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1466055 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvpgu: Remove FECS override sysfs APITerje Bergstrom2017-06-27
| | | | | | | | | | | FECS override PMU support was removed with http://git-master/1297370. Remove the sysfs API that is wired to that. Change-Id: I5802e5a8dd78b80c3d255dd93587b24df9203fca Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1507934 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add fifo ops for handling pbdma_intr_1Seema Khowala2017-06-27
| | | | | | | | | | | | This is needed to handle new pbmda intr_1 in t19x JIRA GPUT19X-47 Change-Id: If75de0b57f3f18420aff07ee99feaad67ac63752 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1329373 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvpgu: Use correct chipidSamuel Payne2017-06-23
| | | | | | | | | | | | | | | Add gm20b "B" revision chipip. Bug 1870669 Change-Id: Ife31e6d739aabb8ef4a4f401091c3202b415a70e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1490650 Reviewed-by: Samuel Payne <spayne@nvidia.com> Signed-off-by: Samuel Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/1490648 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu_flcn_* interfacesMahantesh Kumbar2017-06-23
| | | | | | | | | | | | | | - set nvgpu_flcn_reset() to point to gk20a_pmu_reset() - set PMU interrupt using nvgpu_flcn_enable_irq() - replace pmu_idle with nvgpu_flcn_wait_idle() JIRA NVGPU-57 Change-Id: I50d0310ae78ad266da3c1e662f1598d61ff7abb6 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1469478 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon reset supportMahantesh Kumbar2017-06-23
| | | | | | | | | | | | | | | | | | | | | | | | | - Added flacon reset dependent interface & HAL methods to perform falcon reset. - method to wait for idle - method to reset falcon - method to set irq - method to read status of CPU - Updated falcon ops pointer to point gk20a falcon HAL methods - Added members to know support of falcon & interrupt. - Added falcon dependency ops member to support flacon speicifc methods JIRA NVGPU-99 JIRA NVGPU-101 Change-Id: I411477e5696a61ee73caebfdab625763b522c255 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1469453 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorder members of gpu_opsSunny He2017-06-22
| | | | | | | | | | | | | | Reorder non-function pointer members of gpu_ops to be at the very end of their respective sub-structs. This allows for easier debug interpretation and slightly improves readability. Jira NVGPU-107 Change-Id: Ife3279180306de70f7fad6760f616c6d69769b36 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: http://git-master/r/1506591 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move devfreq field to os_linuxTerje Bergstrom2017-06-21
| | | | | | | | | | | | | Move devfreq field from struct gk20a to os_linux. It's a Linux specific framework. JIRA NVGPU-38 Change-Id: I1e00f5a80e31deb4aaba379274c3a7a7b04d963b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505176 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move dma_params to os_linuxTerje Bergstrom2017-06-21
| | | | | | | | | | | | dma_params is inherently a Linux structure, so move it to os_linux. JIRA NVGPU-38 Change-Id: If81249b3cb7d65187202df72b35a1d24e274263b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505928 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove Linux devnode fields from gk20aTerje Bergstrom2017-06-21
| | | | | | | | | | | | | | | Move Linux devnode related fields to a new header file os_linux.h. The class structure is defined in module.c, so move its declaration to module.h. JIRA NVGPU-38 Change-Id: I5d8920169064f4289ff61004f7f81543a9aba221 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505927 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove some #includes from gk20a.hTerje Bergstrom2017-06-21
| | | | | | | | | | | | | | | | | | | | | linux/version.h and linux/sched.h are not used by gk20a.h, so remove them. acr_gm20b.h and bus_gk20a.h are not needed by gk20a.h, so remove them. pmu_gp106.c relies on implicit #include of acr_gm20b.h by gk20a.h, so add that as an explicit #include. Remove #include of iomap.h. platform_gk20a_tegra.c legacy rail gating code still relies on access to that header, so add it as explicit include. JIRA NVGPU-38 Change-Id: I1cf57b9d3a7ee5e3cad298341107e317b4b8662f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505926 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check ctx valid bit at right placeSeema Khowala2017-06-21
| | | | | | | | | | | | | | | | When contexts are unloaded from GR, the valid bit is reset but the instance pointer information remains intact. Check valid bit in *is_channel_ctx_resident* function as valid bit might not be set when *get_channel_from_ctx function* is called from gr_isr Bug 200289491 Change-Id: I4da7f04794c7e7e80b511756dbd851205cd76fbc Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1505908 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: get ctx id from valid ctx memSeema Khowala2017-06-21
| | | | | | | | | | | | | | ctx id should be read from right mem area else it will return 0 and cause issue with fecs methods that depend on ctx id Bug 200289491 Change-Id: Iba74f653afccf34e95cd90175833e3270239c264 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1505902 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: mclk switching sequences for PG419Thomas Fleury2017-06-21
| | | | | | | | | | | | | | | | | VBIOS memory settings have been updated for PG419, significantly modifying MCLK switching sequences. This change adds support for PG419 tables, while remaining backward compatible with PG418. Bug 1921082 JIRA EVLR-1269 Change-Id: Ia8a1f8b3f482e348a46f0acb540af23287d9c11e Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1484110 (cherry picked from commit c2444ae89caf97da2702e8486cc8fb162b4f50b1) Reviewed-on: http://git-master/r/1485300 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check for valid channel ctx before preemptseshendra Gadagottu2017-06-20
| | | | | | | | | | | | | | | Always check for valid channel gr_ctx before issuing channel preempt. Commands like "echo > /dev/nvhost-gpu" create channel to just power-up gpu without any valid channel context. So don't try to preempt those channels. Bug 1937331 Change-Id: I48a4bfd35728b83b27eb968e51a56b900d1fa799 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1505783 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove device pointer from gk20a_gpu_ctxTerje Bergstrom2017-06-20
| | | | | | | | | | | | | | Remove pointer to struct device from gk20a_gpu_ctx. The pointer is not used anywhere, and it adds an unnecessary Linux dependency. JIRA NVGPU-38 Change-Id: Id5843a21e4809ca840e4f5d561728f859bbd964e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505202 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Pass struct gk20a to secure allocTerje Bergstrom2017-06-20
| | | | | | | | | | | | | Pass struct gk20a to secure alloc API instead of Linux specific struct device. JIRA NVGPU-38 Change-Id: I6d9afaeeff9b957351072caa29690f2caf58f858 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505179 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Pass struct gk20a to busy and resumeTerje Bergstrom2017-06-20
| | | | | | | | | | | | | | Pass struct gk20a pointer to gk20a_busy_noresume() and gk20a_idle_nosuspend(). This reduces the number of dependencies to Linux specific struct device. JIRA NVGPU-38 Change-Id: I5e05be32e2376bc8be5402bb973c20e28c35a1c3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505177 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Delete obsolete WRITE_ONCE macroTerje Bergstrom2017-06-20
| | | | | | | | | | | | | | | Delete a version of WRITE_ONCE() that gk20a.h defines only for kernels older than 3.18. We don't support kernels below 4.4. JIRA NVGPU-38 Change-Id: I0af50936523fde9929c21eea0547b91dac4a0081 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505175 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Delete cooling deviceTerje Bergstrom2017-06-20
| | | | | | | | | | | | | | We don't use cooling device, so delete its definition from gk20a.h. JIRA NVGPU-38 Change-Id: Ie39d3dea4f0de870ebe6493bbf90a286452ae61d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505174 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Move internal channel trace functionTerje Bergstrom2017-06-20
| | | | | | | | | | | | | | Move internal channel trace function to ioctl_channel.c. It's not used anywhere else, so it does not need to be exported outside ioctl_channel.c. JIRA NVGPU-38 Change-Id: If6300781961ffffad4f63bc212d68adf8f3497fc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505173 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move tsg_gk20a_from_ch to tsg_gk20a.cTerje Bergstrom2017-06-20
| | | | | | | | | | | | | | | | The function tsg_gk20a_from_ch() is an operation on tsg_gk20a structure, so move it to be part of tsg_gk20a.c and export via tsg_gk20a.h. JIRA NVGPU-38 Change-Id: I2afba3533ac829088a5edf8b16cf4e071b69b77a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505172 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Move time correlation to common codeTerje Bergstrom2017-06-20
| | | | | | | | | | | | | Time correlation does not have chip or OS specific dependencies, so move it to generic new source file bus.c. JIRA NVGPU-38 Change-Id: Ic7fdf8c9ccacf05baf1b3438a86b28e517093641 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505171 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add devfreq supportSachit Kadle2017-06-19
| | | | | | | | | | | | | | | | | | | | | | Add devfreq governor support in order to allow frequency scaling in virtualization config. GPU clock frequency operations are re-directed to the server over RPC. Bug 200237433 Change-Id: I1c8e565a4fff36d3456dc72ebb20795b7822650e Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1295542 (cherry picked from commit d5c956fc06697eda3829c67cb22987e538213b29) Reviewed-on: http://git-master/r/1280968 (cherry picked from commit 25e2b3cf7cb5559a6849c0024d42c157564a9be2) Reviewed-on: http://git-master/r/1321835 (cherry picked from commit f871b52fd3f553d6b6375a3c848fbca272ed8e29) Reviewed-on: http://git-master/r/1313468 Tested-by: Aparna Das <aparnad@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: only support TSC time correlation infoKonsta Holtta2017-06-19
| | | | | | | | | | | | | | | Remove the two other unnecessary options based on jiffies and gettimeofday, leaving only the time stamp counter clocksource. Jira NVGPU-83 Change-Id: I289951aba832eda36cb9cb68b7e41e6061ec3a03 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1503000 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu : nvgpu: Update sub-feature mask for ELPG.Deepak Goyal2017-06-19
| | | | | | | | | | | | | This patch also adds new interface for GR INIT PARAM cmd and adds new pmu command to update sub-feature mask for ELPG. JIRA GPUT19X-20. Change-Id: Id3b3b65882c714f80a05de5660895258b26a08bd Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1503141 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use time API in channel ref action debugKonsta Holtta2017-06-19
| | | | | | | | | | | | | Save the time using nvgpu_current_time_ms() instead of the Linux-specific jiffies counter. Jira NVGPU-83 Change-Id: I19b4296d8b64ddf52506144e77d151f668ff7838 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1503002 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use timeout API in ch poll workerKonsta Holtta2017-06-19
| | | | | | | | | | | | | Instead of using raw jiffies, use milliseconds and the nvgpu timeout API. The COND_WAIT API uses also just milliseconds. Jira NVGPU-83 Change-Id: I21b5e0880f0b6aa02856d7c207be97861e423b6b Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1502999 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: hal for timestamps correlationThomas Fleury2017-06-15
| | | | | | | | | | | | | | | | | | | | | | | | In order to perform timestamps correlation for FECS traces, we need to collect GPU / GPU timestamps samples. In virtualization case, it is possible for a guest to get GPU timestamps by using read_ptimer. However, if the CPU timestamp is read on guest side, and the GPU timestamp is read on vm-server side, then it introduces some latency that will create an artificial offset for GPU timestamps (~2 us in average). For better CPU / GPU timestamps correlation, Added a command to collect all timestamps on vm-server side. Bug 1900475 Change-Id: Idfdc6ae4c16c501dc5e00053a5b75932c55148d6 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1472447 (cherry picked from commit 56f56b5cd9d2e75cf7d2613b5e115bfebdbee0ce) Reviewed-on: http://git-master/r/1489183 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: reorganize PMU perfmonMahantesh Kumbar2017-06-15
| | | | | | | | | | | | | | | | | | | | | | | -Moved perfmon code from pmu_gk20a.c to "drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c" file -Moved below related methods perfmon init, start/stop sampling, load counter read/write/reset, perfmon event handler - prepend with nvgpu_ for perfmon global methods by replacing gk20a_ JURA NVGPU-56 JURA NVGPU-98 Change-Id: Idbcdf63ebd76da170e609cc401b320a42110cd7b Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1501418 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use fuse APIs from <nvgpu/fuse.h>Deepak Nibade2017-06-15
| | | | | | | | | | | | | | | | | | | | | | | | Remove <soc/tegra/fuse.h> includes and include <nvgpu/fuse.h> header to remove direct dependency on platform specific header Use specific APIs like below to read/write fuses nvgpu_tegra_fuse_write_bypass() nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable() Remove old code which was compiled for kernel versions less than 4.4 since we support only k4.4 and greater versions now Jira NVGPU-75 Change-Id: Iddd8e1a8da7effbce2aff217e8e25f7de04962d6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1497518 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: bring back tegra idle registrationKonsta Holtta2017-06-15
| | | | | | | | | | | | | | | | | | | | To make do_idle work when nvgpu is built as a module, reverse the order of call dependencies for do_idle. Don't provide visible gk20a_do_{idle,unidle}() functions for the kernel but instead call the kernel for registering and unregistering pointers to them when the driver loads and unloads. Refactor the internal __gk20a_do_{idle,unidle} functions to take a struct gk20a * instead of struct device *, and use the callback api for providing that g instead of retrieving the plat device from device tree. Bug 200290850 Change-Id: Ibef8b069302e547b298069cbb97734f461a10cc3 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1493774 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: hold power ref for deterministic channelsKonsta Holtta2017-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support deterministic channels even with platforms where railgating is supported, have each deterministic-marked channel hold a power reference during their lifetime, and skip taking power refs for jobs in submit path for those. Previously, railgating blocked deterministic submits in general because of gk20a_busy()/gk20a_idle() calls in submit path possibly taking time and more significantly because the gpu may need turning on which takes a nondeterministic and long amount of time. As an exception, gk20a_do_idle() can still block deterministic submits until gk20a_do_unidle() is called. Add a rwsem to guard this. VPR resize needs do_idle, which conflicts with deterministic channels' requirement to keep the GPU on. This is documented in the ioctl header now. Make NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING always set in the gpu characteristics now that it's supported. The only thing left now blocking NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_FULL is the sync framework. Make the channel debug dump show which channels are deterministic. Bug 200291300 Jira NVGPU-70 Change-Id: I47b6f3a8517cd6e4255f6ca2855e3dd912e4f5f3 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1483038 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: moved pg out from pmu_gk20a.c/hMahantesh Kumbar2017-06-13
| | | | | | | | | | | | | | | | | | | - moved pg related code to pmu_pg.c under common/pmu folder PG state machine support methods PG ACK handlers AELPG methods PG enable/disable methods -prepended with nvgpu_ for elpg/aelpg global methods by replacing gk20a_ JIRA NVGPU-97 Change-Id: I2148a69ff86b5c5d43c521ff6e241db84afafd82 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1498363 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use hww_esr_reset field to reset hwww_esrSeema Khowala2017-06-13
| | | | | | | | | | | Use hww_esr_reset field to clear hww errors Change-Id: I4b5da20c8a4bcfe2dea357d3d2ebd53678673b48 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1500965 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add sked exception detection and handlingSeema Khowala2017-06-13
| | | | | | | | | | | | | Needed to detect and clear sked exception Bug 200315442 Change-Id: Ia85e8827e563addf7b9d0f95ef192379bb808638 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1500860 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: reorganize PMU F/W supportMahantesh Kumbar2017-06-13
| | | | | | | | | | | | | | | | | | | | - Moved pmu f/w related support from pmu_gk20a.c to "drivers/gpu/nvgpu/common/pmu/pmu_fw.c" file - Prepended with nvgpu_ for global functions & replaced wherever used - Moved below list related to PMU f/w init/remove, PMU version specific ops, non-secure ucode blob prepare, JIRA NVGPU-56 Change-Id: Ifdad8c560bd233e98728717d5868119e9d8e8d90 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1480636 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: reorganize PMU FB alloc/freeMahantesh Kumbar2017-06-13
| | | | | | | | | | | | | | | | | | Moved PMU FB access related code from pmu_gk20a.c to "drivers/gpu/nvgpu/common/pmu/pmu.c" file - Prepended with nvgpu_ for global functions & replaced wherever used. JIRA NVGPU-56 JIRA NVGPU-94 Change-Id: I42bfd9d216e6b35672a9738f01302d954b32b69e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1480551 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: reorganize PMU initMahantesh Kumbar2017-06-12
| | | | | | | | | | | | | | | | | | | | | | | | - Moved PMU init code from pmu_gk20a.c to "drivers/gpu/nvgpu/common/pmu/pmu.c" file - Moved below related methods SW/HW init, init msg handler, deinit/destroy, PMU state machine -Created HAL methods to read message queue tail & supported mutex count. -prepend with nvgpu_ for pmu init global mehtods JIRA NVGPU-56 JIRA NVGPU-92 Change-Id: Iea9efc194fefa74fb5641d2b2f4633577d2c3a47 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1480002 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: reorganize PMU IPCMahantesh Kumbar2017-06-09
| | | | | | | | | | | | | | | | | | | | - Moved PMU IPC related code to drivers/gpu/nvgpu/common/pmu/pmu_ipc.c file, -Below is the list which are moved seq mutex queue cmd/msg post & process event handling NVGPU-56 Change-Id: Ic380faa27de4e5574d5b22500125e86027fd4b5d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1478167 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move error notifier free to Linux moduleTerje Bergstrom2017-06-08
| | | | | | | | | | | | | | | Freeing error notifier involves calling dma_buf API, which is Linux specific. Move the free to happen in Linux specific channel close path. JIRA NVGPU-65 Change-Id: Ifd8b31bb8c8af13975c34add00f51dd869cfd76a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1498583 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: Update PMU firmware version.Deepak Goyal2017-06-08
| | | | | | | | | | | | | | | This patch also updates PMU cmdline args as required by updated firmware. GPUT19x-30 Change-Id: I44214007046081a44acc7284eb2854d0548a8da8 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1498188 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: use nvgpu specific nvhost APIsDeepak Nibade2017-06-08
| | | | | | | | | | | | | | | | | | | | | | | | | | Remove use of linux specifix header files <linux/nvhost.h> and <linux/nvhost_ioctl.h> and use nvgpu specific header file <nvgpu/nvhost.h> instead This is needed to remove all Linux dependencies from nvgpu driver Replace all nvhost_*() calls by nvgpu_nvhost_*() calls from new nvgpu library Remove platform device pointer host1x_dev from struct gk20a and add struct nvgpu_nvhost_dev instead Jira NVGPU-29 Change-Id: Ia7af70602cfc16f9ccc380752538c05a9cbb8a67 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1489726 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: add nvhost abstraction filesDeepak Nibade2017-06-08
| | | | | | | | | | | | | | | | | | | | | Add new abstraction file common/linux/nvhost.c for all nvhost APIs and operations and export them from header <nvgpu/nvhost.h> This file will be compiled only if config CONFIG_TEGRA_GK20A_NVHOST is set Define struct nvgpu_nvhost_dev in a separate private header nvhost_priv.h Jira NVGPU-29 Change-Id: I17e1f7836d4854feadff0c339bc093e78ba7f3eb Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1489725 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Split non-stall interrupt handlingTerje Bergstrom2017-06-07
| | | | | | | | | | | | | | | | | | | | | | Split handling of stalling interrupt to Linux specific chip agnostic and OS independent chip specific parts. Linux specific chip independent part contains handler for ISR and passing the control to a bottom half worker. It uses the new MC HALs intr_nonstall (query interrupt status), intr_nonstall_pause (pause interrupts), intr_nonstall_resume (resume interrupts), and is_intr1_pending (query per-engine interrupt bit). MC HAL isr_nonstall is removed, because its work is now handled in chip independent code. JIRA NVGPU-26 Change-Id: I3e4c9905ef6eef7f1cc9f71b0278518ae663f87e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1497048 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add MC HAL is_intr1_pendingTerje Bergstrom2017-06-07
| | | | | | | | | | | | | | | Add MC HAL is_intr1_pending. At the same time introduce nvgpu_unit that is passed as parameter to is_intr1_pending. The API is passed contents of intr1 register and an engine number, and returns true if there's an interrupt pending for the engine. JIRA NVGPU-26 Change-Id: I8e6363dd78572f8e41dbab2b258036ed168b6f75 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1497870 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: implement chip specific fb cbc_initseshendra Gadagottu2017-06-07
| | | | | | | | | | | | | Add function pointer in fb to add chip specific cbc init. GPUT19X-70 Change-Id: I12f73945d99498de965a671fd8e258b5c95bbabe Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1484524 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-17 05:39:59 -0400