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path: root/drivers/gpu/nvgpu/gk20a
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* gpu: nvgpu: gm20b: fix issue with rail gating ref countSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | | gpu rail gating reference count is going wrong because "can_railgate" is set to false during probe(). For rail-gating to work no gpu re-work is needed and by default rail-gating is enabled with INT_MAX delay. Bug 200044987 Change-Id: I9367275cd18c34cb19a51193353585789ba44c03 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/556568 Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: send ELPG init cmd after GR is readyVijayakumar2015-03-18
| | | | | | | | | | | | bug 200040021 bug 200032923 Change-Id: I5aa7f4efb1b675e9a3faaf73a80452e55cded89e Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Change-Id: Ic162902bd2f05abab9ebd37392ed56dc4c164ba8 Reviewed-on: http://git-master/r/539995 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: require mapped buffer be inside vaKonsta Holtta2015-03-18
| | | | | | | | | | When validating buffers to be mapped, check that the buffer end does not overflow over the virtual address node space. Bug 1562361 Change-Id: I3c78ec7380584ae55f1e6bf576f524abee846ddd Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: cde: CDE optimizationsJussi Rasanen2015-03-18
| | | | | | | | | | | | | | | | | -Change cde_buf to use writecombined cpu mapping. -Since reading writecombined cpu data is still slow, avoid reads in gk20a_replace_data by checking whether a patch overwrites a whole word. -Remove unused distinction between src and dst buffers in cde_convert. -Remove cde debug dump code as it causes a perf hit. Bug 1546619 Change-Id: Ibd45d9c3a3dd3936184c2a2a0ba29e919569b328 Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/553233 Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Tested-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: Remove usage of KEPLER_C syncpt incrTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | | Using KEPLER_C for doing sync point increment has side effects. It adds a SetObject method, which changes channel state that not all user space accounts for. Bug 1462255 Bug 1497928 Bug 1559462 Change-Id: I5c422ad8ca94fba15cad9bd232f7a10d94aa0973 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/554478 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: vgpu: disable GK20A PMU supportHaley Teng2015-03-18
| | | | | | | | | | | | | | | | GK20A PMU is not supported in GPU client for virtualization. However, to make native case and virtualization case can share same defconfig and kernel image, we need to enable CONFIG_GK20A_PMU and CONFIG_GK20A_DEVFREQ in defconfig. This commit changes to detect if we should disable GK20A PMU support in run time. Bug 200041597 Change-Id: I292c647303ed57af6faa1c5671037ca27b48e31e Signed-off-by: Haley Teng <hteng@nvidia.com> Reviewed-on: http://git-master/r/553653 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu:nvgpu:gm20b: disable irqs when hs pmu executesVijayakumar2015-03-18
| | | | | | | | | | | | | bug 200040021 polling halt irq to check for hs bin completion keep irqs disabled to avoid executing irq handler Change-Id: Ic245d89580444dcbf1cf5ec34bfe0f8b0c5bbc0f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/554659 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Improve error handing in fifoTerje Bergstrom2015-03-18
| | | | | | | | | When initializing fifo, we ignore several error conditions. Add checks for them. Change-Id: Id67f3ea51e3d4444b61a3be19553a5541b1d1e3a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/553269
* gpu: nvgpu: dump falcon stats in mmu fault handlerKonsta Holtta2015-03-18
| | | | | | | | | | | | | | If engine status is in context switch in the fifo mmu fault handler, dump falcon stats and gr stats for each engine. Bug 1544766 Change-Id: Idfa9772b7e67072941144ac3bdd73e791fdc2b23 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/553205 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: calculate zcull_sm_num_rcp using tpc_countDavid Li2015-03-18
| | | | | | | | | | | | old value is for 1 SMs so on gm20b with 2 SMs it resulted in half zcull coverage bug 1553171 Change-Id: I269f9a333a059b2ef533672df63ccaa90b2d00c7 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: http://git-master/r/500517 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix gpu identification for 3demcSamuel Russell2015-03-18
| | | | | | | | | | | | | | Modify GPU detection in 3demc-bw-ratio to use the SOC Id. Bug 1364894 Change-Id: If52e8c5153e76b29d67d28c52303b095df2e8bf0 Signed-off-by: Samuel Russell <samuelr@nvidia.com> Reviewed-on: http://git-master/r/542770 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add no-op stubs for vgpuKonsta Holtta2015-03-18
| | | | | | | | | | | | Implement empty or -ENOSYS functions for vgpu if CONFIG_TEGRA_GR_VIRTUALIZATION is not enabled, and remove ifdefs around the calling code. Change-Id: Idc75c9bc486d661786bc222bd9e0380aa7766e78 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/552898 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: support new pmu ucode revisionVijayakumar2015-03-18
| | | | | | | | | | bug 200042729 Change-Id: Ic4b4fa4c25f4017a69355e7f03a3f25d4ce92cff Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/552554 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not reset ctxsw & wait for fe_giTerje Bergstrom2015-03-18
| | | | | | | | | | | | | At this stage, ctxsw is always in reset state, because we're powering GPU up, or we have reset the whole GR partition. Remove the code to invoke a second reset. Fix waiting for FE idle. We should wait after each bundle, and break if any iteration fails. Change-Id: I0846f67c6d860a485dea62ff870deafe55a47365 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/552799
* gpu: nvgpu: add __must_check to gk20a_busyKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | The return value of gk20a_busy must be checked since it may not succeed in some cases. Add the __must_check attribute that generates a compiler warning for code that does not read the return value and fix all uses of the function to take error cases into account. Bug 200040921 Change-Id: Ibc2b119985fa230324c88026fe94fc5f1894fe4f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542552 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: enable aelpgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Adaptive Engine Level Power Gating power feature for gm20b. Bug 1552466 Change-Id: I2659f80a567699eff64307800710d4978d02adc1 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/501343 Reviewed-by: Mitch Luban <mluban@nvidia.com> Tested-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: Expose PMU security mode in debugfsTerje Bergstrom2015-03-18
| | | | | | | | | Expose a debugfs entry pmu_security. It allows checking if PMU was booted in secure or non-secure mode. Change-Id: Iea584b696440779bee0900edccabd4e5b2997805 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/552456
* gpu: nvgpu: create new nvgpu ioctl headerKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | Move nvgpu ioctls from the many user space interface headers to a new single nvgpu.h header under include/uapi. No new code or replaced names are introduced; this change only moves the definitions and changes include directives accordingly. Bug 1434573 Change-Id: I4d02415148e437a4e3edad221e08785fac377e91 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542651 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: rename gpu ioctls and structs to nvgpuKonsta Holtta2015-03-18
| | | | | | | | | | | | | | To help remove the nvhost dependency from nvgpu, rename ioctl defines and structures used by nvgpu such that nvhost is replaced by nvgpu. Duplicate some structures as needed. Update header guards and such accordingly. Change-Id: Ifc3a867713072bae70256502735583ab38381877 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542620 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix -EINVAL retval in ioctlsKonsta Holtta2015-03-18
| | | | | | | | | | | | Proper error number for invalid request number is EINVAL instead of EFAULT, so change it in ioctl calls. Change-Id: I8fddd34e012700550e9e30fe17ba7152b3a0417b Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542563 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: cde: check return values from busyKonsta Holtta2015-03-18
| | | | | | | | | | | check gk20a_busy return value in cde converter code paths. Bug 200040921 Change-Id: Ibad36df5877e325636a0a6ccc30c0d3d076ca941 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/540006
* gpu: nvgpu: cde: CDE swizzling optimizationsJussi Rasanen2015-03-18
| | | | | | | | | | | | | | | | | Change CDE swizzling shader kernel size to 8x8 to avoid waste with relatively small surfaces. Map compbit backing store and destination surface as cacheable. Clean up kernel size calculation. Bug 1546619 Change-Id: Ie97c019b4137d2f2230da6ba3034387b1ab1468a Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/501158 Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Tested-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: Add GM20b GPCPLL NA mode basic supportAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | Added basic support for GM20b GPCPLL noise-aware(NA) mode. In this mode PLL internal DVFS mechanism is engaged, and output frequency is scaled with voltage automatically. The scaling coefficients in this commit are preliminary, pending characterization. If NA mode is enabled, any frequency change is done under PLL bypass, with no dynamic ramp allowed. This commit kept NA mode disabled. Bug 1555318 Change-Id: I8d96a10006155635797331bae522fb048d3dc4a0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/499488 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: require bound as before gpfifo submitKonsta Holtta2015-03-18
| | | | | | | | | | | | Channel gpfifo cannot be submitted if the channel has no vm, so add a check for it and bail out if no as is bound. Clean up other similar checks too. Change-Id: Ibb0fe08e44e34bbaaa00ebd02dce6cc4d93ca5d9 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/538887 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add debug events in open and ioctlKonsta Holtta2015-03-18
| | | | | | | | | | | | | Add debug events for measuring the duration of gk20a channel open and channel ioctl calls. Bug 200035111 Change-Id: Ib4837c745e73ee1690814d60bdca021821567153 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/538768 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gk20a: Unlock mutex upon queue full.Mahantesh Kumbar2015-03-18
| | | | | | | | | | | | | | Unlock mutex upon queue full then return -EAGAIN. Bug 1551294 Change-Id: I2a06a99028f98e6602a4cc27d15015bfe1db4eda Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/501235 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Tested-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix fence creation error checkKonsta Holtta2015-03-18
| | | | | | | | | | | | nvhost_sync_create_fence returns ERR_PTRs instead of NULLs on error; check for its errors with IS_ERR. Change-Id: I9752e0d8fa703b2872918b23721ae973be58bf35 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/533794 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: Support 512 channels in gm20bTerje Bergstrom2015-03-18
| | | | | | | | | Retrieve channel count from gm20b specific header instead of the gk20a header. This increases channel count from 128 to 512. Change-Id: I96d4887432852795f7f526e33f0d3d2458f3af0e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/500623
* gpu: nvgpu: Change error for invalid ioctl to dbgTerje Bergstrom2015-03-18
| | | | | | | | | | | Change loglevel of text for invalid ioctl to dbg. Bug 20038780 Change-Id: I0a2ba97d9c21b2225f8d3db59c80b70c2f2c679e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/501171 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: cde: Increase the number of cde contextsLauri Peltonen2015-03-18
| | | | | | | | | | | | | | | Allocate four channels for cde jobs. Bug 1546619 Change-Id: Id2637f71426f42c2d553d38cd74873b9f0628b55 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/499671 Reviewed-by: Jussi Rasanen <jrasanen@nvidia.com> Tested-by: Jussi Rasanen <jrasanen@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix calculation of MMU debug addressTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | Fix calculation of the debug buffer address. Bug 1551221 Change-Id: I8d7921070549a1689dba0675d83bfdbf76ba5193 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/500705 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Riku Salminen <rsalminen@nvidia.com> Tested-by: Riku Salminen <rsalminen@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gm20b: Require rework for DVFS and rgArto Merilainen2015-03-18
| | | | | | | | | | | | | | | | | | Boards require a rework to make railgating and DVFS work realiably. The information whether the board has been reworked or not will be available on DTS. This patch adds a DTS check to the GPU driver initialisation. If the rework information is not available (or the rework has been marked as disabled), railgating and DVFS are disabled. Bug 1555485 Change-Id: Ie86fe35fb94377403472faffcbcaec645b6e40d9 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/500218 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Clear invalid methodTerje Bergstrom2015-03-18
| | | | | | | | | Invalid method needs to be cleared in gm20b to prevent getting same interrupt again. Change-Id: I4d83d1a27e5c711b5d82b95552be84d5f16a13e0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/500286
* gpu: nvgpu: FE object table has 4 elementsTerje Bergstrom2015-03-18
| | | | | | | | | Restrict reading of FE object table to the number of entries available. Change-Id: I11275ecd14e53f0b763d00d65042adb4b1e8ae6f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/449306
* gpu: nvgpu: Use polling to detect runlist switchTerje Bergstrom2015-03-18
| | | | | | | | | | | Runlist event is not sent in gm20b for updated runlist. Polling is the preferred way also for gk20a. Bug 1555239 Change-Id: I60de084db69f848f63451f1f3078f183ca51ba50 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/500241
* gpu: nvgpu: implement poll() for semaphoresKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | | | | Add poll interface and control ioctls for waiting for GPU job completion via semaphores. Poll on a gk20a channel file waits for events from pending semaphore interrupts (stalling) of that channel. New ioctls enable and disable the events, and clear a single interrupt event so that next poll doesn't wake up for it again. Bug 1528781 Change-Id: I5c6238966b5d0900c8ab263c6a7f8f2611901f33 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/497750 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ioctl support flags in gpu characteristicsKonsta Holtta2015-03-18
| | | | | | | | | | | | | | Expose supported nvgpu ioctls to userspace via bits in the flags field of nvhost_gpu_characteristics; currently define two bits for special memory allocation support. Bug 1539747 Change-Id: I1bc9333b12825d07a00b7a4136ae9d35816a5855 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/495942 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Allow skipping regops addr validationTerje Bergstrom2015-03-18
| | | | | | | | | | | If allow_all is set, skip regops address validation. Change-Id: I42d6c9f1a5d2c8d9bc6783adff5f6048c45350f6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/499221 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: Fix L2 bypass to work in gm20bTerje Bergstrom2015-03-18
| | | | | | | | | | | | L2 bypass registers have moved in gm20b. Move the code to ltc_common.c, which gets compiled once per chip version. Change-Id: I0ab4dd03c78b8ad8abc7a7b18c094b6002827587 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/499220 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: gm20b: enable elpgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Engine Level Power Gating power feature for gm20b. Bug 1552466 Change-Id: Ief9cf648270412f7a9f6f5b28a1fce08effdd670 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/499541 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: enable slcgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Second Level Clock Gating power feature for gm20b. Bug 1552466 Change-Id: I34a3d93a98f7b784ab26fb7940d50db262b35f57 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/499540 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: enable elcgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Engine Level Clock Gating power feature for gm20b. Bug 1552466 Change-Id: I6f0bc565700bfd183c703fc35389188906842a4e Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/499539 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: enable blcgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Block Level Clock Gating power feature for gm20b. Bug 1552466 Change-Id: Ibdd611bc2932ae9c3ce2c0d9eb847fa46a3759c7 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/499538 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use TSG recover APIDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use TSG specific API gk20a_fifo_recover_tsg() in following cases : - IOCTL_CHANNEL_FORCE_RESET to force reset a channel in TSG, reset all the channels - handle pbdma intr while resetting in case of pbdma intr, if channel is part of TSG, recover entire TSG - TSG preempt failure when TSG preempt times out, use TSG recover API Use preempt_tsg() API to preempt if channel is part of TSG Add below two generic APIs which will take care of preempting/ recovering either of channel or TSG as required gk20a_fifo_preempt() gk20a_fifo_force_reset_ch() Bug 1470692 Change-Id: I8d46e252af79136be85a9a2accf8b51bd924ca8c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/497875 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: handle MMU fault for TSGDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | - add support to handle MMU faults on a channel in TSG - first get the ID and type of channel that engine is running - if TSG, abort each channel in it - if regular channel, abort that channel - also, add two versions of API set_ctx_mmu_error(), one for regular channel and another for TSG Bug 1470692 Change-Id: Ia7b01b81739598459702ed172180adb00e345eba Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/497874 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add API to recover TSGDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add and export API "gk20a_fifo_recover_tsg()" to recover a TSG - if TSG is running on any engine, then trigger MMU fault on those engines - otherwise, abort each channel in TSG - modify channel specific API engines_on_ch() to generic engines_on_id() which will take an ID and a flag to specify whether ID is for channel or TSG and return engines running on that ID - modify channel specific API get_faulty_channel() to generic get_faulty_id_type() which will take pointers to ID and type of ID (either a regular channel or TSG) - remove runlist update from recover_ch() since no need to touch runlist during recovery - set error notifier first and then only abort the channels for TSG recovery path - also, add necessary accessors to get engine status type as TSG Bug 1470692 Change-Id: I7137f611f80916b3d256d4b0dc6e5cf1e93eef6f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/497873 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* edp: sysedp : CPU/GPU priority depends on fGPUMatt Longnecker2015-03-18
| | | | | | | | | | | | | | | | Provide sysedp_dynamic_capping with the instantaneous GPU frequency when notifying it of the GPU load. Modify the gpu/cpu priority decision logic to choose CPU priority until GPU frequency gets "near" the CPU-priority-limited-GPU-fmax. Introduce the priority_bias debugfs parameter to facilitate tuning of "near". priority_bias takes a value from 0 to 100. Change-Id: Ia2cba36b8ea024fb8b01b5ba195dcf6550e38121 Signed-off-by: Matt Longnecker <mlongnecker@nvidia.com> Reviewed-on: http://git-master/r/481720 GVS: Gerrit_Virtual_Submit Reviewed-on: http://git-master/r/498912 Reviewed-by: Timo Alho <talho@nvidia.com>
* gpu: nvgpu: Support ZBC color trackingLauri Peltonen2015-03-18
| | | | | | | | | | | | | | | | | | The compression state tracking user space API already accepts and returns the ZBC color used for the surface. Actually store the color in kernel so that the feature works. Bug 1536227 Bug 1524301 Change-Id: I264e1eeb90f0c4d40fe35fc2479b0ce83e19a7d7 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/497476 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Defer CDE app initializationLauri Peltonen2015-03-18
| | | | | | | | | | | | | | | | | | | | Defer CDE app initialization to the point where we actually need to launch the app. This allows us to use the compression state API also on T124 where we never use the CDE app. Also return the error code correctly from gk20a_prepare_compressible_read. Bug 1524301 Change-Id: If79fbe161e8dc9353b9f5fa0dfcd7f30b00d29b4 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/497351 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Jussi Rasanen <jrasanen@nvidia.com> Tested-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: check dma_buf_get retval with IS_ERRKonsta Holtta2015-03-18
| | | | | | | | | | | | | dma_buf_get returns PTR_ERRs, so fix checking for null to proper IS_ERR in gk20a_vm_map_buffer. Buffer mapping from user space with ioctls would also have paniced here if an improper handle would be passed. Change-Id: I245fe41cd209e49fc9265e56340c1c8215ffb1d2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/498320 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-13 10:20:32 -0400