| Commit message (Collapse) | Author | Age |
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native gpu driver supports map compbits but vgpu does not.
Bug 1778448
Bug 200275051
JIRA VFND-3513
Change-Id: I433a6f8631b495875ba899af9609203ab36187ef
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1314065
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add a debugfs interface to profile the kickoff ioctl
it provides the probability distribution and separates the information
between time spent in: the full ioctl, the kickoff function, the amount
of time spent in job tracking and the amount of time doing pushbuffer
copies
JIRA: EVLR-1003
Change-Id: I9888b114c3fbced61b1cf134c79f7a8afce15f56
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1308997
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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*client_type_gpc_v is different for t19x
Change-Id: Ic8f8eff2d98138a877ef95c6f7f40226f0d61a61
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313436
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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1) Trace buffer allocation now calls generic gmmu alloc/map.
so for dGPUs they are allocated in vidmem and iGPUs they
are allocated in sysmem
2) Use pmu surface mechanism to setup trace buffer params as
dGPU binaries follow falcon memory structure to get mem surface
params
3) Fix minor coverity issue by removing unnecessary overwrite
of count variable in trace print function
JIRA DNVGPU-217
Coverity ID 2431386
Change-Id: I2ae49a4e0450481cde2a778447c270a796681dad
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1312404
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-Handle pbus and priv stall interrupts first.
In general critical interrupts should be
handled before any other non critical ones.
-Dump info enabled with gpu_dbg_intr if priv_ring
interrupt is flagged by fmodel.
JIRA NVGPU-25
Change-Id: Iee767d8c9c933ceb57532c1b5a7fd7812daf1b6d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1311273
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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trace_printk() does an extra stringify operation before calling
do_trace_printk(). The string ends up unused. This has an impact
to kernel even if we never end up using trace_printk().
Disable use of trace_printk() and introduce a Kconfig option for
re-enabling it.
Change-Id: I2e1014f5231f2089d7dc3cb2539e3eb5f4d58361
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1295298
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Implement kmem abstraction and tracking in nvgpu. The abstraction
helps move nvgpu's core code away from being Linux dependent and
allows kmem allocation tracking to be done for Linux and any other
OS supported by nvgpu.
Bug 1799159
Bug 1823380
Change-Id: Ieaae4ca1bbd1d4db4a1546616ab8b9fc53a4079d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1283828
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Change nvgpu_kalloc() to nvgpu_big_[mz]alloc(). This is necessary
since the natural free function name for this is nvgpu_kfree() but
that conflicts with nvgpu_k[mz]alloc() (implemented in a subsequent
patch).
This API exists becasue not all allocation sizes can be determined
at compile time and in some cases sizes may vary across the system
page size. Thus always using kmalloc() could lead to OOM errors due
to fragmentation. But always using vmalloc() is wastful of memory
for small allocations. This API tries to alleviate those problems.
Bug 1799159
Bug 1823380
Change-Id: I49ec5292ce13bcdecf112afbb4a0cfffeeb5ecfc
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1283827
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Remove nvgpu_gpuid_t18x.h since this file is now visible. Migrate
the relevant definitions and defines into their expected places and
make the code use the real defines. No longer is hiding t18x specific
stuff necessary.
Bug 1799159
Change-Id: I47fa2392e46fdb7aacc70aeb0cc8c3f5ca0dc22f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1300976
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Added fecs trace characteristic flag to vgpu to determine for
platform support
Also moved fecs flag from ctxsw init to fecs init for native linux.
This makes flag init uniform across both platforms.
JIRA EVLR-993
Change-Id: Id62f31954cb5d7028ef01a199548f5f908b51eb0
Signed-off-by: Vishnu Reddy Mandalapu <vmandalapu@nvidia.com>
Reviewed-on: http://git-master/r/1305045
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Implement a worker thread to replace the delayed works in channel
watchdog and job cleanups. Watchdog runs by polling the channel states
periodically, and job cleanup is performed on channels that are appended
on a work queue consumed by the worker thread. Handling both of these
two in the same thread makes it impossible for them to cause a deadlock,
as has previously happened.
The watchdog takes references to channels during checking and possibly
recovering channels. Jobs in the cleanup queue have an additional
reference taken which is released after the channel is processed. The
worker is woken up from periodic sleep when channels are added to the
queue.
Currently, the queue is only used for job cleanups, but it is extendable
for other per-channel works too. The worker can also process other
periodic actions dependent on channels.
Neither the semantics of timeout handling or of job cleanups are yet
significantly changed - this patch only serializes them into one
background thread.
Each job that needs cleanup is tracked and holds a reference to its
channel and a power reference, and timeouts can only be processed on
channels that are tracked, so the thread will always be idle if the
system is going to be suspended, so there is currently no need to
explicitly suspend or stop it.
Bug 1848834
Bug 1851689
Bug 1814773
Bug 200270332
Jira NVGPU-21
Change-Id: I355101802f50841ea9bd8042a017f91c931d2dc7
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1297183
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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fifo_pbdma_status__size_1_v() and fifo_engine_status__size_1_v()
are not same for all gpus. Use litter value to calculate chip
specific fifo*status__size_1(v)
JIRA GV11B-45
Change-Id: I3d3d45bf79d15e14739fcc18cb1ca987669d5c11
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1312688
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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VPR channels can access VPR, and writing to FECS buffer outside of
VPR causes a region violation.
Bug 1877511
Change-Id: Ida466c81e928d1f67bf1b0e7dd6afb799c1ab2f6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1312759
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Tested-by: Season Li <seasonl@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Check for pmu enable, before calling pmu_destrory().
Change-Id: I64c5071ed69b6b50140e46da48a2b165c1f7ba02
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1313391
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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generated hw header for top_device_info_data_fault_id_enum_v
is different between legacy chips and t19x
JIRA GV11B-7
Change-Id: I877e88a5b1b1f3f41bc72b895536f4a01b4fbd4e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gr_fe_tpc_fs_r addr is different for t19x
Change-Id: I9868fcaf94d063753c4ecf1970b53374cb67b380
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1310326
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In gk20a_vm_map_duplicate_locked(), we always do a linear search
in rb-tree to find a duplicate entry of the buffer
In case NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET is set, we first
traverse whole rb-tree linearly and then compare offset_align
with the address searched from rb-tree
If size of rb-tree is very large this linear lookup takes upto
7mS and causes huge delays
Hence in case of NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET, we can
use offset_align to perform a binary search on rb-tree and then
verify that dmabuf and kind match with the node obtained from
the search
This saves a lot of time per-lookup
Bug 1874516
Change-Id: Ia4924b64d66e586c14341ae2e2283beac394bf6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1309343
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Remove MCLK and GPCCLK domain aliases, now that userspace
has swithed to new enumerations.
Jira DNVGPU-211
Change-Id: I2af2fd67dbed47088d7161ba0605e13dd7c674a5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1292609
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
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-Init pbdma and engine bit mask per runlist.
-Organize debug info to print supported pbdma instances
for particular runlist.
JIRA GV11B-3
Change-Id: Ie34dd98ccbe2c779ca1c795855c2a7df4abd2715
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1309706
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In this patch hard coded function calls for PMU
reset are replaced by PMU ops.
Change-Id: I266c43e3540163a133895244dcf91169116812f5
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1303757
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-Moved ACR interface headers from acr_gm20b.h/acr_gp106.h to
Its specific header files under drivers/gpu/nvgpu/include/nvgpu/acr/
Folder.
- nvgpu_acr.h - Top-level header-file which include ACR interfaces
headers & defines required to communicate with ACR, including this
header file is good to get access into ACR interface & made changes
accordingly,
-Deleted acr.h & acr_t18x.h as not required anymore
& removed its include from dependent files.
Jira NVGPU-19
Change-Id: Ie404043cfe1ab32404eb63a43831f470d8436324
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1304748
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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API DEFINE_MUTEX() is defined in Linux and might
not be available in other OSs.
Hence remove its usage from nvgpu
Declare and explicitly initialize below mutexes
for both nvgpu and vgpu
g->mm.priv_lock
g->mm.tlb_lock
Jira NVGPU-13
Change-Id: If72885a6da0227a1552303206172f1f2b751471d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1298042
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Instead of using Linux APIs for mutex and spinlocks
directly, use new APIs defined in <nvgpu/lock.h>
Replace Linux specific mutex/spinlock declaration,
init, lock, unlock APIs with new APIs
e.g
struct mutex is replaced by struct nvgpu_mutex and
mutex_lock() is replaced by nvgpu_mutex_acquire()
And also include <nvgpu/lock.h> instead of including
<linux/mutex.h> and <linux/spinlock.h>
Add explicit nvgpu/lock.h includes to below
files to fix complilation failures.
gk20a/platform_gk20a.h
include/nvgpu/allocator.h
Jira NVGPU-13
Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1293187
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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mutex_is_locked() API is defined on Linux only
and not on other OS like QNX.
Hence remove use of this API for OS abstraction
support to nvgpu.
Instead of using mutex_is_locked(), use
mutex_trylock() for same purpose
Jira NVGPU-13
Change-Id: I542daf20a2294153da8e8bfe89e0dc0387297523
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1297184
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In the PCI init/de-init code only disable IRQs if they were enabled.
The enable happens in the common power_on code. The PCI routines could
both be called without the common power_on code being called which
causes an extra disable to happen.
Bug 200275531
Change-Id: I43a8a9881f1e9ae254bf36230f29849df074657f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1301701
(cherry picked from commit cca70e9adccee1ef65a0a6d95a4494fc87500c17)
Reviewed-on: http://git-master/r/1298954
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Commit 7e403974d3584ab8880e42d422ee3afb7f49d6f3 ("gpu: nvgpu: Simplify
ref-counting on VMs") accidentally broke the CE context creation while
moving away from direct ch->vm assignments. ce_ctx->vm isn't part of
that simplification, so initialize it because it's used elsewhere and
were left NULL.
Bug 1846718
Change-Id: I6219880227b881d2175005b7eaf6e6e08a6f888e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1306221
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
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In two places we used broadcast register as base, but added the
unicast offset to it. This causes the write to go well beyond
valid register range.
Change the broadcast base to use unicast base instead in sequence
to resume a single SM and to record error state of SM.
Bug 200256272
Change-Id: I4ca9af2bb5877dba20ab96575f5094d42949c9e2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry-picked from commit 04177b3414535ce5092c8baeae29883bada9d36c)
Reviewed-on: http://git-master/r/1306331
Reviewed-by: Automatic_Commit_Validation_User
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Remove gm204/gm206 support. It was used only in the interim until
Pascal cards were available, and we don't maintain that code anymore.
This patch leaves only BIOS code.
Change-Id: I215988603d4588ef710bdda6e47449e9235e78ac
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1302224
GVS: Gerrit_Virtual_Submit
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Most of BIOS parsing code is not specific to any particular GPU. Move
most of the code to generic files, and leave only chip specific parts
dealing with microcontroller boot into chip specific files.
As most of the parsing is generic, they do not need to be called via
HALs so remove the HALs and change the calls into direct function
calls.
All definitions meant to be used outside BIOS code itself are now in
<nvgpu/bios.h>
Change-Id: Id48e94c74511d6e95645e90e5bba5c12ef8da45d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1302222
GVS: Gerrit_Virtual_Submit
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It couldn't be zero, since it won't enable wdt.
JIRA VFND-3450
Change-Id: I9f6ab37bd438923596406a085603c70dcb83d46a
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1292715
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This ioctl can be used on gp10b to set a flag in the context header
indicating this context should be run at elevated clock
frequency. FECS ctxsw ucode will read this flag as part of the context
switch and will request higher GPU clock frequencies from BPMP for the
duration of the context execution.
Bug 1819874
Change-Id: I84bf580923d95585095716d49cea24e58c9440ed
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1292746
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Change the prefix in the semaphore code to 'nvgpu_' since this code
is global to all chips.
Bug 1799159
Change-Id: Ic1f3e13428882019e5d1f547acfe95271cc10da5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1284628
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Move semaphore_gk20a.c drivers/gpu/nvgpu/common/ since the semaphore
code is common to all chips.
Move the semaphore_gk20a.h header file to drivers/gpu/nvgpu/include/nvgpu
and rename it to semaphore.h. Also update all places where the header
is inluced to use the new path.
This revealed an odd location for the enum gk20a_mem_rw_flag. This should
be in the mm headers. As a result many places that did not need anything
semaphore related had to include the semaphore header file. Fixing this
oddity allowed the semaphore include to be removed from many C files that
did not need it.
Bug 1799159
Change-Id: Ie017219acf34c4c481747323b9f3ac33e76e064c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1284627
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move nvgpu_common.c to drivers/gpu/nvgpu/common since it is a common
C file to all drivers.
Similarly move nvgpu_common.h to drivers/gpu/nvgpu/include/nvgpu since
this follows the new include guidelines.
Bug 1799159
Change-Id: I00ebed289973b27704c2cff073526e36505bf699
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1284612
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Add HAL for enabling and disabling shadow ROM. This removes XVE dependency
from bios code.
Change-Id: Icafec72dae71669376bbfb97077661b7165badb8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1302223
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Some copyright updates have been missed in the header files. This patch
takes care of updating those copyrights.
Bug 1799159
Change-Id: Ie51111a5da5fb1eb12aabe69dc00bfb7caea5aba
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1293354
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Moved pmuif/* headers to drivers/gpu/nvgpu/include/nvgpu folder
to support cross platform feature implementation.
Made changes to files which accessed include pmuif/* to reflect
pmuif/* movement changes.
Deleted includes of gk20a.h/pmu_gk20a.h from pmuif/*.h files.
Jira NVGPU-19
Change-Id: Iace4e107c24bdaff08a407eae3b147959173e485
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1299823
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use upstream function tegra_get_chip_id and chip id macros,
as downstream function tegra_get_chipid() and chip_id macros
is going to be deprecated.
This is done as a part to removing duplicate code.
Change-Id: I846384955e983a36af0b3501d2b23c47e1d0798c
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1299873
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Deleted PMU fecs override interface from pmu_api.h
header file as feature not used anymore
& its dependent code too.
Deleted file pmu_api.h as file dont
have any interfaces left inside
Jira NVGPU-19
Change-Id: I490cf67ae60ce2f1de37da063199ee04835b940d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1297370
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Moved ACR interface from pmu_api.h to
gpmuif_acr.h header file
gpmuif_acr.h - PMU Command/Message Interfaces for
Access Control Region (ACR)
Jira NVGPU-19
Change-Id: Ic37ff3f4ca069aa4bdd6729bbfccc00e15185b02
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1297369
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Moved perfmon interface from
pmu_api.h & pmu_gk20a.h to gpmuif_perfmon.h
header files
gpmuif_perfmon.h - PMU Command/Message Interfaces
PERFMON
Jira NVGPU-19
Change-Id: I983f89f0f6ec3b889d975178fb1405f166b7d1b9
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1297262
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Moved Power Gating (PG) interface from
pmu_api.h & pmu_gk20a.h to gpmuif_ap/pg
header files.
gpmuif_pg.h - PMU Command/Message Interfaces
for power gating (PG)
gpmuif_ap.h - PMU Command/Message Interfaces
for Adaptive Power
Jira NVGPU-19
Change-Id: I1eeee78bdf89d894f9a4731435cdb121f73b1e0f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1297203
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use MSI interrupts instead of legacy on PCIe
dGPUs to reduce latency and contention with other
PCIe devices
JIRA EVLR-986
Change-Id: I6cecc7e62e5797860d42a5bee21e8f4f664e1b18
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1291758
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The driver file includes <linux/tegra-powergate.h> but does
not use anything from this header.
Remove this unnecessarily inclusion of header file.
bug 200257351
Change-Id: Idc9c79bfdcad0081b1121ec746fcc7a70306adf5
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1300555
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Moved falcon-controller common interface code
from pmu_common.h to flcnif_cmn.h file.
Interfaces are common for falcons irrespective
of F/W on falcon controllers
Jira NVGPU-19
Change-Id: Iad11b2fade8cf6716888773b2b1c23919cbcc07b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1296695
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Moved PMU/Falcon interface which are present
in pmu_gk20a.h & pmu_common.h to new files
as per feature
nvgpu_gpmu_cmdif.h - Top-level header-file that defines
the command/message interfaces used to communicate with PMU
gpmuif_pmu.h - PMU Command/Message init interfaces
gpmuif_cmn.h - Common definitions used by interfaces
Jira NVGPU-19
Change-Id: Id8ea6075e4dbba7697036951dcb85487eb861710
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1296415
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add support to do EMC frequency scaling via bwmgr on T210 K4.4.
Bug 200267304
Change-Id: Ib01f1a256cfceefc5551e128b7ba8953fafe21d3
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: http://git-master/r/1285001
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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Added function pointer to implement chip specific
init_elcg mode and updated this pointer for legacy chips.
JIRA GV11B-58
Change-Id: I3fff4f771eaa5dad98a3d8166c9127ecd6b745e4
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1300120
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Similar to patch 67fc4629892ab60d6335752b93d883ef690f1ea4 fix
more circular dependencies arising from #include'ing gk20a.h
for no apparent reason.
Bug 200192125
Coverity ID 2011397
Coverity ID 2011398
Change-Id: I75bcb3e4e66b680498b0e20d645ab9543aae6697
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1296947
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Remove the broke ref counting from as_share. The ref-count is
incremented for every bind channel but never decremented. This
results in VMs never being freed.
Bug 1846718
Change-Id: I6253b3eab7c7471d3ed6feddb3705c49a8704bed
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1296900
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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