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path: root/drivers/gpu/nvgpu/gk20a
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* gpu: nvgpu: add target refcount for gk20a_wait_for_idle()Deepak Nibade2017-01-25
| | | | | | | | | | | | | | | | | | | | | | API gk20a_wait_for_idle() right now always waits for 0 usage count But in case railgating is disabled through sysfs, usage count will never get to 0 Hence in this case we should wait for usage count of 1 If platform->user_railgate_disabled is set, keep target usage count of 1, otherwise keep target usage count as 0 Bug 200260926 Change-Id: I1a80621ca61babbd6566989dc09a7b20670c649c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1291421 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Make driver rebind workAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the GPU bind and rebind operations work when the driver is idle. This required two changes. 1. Reset the GPU before doing SW init for PCI GPUs. This clears the SW state which may be stale in the case of a rebind attempt. 2. Cleanup the interrupt enable/disables. Firstly there was one place where nvgpu would accidentally disable the stalling interrupt twice when the stalling interrupt and non-stalling interrupt are the same. Secondly make sure when exiting nvgpu that the interrupt enable/disables are balanced. Leaving the interrupt in the -1 disable state means that next time the driver runs interrupts never quite get enabled. Bug 1816516 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1287643 Reviewed-on: http://git-master/r/1287649 (cherry picked from commit aa15af0aae5d0a95a8e765469be4354ab7ddd9f8) Change-Id: I945e21c1fbb3f096834acf850616b71b2aab9ee3 Reviewed-on: http://git-master/r/1292700 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add GPU reset to XVEAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | | | | | Add a full GPU reset function to the XVE block. This allows the driver to reset the GPU (except the XVE and XP interfaces) to clear the GPU's state. This is necessary for the GPU rebind to work. The state of the GPU needs to be cleared before the new driver instance can work. Bug 1816516 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1287642 Reviewed-on: http://git-master/r/1287648 (cherry picked from commit 7e751c0eb2c0f7d9d0b2020600c33fc8b4381878) Change-Id: Ie2b721bf1b40acbab34de2436dea4e70d33b5611 Reviewed-on: http://git-master/r/1292698 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use correct class for driver de-initAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | When removing the driver nodes make sure to use the correct class to free the dev-node. Bug 1816516 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1287641 Reviewed-on: http://git-master/r/1287647 (cherry picked from commit acf97306b4950d8397bb511784b3391a3530ff77) Change-Id: I983a2106eff6f4839c52a2e16bdd036facb501c0 Reviewed-on: http://git-master/r/1292697 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Debug spew for context priority & GfxpMihir Thakkar2017-01-24
| | | | | | | | | | | | | | | | Prints out Timeslice value, Interleave level, Graphics preemption mode and compute preempt mode along with chid, tsgid, pid. Enable it with setting dbg_mask with 8192 Bug 1855710 Change-Id: I60efef9810587f8fedd4e2ba62ba67d06d84faea Signed-off-by: Mihir Thakkar <mthakkar@nvidia.com> Reviewed-on: http://git-master/r/1287141 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add null check for g->host1x_devSeema Khowala2017-01-24
| | | | | | | | | | | | | gk20a_tegra_dump_debug() is set in a platform where host1x support is not enabled. Change-Id: Ic57f9081d75be976a092827b253cb2a195d8f16d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1284336 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: restore golden context without bindseshendra Gadagottu2017-01-20
| | | | | | | | | | | | | | | | | Copy and restore golden context correctly with context header. Removed parallel fecs bind method, which can cause issues for context in execution. Also added function pointer to freeing context header during channel context free. Bug 1834201 Change-Id: I7962d68338d5144f624375ab81436e86cb31051e Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1275201 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: compare rounded freq to last valueDeepak Nibade2017-01-20
| | | | | | | | | | | | | | | | | | We right now compare requested value to the last freq value. Last freq value is always a rounded value, whereas requested value need not be a rounded value Hence it is incorrect to compare requested value to last freq value Fix this by comparing rounded value to last_freq Change-Id: I7c6ea7c4e57105598c9af75efe70016b7fa8038b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1287360 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use soc/tegra/chip-id.h for soc headerShardar Shariff Md2017-01-20
| | | | | | | | | | | | The soc tegra headers are unified and moved all the content of linux/tegra-soc.h to the soc/tegra/chip-id.h to have the single soc header for Tegra. Change-Id: I281e19dd3eb1538b8dfbea4eb0779fb64d1fcffa Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1288365 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: pmu version updateVijayakumar2017-01-19
| | | | | | | | | | | | | | | | | bug 200269171 Updating PMU firmware to fix voltage raise when switching mclk to 810mhz with CLFC and MSCG enabled. The fix is to make sure that clock domain is not evaluated in CLFC if MSCG has engaged anytime after the previous evaluation Change-Id: I2b6979ed3361f47273f2643c27c005deac49dc8b Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1286437 (cherry picked from commit dbfccb42614ec9361628b3c3427a65d3fe908597) Reviewed-on: http://git-master/r/1287461 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix dev_info typo in refcount trackingKonsta Holtta2017-01-18
| | | | | | | | | | | | | | The recently added refcount tracking support had a slight mishap in refactoring some printks. Fix a typo to make the support compile again when enabled. Bug 1826754 Change-Id: Ifd76d644932fa219751db82a0beb3c8482ea68c3 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1285922 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: pmu: Update perfmon unit ID for T19x.Deepak Goyal2017-01-18
| | | | | | | | | | | | update perfmon id for t19x in get_perfmon_id(). JIRA GV11B-30 Change-Id: I7c76b49cc47f8de1e6fa9492e2986830dcff901f Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1284763 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: pmu: Use ops to get PMU queue HEAD/TAIL.Deepak Goyal2017-01-18
| | | | | | | | | | | | | | pmu_queue_head() & pmu_queue_tail() are updated to use gops to include chip specific PMU queue head/tail registers. JIRA GV11B-30 Change-Id: I9c3d6a4601ba2767f9ada95642052044e2b79747 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1283266 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use timer API in gk20a codeAlex Waterman2017-01-18
| | | | | | | | | | | | | | | | | Use the timers API in the gk20a code instead of Linux specific API calls. This also changes the behavior of several functions to wait for the full timeout for each operation that can timeout. Previously the timeout was shared across each operation. Bug 1799159 Change-Id: I2bbed54630667b2b879b56a63a853266afc1e5d8 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1273826 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: pmu: Add support for new PMU ucode.Deepak Goyal2017-01-18
| | | | | | | | | | | | | | -GV11B PMU ucode is added in nvgpu supported ucodes. -PMU INIT msg structure(v4) is added JIRA GV11B-30 Change-Id: Ifced87b1ca2692c277ae11f562cb36b328da3fe4 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1259274 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support t19x zbcSeema Khowala2017-01-18
| | | | | | | | | | | | | Added infrastructure for supporting new zbc features JIRA GV11B-9 Change-Id: Id8408348759488e8b0393dd89dd0faacfb111f01 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1235525 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: serialize debug session IOCTLsDeepak Nibade2017-01-17
| | | | | | | | | | | | | | | | | | Hold debug_s->ioctl_lock for all debug session IOCTLs to prevent multi-threaded user space IOCTL calls debug session IOCTL calls are not thread-safe and hence this serialization is required Bug 1832267 Change-Id: I847ac951601d4f0093546b592bdb8c8f00185317 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1286436 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: wait for idle in shutdownDeepak Nibade2017-01-17
| | | | | | | | | | | | | | | | | | | In gk20a_pm_shutdown(), we currently do not wait for IOCTLs or threads in progress and directly proceed with shutdown sequence This can cause random hangs during system shutdown Fix this by calling gk20a_wait_for_idle() after we disable runtime PM in gk20a_pm_shutdown() Bug 200260926 Change-Id: I0f06ba9232263fcb09c6e9d246be89deec053d44 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1286522 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Added lpwr_debug debugfs nodeMahantesh Kumbar2017-01-17
| | | | | | | | | | | | | | | | - lpwr_debug node to dump current pstate & PG status. JIRA DNVGPU-165 Change-Id: I8240aea7145c3016946f4322fe0781d78ee2ec73 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1253509 (cherry picked from commit 4852997df5b89aeb8544ed9092ccc9ee8b8c375e) Reviewed-on: http://git-master/r/1271618 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: HAL to get current pstateMahantesh Kumbar2017-01-17
| | | | | | | | | | | | | | | | | | - Added HAL support to get current pstate from clk_arb Note - This function is inherently unsafe to call while arbiter is running arbiter must be blocked before calling this function JIRA DNVGPU-165 Change-Id: I4e9f5eba7739280bddd9ee661fd314288c129516 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1286378 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix pmu->mscg_stat optimization issueMahantesh Kumbar2017-01-17
| | | | | | | | | | | | | | | | | | | | | | | - with help of WRITE_ONCE() & ACCESS_ONCE() make sure variable pmu->mscg_stat read/write goes through without optimization - Added WRITE_ONCE() define for kernel-3.18 version & below to support backward compatibility issue: inconsistencies on getting MSCG to trigger consistently in P5 due to a lack of memory barrier around and volatile accesses to the variable pmu->mscg_stat JIRA DNVGPU-71 Change-Id: I04d30493d42c52710304dbdfb9cb4a1e9a76f2c0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1252524 (cherry picked from commit 8af7fc68e7ab06a856ba4ef4e44de7336682361b) Reviewed-on: http://git-master/r/1271614 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: print process name on submit failureDeepak Nibade2017-01-17
| | | | | | | | | | | | | | | | | | | Print process name if we fail submit due to gk20a_busy() failure This is helpful in debugging and to know the process name submitting jobs to nvgpu after system shutdown was already triggered Bug 200262275 Change-Id: I34d8c07fc96fd5556afa982bfd56f7f3964449d0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1284113 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: sim: avoid fecs golden context restoreseshendra Gadagottu2017-01-16
| | | | | | | | | | | | | | | | | | | When gpu host is executing a context, there should not be any calls to fecs that can change the current context in execution. For some reason legacy fmodels are calling fecs method to golden context restore while loading golden context for new channel. This call is not required and should not be called. Only first time during golden context creation, fecs methods like bind can be called and it is pretty safe to do. Bug 1834201 Change-Id: Ia6178e875e3ac37fb1cf10e27976c26b9a02c56f Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1284512 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use HAL to set TSG timesliceThomas Fleury2017-01-16
| | | | | | | | | | | | | | | | | | | | | | | | | Setting timeslice for virtualized case was not effective, because both ioctls NVGPU_TSG_IOCTL_SET_TIMESLICE and NVGPU_SCHED_IOCTL_TSG_SET_TIMESLICE were calling the native function to set TSG timeslice. - Fixed wrapper function to call HAL - Defined HAL function for "native" set TSG timeslice - Also, properly update timeout_us in TSG context, in virtualized case. This change also moves the min/max bounds checking for tsg timeslice into the native function implementation. There is no sysfs node for these parameters for vgpu, as RM server is ultimately responsible for this check. Bug 200263575 Change-Id: Ibceab9427561ad58ec28abfff0c96ca8f592bdb9 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1283180 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PG sysfs update for RPPG/MSCGMahantesh Kumbar2017-01-16
| | | | | | | | | | | | | | | | | | | - Added sysfs node to control RPPG/MSCG enable/disable - RPPG is controlled with elpg_enable node, same node used to control ELPG. - MSCG is controlled with mscg_enable node JIRA DNVGPU-71 Change-Id: I1a1b33d7425c25c9cfd466f7cabce08f3152326d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1251611 (cherry picked from commit eaf255f2dd3d20c071714dd509a785e9172399bf) Reviewed-on: http://git-master/r/1274645 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: HAL to query LPWR feature supportMahantesh Kumbar2017-01-16
| | | | | | | | | | | | | | | HAL to query LPWR feautre's RPPG/MSCG support based on current pstate configured. JIRA DNVGPU-71 Change-Id: I58a34c6dca68e3eb76e222bd781578bf682eac34 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1283916 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add sysfs nodes for timeslice min/maxPeter Boonstoppel2017-01-12
| | | | | | | | | | | | | | | | | | The timeslice values that can be selected for a particular channel/tsg are bounded by a static min/max. This change introduces two sysfs nodes that allow these bounds to be configured from userspace. min_timeslice_us max_timeslice_us Bug 200251974 Bug 1854791 Change-Id: I5d5a14225eee4090e418c7e43629324114f60768 Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1280372 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update patch count after addingTerje Bergstrom2017-01-11
| | | | | | | | | | | | | | | | | | When kernel adds patches to a context, kernel needs to update the patch count in order for FECS to pick up the new patches. Previously patching was done only at the context creation time. Now patching is used also when changing preemption mode, but the patches did not take effect due to not updating count. Update patch count every time we end patching of a context. Bug 1852094 Change-Id: Ic2150741609d1d1956769e439ce1c5f2edcacb84 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1280424 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Start re-organizing the HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | | | | Reorganize the HW headers of gk20a. The headers are moved to a new directory: include/nvgpu/hw/gk20a And from the code are included like so: #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h> This is the first step in reorganizing all of the HW headers for gm20b, gm206, etc. This is part of a larger effort to re-structure and make the driver more readable and scalable. Bug 1799159 Change-Id: Ic151155cbc2e6f75009f2d9d597b364a1bed2c4c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1244790 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add support for refcount trackingKonsta Holtta2017-01-11
| | | | | | | | | | | | | | | | | If enabled, track actions (gets and puts) on channel reference counters. Dump the most recent actions to syslog when gk20a_wait_until_counter_is_N gets stuck when closing a channel. GK20A_CHANNEL_REFCOUNT_TRACKING specifies the size of the action history. Default is to disable completely, as this has some runtime overhead. Bug 1826754 Change-Id: I880b0efe8881044d02ae224c243a51cb6c2db8c1 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1262424 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set PMU "queue full" as debug messageMahantesh Kumbar2017-01-10
| | | | | | | | | | | | | | | Queue full message is not an error, it informs queue is full & wait till it gets space in queue to upload pending request. Bug 200256603 Change-Id: I14f4196b391cd54e1b9616f0555a5ce0856af428 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1260494 (cherry picked from commit e7360fb52b2030c9c68aa5ed06ecd7c32b47a8c5) Reviewed-on: http://git-master/r/1271619 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pg mscg state updateMahantesh Kumbar2017-01-10
| | | | | | | | | | | | | | | | | - Added mscg_transition_state to know mscg allow/disallow status - reused ELPG state transition defines for mscg state transition JIRA DNVGPU-71 Change-Id: Ie0214a174ceecf7e97a1086f53fd965b0b655d14 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1253508 (cherry picked from commit 726dde9cff1da38525518a91e756598a5ab71f73) Reviewed-on: http://git-master/r/1271617 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pmu->pmu_state updateMahantesh Kumbar2017-01-10
| | | | | | | | | | | | | | | | - set pmu->pmu_state to PMU_STATE_ELPG_BOOTED only for ELPG after PMU_STATE_ELPG_BOOTING state Bug N/A Change-Id: I08480e2afd5a5050a903327b91e43b25780cdaf8 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1254429 (cherry picked from commit d68f4f91796d1d98dbc1b5b24d526fe2e487966f) Reviewed-on: http://git-master/r/1271616 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add thermal alarm notification for UMDLakshmanan M2017-01-10
| | | | | | | | | | | | | | | Added the thermal alarm notification handling for UMD JIRA DNVGPU-130 Bug 200231080 Change-Id: I034c7b35a18a091ef7659ff992f1950576623cad Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1251760 (cherry picked from commit 9e66f2e2f7fbcab29e25c976c1d5fa29671afcd0) Reviewed-on: http://git-master/r/1282084 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pg stat read updateMahantesh Kumbar2017-01-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added struct pmu_pg_stats_data to extract data from multiple version of pmu pg statistics - Added pmu_pg_stats_v2 interface to fetch PG statistics data from PMU - Added MSCG debugfs node to read mscg statistics from PMU. - Added pmu_elpg_statistics HAL support for gp106 PG statistics read. - Made changes to gp104/gp106 pmu_elpg_statistics HAL to support for struct pmu_pg_stats_data JIRA DNVGPU-165 Change-Id: I2b9e89c0fae90deb45006c4478170b9a97b56603 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1252798 (cherry picked from commit 3c073b15fd991db8d65b3171b02c161294be40cd) Reviewed-on: http://git-master/r/1271615 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add thermal alert limit IOCTL for UMDLakshmanan M2017-01-10
| | | | | | | | | | | | | | | Added the thermal alert lmit IOCTL for UMD JIRA DNVGPU-130 Bug 200231080 Change-Id: I4a84157d90b12b576fa144567a3bdd5d39f5278e Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1249483 (cherry picked from commit d3458008cc3dd98d3a51841b6ed8cea1aed9eb89) Reviewed-on: http://git-master/r/1253457 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add thermal alert event handlingLakshmanan M2017-01-10
| | | | | | | | | | | | | | | | * Added the thermal alert event handling * Added the thermal alert event PMU RPC JIRA DNVGPU-130 Bug 200231080 Change-Id: If5ff2704e5aa6ad2f25123f72c3049a311dae5dc Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1248964 (cherry picked from commit 1850e5a9b9dfa2f9df634e2f284ab282ad9f7fc8) Reviewed-on: http://git-master/r/1253452 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move GPFIFO to sysmemTerje Bergstrom2017-01-09
| | | | | | | | | | | | | | | Kickoff latencies when GPFIFO is in vidmem grow significantly as function of number of GPFIFO entries. Move GPFIFO to sysmem to improve kickoff latency. Bug 1848369 Change-Id: Ie95d10df26b4f1370f7250a8fbf0f7ef0211df32 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry-picked from commit 897cb579a759bbe8455ce368413979e91eb0d475) Reviewed-on: http://git-master/r/1281564 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move allocators to common/mm/Alex Waterman2017-01-09
| | | | | | | | | | | | | | | | | | | Move the GPU allocators to common/mm/ since the allocators are common code across all GPUs. Also rename the allocator code to move away from gk20a_ prefixed structs and functions. This caused one issue with the nvgpu_alloc() and nvgpu_free() functions. There was a function for allocating either with kmalloc() or vmalloc() depending on the size of the allocation. Those have now been renamed to nvgpu_kalloc() and nvgpu_kfree(). Bug 1799159 Change-Id: Iddda92c013612bcb209847084ec85b8953002fa5 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1274400 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add support for alarms in arbiterDavid Nieto2017-01-06
| | | | | | | | | | | | | | | Pass flags as mask in event initialization JIRA: DNVGPU-189$ Change-Id: Ied22a585a8f59f44e577bc678f8cef380432c9a2 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1252474 (cherry picked from commit 56fa34b8ac0ebafaf09a8760bec6200adf9f3c39) Reviewed-on: http://git-master/r/1280886 GVS: Gerrit_Virtual_Submit Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not access NULL pointer devTerje Bergstrom2017-01-06
| | | | | | | | | | | | | In gk20a_busy() we check if dev is NULL and return -ENODEV if so. But before that we've already dereferenced dev by passing it to get_gk20a(). Defer call to get_gk20a() until after the NULL check. Bug 200192125 Change-Id: I943a9e96d13ff8cb4333fe20a941c8e95d159a66 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1280349 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix out-of-bound access on gr->map_tilesDeepak Nibade2017-01-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix slab-out-of-bounds issue reported by KASAN [ 28.464077] BUG: KASAN: slab-out-of-bounds in gr_gk20a_init_map_tiles+0x624/0x708 at addr ffffffc1a098ee01 ... [ 28.503241] INFO: Allocated in gr_gk20a_init_map_tiles+0x2dc/0x708 age=11 cpu=5 pid=1 out-of-bound access from below 3 stacks : [1] [ 28.782886] [<ffffffc0007d5f64>] gr_gk20a_init_map_tiles+0x624/0x708 [ 28.789228] [<ffffffc0007eadf0>] gk20a_init_gr_support+0x2d0/0xeb0 [ 28.795397] [<ffffffc00079d9c8>] gk20a_pm_finalize_poweron+0x738/0xd10 [2] [ 29.268070] [<ffffffc0007d618c>] gr_gk20a_zcull_init_hw+0x144/0x730 [ 29.274329] [<ffffffc0007d6a00>] gk20a_init_gr_setup_hw+0x288/0x1530 [ 29.280677] [<ffffffc0007eac6c>] gk20a_init_gr_support+0x14c/0xeb0 [ 29.286938] [<ffffffc00079d9c8>] gk20a_pm_finalize_poweron+0x738/0xd10 [3] [ 50.076223] [<ffffffc000d1df14>] gr_gk20a_setup_rop_mapping+0x5e4/0x2018 [ 50.082913] [<ffffffc000d2559c>] gr_gk20a_init_fs_state+0x80c/0x1028 [ 50.089259] [<ffffffc000ddcbc8>] gr_gm20b_init_fs_state+0xc8/0x960 [ 50.095430] [<ffffffc000e413f8>] gr_gp10b_init_fs_state+0x5c0/0x5d8 [ 50.101687] [<ffffffc000d2ed30>] gk20a_init_gr_setup_hw+0x1b48/0x2418 [ 50.108115] [<ffffffc000d50bc0>] gk20a_init_gr_support+0x19e0/0x1ab0 [ 50.114457] [<ffffffc000cc7af8>] gk20a_pm_finalize_poweron+0xd20/0x1558 Fix this by adding below - allocate gr->map_tiles[] with size of (num_gpc * num_tpc_per_gpc) intead of num_gpc - add new static API gr_gk20a_get_map_tile_count() which returns tile count for given index, and returns 0 for out-of-bounds access Bug 200257557 Change-Id: If572837ffb661f92a21be5ce855d0146b2609cb0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1279411 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove default verbose in pbus isrDavid Nieto2017-01-04
| | | | | | | | | | | | | | And reduce pri timeout to match PCIE specs bug 200246808 Change-Id: I0225ae964b5635665fe774c43f773d0ce86650ab Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1264179 (cherry picked from commit 1c3dbf8324b7ec5d06bd0e57e7deee9a1c8e9411) Reviewed-on: http://git-master/r/1280328 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add platform flag to disable ASPMAlex Waterman2017-01-04
| | | | | | | | | | | | | | | Add a platform flag and logic to disable ASPM on boot if a platform does not want ASPM enabled. Bug 200256272 Change-Id: I378997290377ef8ffa21bf8e7f3f59fa134b3d4d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1263271 (cherry picked from commit 01e4700b74f4b4c6f0b9ffb40747653f2b63ea3c) Reviewed-on: http://git-master/r/1274477 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Handle driver shutdown more gracefullyAlex Waterman2017-01-04
| | | | | | | | | | | | | | | | | | | | | | | | Handle possible asynchronous GPU driver shutdown more gracefully. This occurs when the GPU disappears from the PCI bus, for example, if it overheats or detects an over current event. Also add a preprocessor check to make sure that the gk20a_channel_cancel_pending_sema_waits() is always defined. In some builds CONFIG_SYNC is disabled but the gk20a_remove_support() code does not check for this. Bug 1816516 Bug 1807277 Change-Id: I932e312291c5c6a6ac5e13525ce8ca56a1be3652 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1250028 (cherry picked from commit 337810f8c478238a38d8553c1492622d5fa9aafa) Reviewed-on: http://git-master/r/1274476 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move deferred interrupt wait codeAlex Waterman2017-01-04
| | | | | | | | | | | | | | | | | Move the code that waits for deferred interrupts to nvgpu_common.c and make it global. Also rename that function to use nvgpu_ as the function prefix. Bug 1816516 Bug 1807277 Change-Id: I42c4982ea853af5489051534219bfe8b253c2784 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1250027 (cherry picked from commit cb6fb03e20b08e5c3606ae8a5a9c237bfdf9e7da) Reviewed-on: http://git-master/r/1274475 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Misc fixes for crashes on shutdownAlex Waterman2017-01-04
| | | | | | | | | | | | | | | | | | | | Fix miscellaneous issues seen during driver shutdown. o Make sure pointers are valid before accessing them. o Busy the GPU during channel timeout. o Cancel delayed work on channels. o Avoid access to channels that may have been freed. Bug 1816516 Bug 1807277 Change-Id: I62df40373fdfb1c4a011364e8c435176a08a7a96 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1250026 (cherry picked from commit 64a95fc96c8ef7c5af9c53c4bb3402626e0d2f60) Reviewed-on: http://git-master/r/1274474 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Handle no GPU cases in helper funcsAlex Waterman2017-01-04
| | | | | | | | | | | | | | | | | | | | | | | | | | In many helper functions like gk20a_readl() the code assumed that the GPU is present and registers and available. However, during GPU shutdown this may not be the case. In theory the driver should not be accessing GPU registers during GPU shutdown (since shutdown is triggered by GPU registers being unavailable) but these changes handle any missed cases where this may happen. This goes for GPU device access as well. Many parts of the code assume that if the struct gk20a is valid, the the GPU dev must be there are well. This isn't always the case, it seems. Bug 1816516 Bug 1807277 Change-Id: Icaf6fd56ab7860724e77bda0f5e8d48f0da15642 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1250024 (cherry picked from commit e8c9997b2d7cd424d798ecfce1307e6193c0cf32) Reviewed-on: http://git-master/r/1274473 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: FECS trace support on gp106Thomas Fleury2017-01-04
| | | | | | | | | | | | | Enable FECS ctxsw tracing for gp106. Ensure that FECS records have been written to memory before accessing the ring. Update read index only once all records have been processed. Jira EVLR-424 Change-Id: I1a21f841fcce1588397408906d77e2c3bf4a8c01 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1258243 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Check reference clock before useTerje Bergstrom2017-01-04
| | | | | | | | | | | We use GPU reference clock as a divider. Check before division that reference clock is not zero. Change-Id: Ie453a78b422b2e740daeb7c12ce5b06faa52ba76 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1275743 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-17 09:02:07 -0400