| Commit message (Collapse) | Author | Age |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- Depending on main context or subcontext,
ctxheader and gr_mem should be updated
with pm mode and buffer addresss accordingly
Bug 2404093
Change-Id: Iba16c762c09b2a420570d4f528205e258ff27e8f
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1849396
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- TPC powergating should be done before
calling gk20a_enable_gr_hw.
gk20a_enable_gr_hw() issues a GR engine reset.
Without this fix, enabling 1 TPC from each PES
causes ctxsw timeout error while running GFX Benchmark.
- Adds valid tpc-pg mask for 1/2/3/4 active TPC configs.
TPC Config - TPC-MASK
4 TPC configuration - 0x0
3 TPC configuration - 0x1/0x2/0x4/0x8
2 TPC configuration - 0x5/0x9/0x6/0xa
- We should not write to gr_fe_tpc_pesmask_r()
as part of TPC-PG sequence. This register is for
debug purpose only.
Bug 200442360
Change-Id: I6fbe1ad8fbc836ace8cbaf00ec3d21a12c73e0bd
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809772
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- Defined FALCON_ID_GSPLITE for GSP falcon.
- Created variable gsp_flcn of struct nvgpu_falcon
for GSP falcon & registered to falcon module to access
falcon functions.
- Created HAL file gsp_gv100.c/h for GSP.
- Modified Makefile & Makefile.sources files to include
gsp_gv100 HAL file.
- Enabled GSP falcon support for GV100 by registering
to common falcon module.
- Defined function gv100_gsp_reset() & assigned to
falcon reset as GSP engine reset.
- Updated falcon HAL init code not to return error
if requested falcon is not supported, instead log
the info and return non-error.
JIRA NVGPU-1160
Change-Id: Ice032cf443ae87254375265628b3c022f41544cd
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804551
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
tsg_gk20a.c doesn't depend on any specific hardware, so move it to the
common directory.
Rename the posix tsg file to posix-tsg.c.
Jira NVGPU-967
Change-Id: I6e8908a8f6cf43132db8dffe3a99e424e4f764b1
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1821509
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
-Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c
method nvgpu_init_pmu_support()
-Modified nvgpu_init_pmu_support() to init required interface
for PMU RTOS & does start PMU RTOS in secure & non-secure
based on NVGPU_SEC_PRIVSECURITY flag.
-Created secured_pmu_start ops under PMU ops to start PMU
falcon in low secure mode.
-Updated PMU ops update_lspmu_cmdline_args, setup_apertures &
secured_pmu_start assignment for gp106 & gv100 to support
modified PMU init sequence.
-Removed duplicate PMU non-secure bootstrap code from multiple
files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method
to handle non secure PMU bootstrap, reused this method
for need chips.
JIRA NVGPU-1146
Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1818099
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
-Created struct nvgpu_acr to hold acr module related member
within single struct which are currently spread across multiple structs
like nvgpu_pmu, pmu_ops & gk20a.
-Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members
-Created struct hs_acr to hold ACR ucode specific members like bootloader data
using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run.
-Created acr ops under struct nvgpu_acr to perform ACR specific operation,
currently ACR ops were part PMU which caused to have always dependence
on PMU even though ACR was not executing on PMU.
-Added acr_remove_support ops which will be called as part of
gk20a_remove_support() method, earlier acr cleanup was part of
pmu remove_support method.
-Created define for ACR types,
-Ops acr_sw_init() function helps to set ACR properties
statically for chip currently in execution & assign ops to point to
needed functions as per chip.
-Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr
function to alloc blob space.
-Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde
based on interfaces used to bootstrap ACR ucode.
-Created function gm20b_bootstrap_hs_acr() function which is now common
HAL for all chips to bootstrap ACR, earlier had 3 different function for
gm20b/gp10b, gv11b & for all dgpu based on interface needed.
-Removed duplicate code for falcon engine wherever common falcon code can be used.
-Removed ACR code dependent on PMU & made changes to use from nvgpu_acr.
JIRA NVGPU-1148
Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813231
GVS: Gerrit_Virtual_Submit
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
gk20a_init_gr_prepare() is called only when initializing GR from reset.
In those cases there is no need to disable GRFIFO access. Remove the
corresponding code. It also gets rid of one extra dependency to MC
registers.
JIRA NVGPU-954
Change-Id: I935e65f236e0f29ab224787d20e017d8c67e69e2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822309
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This reverts commit c5810a670d367ae1dc405fcc3108e11265df34bb.
Bug 2400508
Jira VQRM-4806
Bug 200447406
Bug 2331747
Change-Id: Ie2a2c21f9285ff0349c7033fae24766a7117b462
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1837223
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
gk20a/hal.c depends on HAL init functions in all chips. But all chips
also depend on gk20a. That creates a circular dependency. In order to
solve the above, move gpu_init_hal and gk20a_detect_chip to
common/init/hal_init.c. These methods are declared in
include/nvgpu/hal_init.h. Also, the above methods are renamed to
nvgpu_init_hal and nvgpu_detect_chip respectively.
Jira NVGPU-613
Change-Id: Ib0df90287d4491571e4751475739b75fabd1041b
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1827576
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
added hal layer for SM exception mask handling for
taking care of vitualization case.
Jira VQRM-4806
Bug 200447406
Bug 2331747
Change-Id: Ia44778a2e41c1a508c48026b8dee285966f1a544
Signed-off-by: aalex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1816284
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch constructs clk_arbiter specific code for gp10b as well as
gv11b and does the necessary plumbing in the clk_arbiter code. The
changes made are as follows.
1) Constructed clk_arb_gp10b.* files which add support for clk_arb
related HALS including the nvgpu_clk_arb_init and nvgpu_clk_arb_cb.
This doesn't have support for debugfs nor the VFUpdateEvent yet and
consequently no support for arb->notifications.
2) Added gpcclk specific variables corresponding to every gpc2clk in
a given clk_arb related struct.
3) Linux specific support_clk_freq_controller is assigned true in
platform_gp10b.c and platform_gv11b.c files.
4) Incremented the clk_arb_worker.put atomic variable during
worker_deinit so as to allow the worker thread to be stopped.
5) Added the flag clk_arb_events_supported as part of struct
nvgpu_clk_arb. This flag is used to selectively account for the extra
refcounting present in OS specific code i.e.
nvgpu_clk_arb_commit_request_fd. For igpus, the extra refcount is
reduced during nvgpu_clk_arb_release_completion_dev.
Bug 2061372
Change-Id: Id00acb106db2b46e55aa0324034a16a73723c078
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774281
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Fix violations where a variable of type non-boolean is used as a
boolean in nvgpu/gk20a/gr_gk20a.c
Changed instances of BIT() to BIT32() in nvgpu/gk20a/gr_pri_gk20a.h
JIRA NVGPU-646
JIRA NVGPU-1019
Change-Id: I1784f8509cc87d65ac1c8c95796a4c8876626b48
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1811925
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
1) Move channel_sync_gk20a.* from gk20a/ to common/ directory as they
donot program any hardware registers. Also as an add-on rename
channel_sync_gk20a.* to channel_sync.* and update the headers
in required files.
2) Rename the struct gk20a_channel_sync to struct nvgpu_channel_sync. Also,
corresponding syncpt and semaphore versions of the struct alongwith
related methods are renamed by removing "gk20a" from their names and
adding "nvgpu".
3) Add misra-c cleanups
Jira NVGPU-1086
Change-Id: I4e0e21803ca3858dd7a5fc4d2454dba1f1bfcecd
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812594
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
After fecs watchdog gets triggered, system will not
do anything useful as it cannot context switch. Dumping
falcon stats will help debug the issue since s/w is
not triggering recovery.
Bug 2113657
Change-Id: I03ccd5ad7c03daac0581775dc615174cc0e77328
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812720
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Whenever wait for empty HAL is called, GR is out of reset. Check for
GR being out of reset was adding an extra dependency to MC, so just
remove that code.
JIRA NVGPU-964
Change-Id: Ic6d607fd2e29359a67896973517d8de6542029e9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813522
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Move implementation of MC HAL to common/mc. Also bump gk20a
implementation to gm20b.
gk20a_mc_boot_0 was used via a HAL, but we have only one possible
implementation. It also has to be anyway called directly to detect
which HALs to assign, so make it a true common function.
mc_gk20a_handle_intr_nonstall was also used only in os/linux/intr.c
so move it there.
JIRA NVGPU-954
Change-Id: I79aedc9158f90d578db0edc17b714617b52690ac
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813519
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
MISRA 21.2 states that we may not use reserved identifiers; since
all identifiers beginning with '_' are reserved by libc, the usage
of '__' as a prefix is disallowed.
Handle the 21.2 fixes for nvgpu_mem.c and mm.c; this deletes the
'__' prefixes and slightly renames the __nvgpu_aperture_mask()
function since there's a coherent version and a general version.
Change-Id: Iee871ad90db3f2622f9099bd9992eb994e0fbf34
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813623
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Move the contents of the gk20a/gk20a.h to <nvgpu/gk20a.h>.
In order to enable a smooth transition, include <nvgpu/gk20a.h> in the
current file (i.e. gk20a/gk20a.h).
Jira NVGPU-597
Change-Id: I998da0e7688a5827e2974e88ab8ad6849083aa4a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813140
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Fix MISRA 10.3 violations in mclk_gp106.c. Cleanup cases where values
were being assigned to narrower types.
Changes in mclk_gp106.c required updates to other files to resolve
errors and prevent introducing new violations.
JIRA NVGPU-647
Change-Id: Ifdb03ad41d9dbf05dbcf79494ae8565fff6ee083
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809366
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Debug page was allocated and programmed to HUB MMU in GR code. This
introduces a dependency from GR to FB and is anyway the wrong place.
Move the code to allocate memory to generic MM code, and the code
to program the addresses to FB.
Change-Id: Ib6d3c96efde6794cf5e8cd4c908525c85b57c233
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801423
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Vidmem size query was in mm_xxx.c. It involves reading a register from
FB, so move the query to FB HAL.
JIRA NVGPU-1063
Change-Id: I30dfd2c4fdcdd6c841f85aaab7431d52473759bd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801425
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
NVHSCLK registers used by NVLINK IP are part of dev_top
hardware headers. This patch adds "Top" as a separate
unit and exposes HALs to access dev_top registers. The top
unit contains top-level configuration information and any
extra registers or features that do not fit into another block's
feature set.
JIRA NVGPU-1053
JIRA NVGPU-966
Change-Id: Id9a43d4a1c5397959897a242ea97a39a1b95f916
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803632
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
NVGPU_DBG_GPU_IOCTL_REG_OPS currently doesn't return if the ctx was
resident in engine or not.
Regops are broken down into batches of 128 and each batch is executed
together. Since there only 32 bits were available in IOCTL args, returning
is ctx was resident isn't possible for all batches.
Hence return if the ctx was resident for the first batch.
Bug 200445575
Change-Id: Iff950be25893de0afadd523d4ea04842a8ddf2af
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812975
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add fecs trace debugfs initialization as an os op. The
debugfs nodes are set up for gpu versions which call
gk20a_fecs_trace_init().
JIRA NVGPU-602
Change-Id: I606ec31acbf04f633500be4c342db32f3f537794
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812449
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
page_idx is an element of the struct nvgpu_semaphore_pool, defined in
include/nvgpu/semaphore.h file.
page_idx can not be negative so changing it from int to u64 and its
related changes in various files.
This also fixes MISRA 10.4 violations in these files.
Jira NVGPU-992
Change-Id: Ie9696dab7da9e139bc31563783b422c84144f18b
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801632
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This is a big cleanup of return types across a number of modules in the
nvgpu driver. Many functions were returning u32 but using negative
return codes. This is a MISRA 10.3 violation by assigning signed values
to a u32.
JIRA NVGPU-647
Change-Id: I59ee66706321f5b5b1a07ed8c24b81583e9ba28c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810743
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for calls to nvgpu_readl.
JIRA NVGPU-677
Change-Id: I432197cca67a10281dfe407aa9ce2dd8120030f0
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807528
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations caused by
include guards by renaming them to follow the convention,
'NVGPU_PARENT-DIR_HEADER_H'
JIRA NVGPU-1028
Change-Id: I478be317d067a75cdc8cb7fe9577a66d06318a11
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813068
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
| |
As part of MISRA 17.7 fixes for a different GPU, the tlb_invalidate
needs to return an error code.
Change-Id: I3b8b9f112708c17457855dd1fb151168791bc6bf
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810106
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add gops.ltc.get_cbc_base_divisor() HAL to get CBC base divisor value
Bug 2180284
Jira NVGPUT-12
Change-Id: Ifec5e050723a71c2fa735652cb5063f80aaecf60
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805469
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add compbit_backing_size variable to struct gr_gk20a to hold
compbit backing size
And copy this value in respective init_comptags() HAL
Bug 2180284
Jira NVGPUT-12
Change-Id: I3c1bea3a6b7ed39a1e901357e6e062dbf45b747b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776028
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces by introducing the braces.
JIRA NVGPU-671
Change-Id: Ie4bd8bffdafe6321e35394558dc9559f9c2d05c2
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797689
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Below regops HALs are not being called from anywhere, so remove them
gops.regops.get_runcontrol_whitelist_ranges()
gops.regops.get_runcontrol_whitelist_ranges_count()
gops.regops.get_qctl_whitelist_ranges()
gops.regops.get_qctl_whitelist_ranges_count()
HAL gops.regops.apply_smpc_war() is unimplemented for all the chips, and it
was originally only needed for gk20a which is not unsupported
So remove this HAL and its call too
Jira NVGPU-620
Change-Id: Ia2c74883cd647a2e94ee740ffd040a40c442b939
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813106
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Allocation of usermode submit buffers is not chip specific but is
operating system specific; the API belongs to the os_channel layer, not
in the fifo ops HAL.
Bug 200145225
Change-Id: I90adb47103ab4b2e888c3db191d78ceda35e777d
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812287
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
channel_gk20a is clear from chip specifics and from most dependencies,
so move it under the common directory.
Jira NVGPU-967
Change-Id: I41f2160b96d4ec84064288ecc22bb360e82352df
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810578
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for calls to nvgpu_mutex_init and
improves related error handling.
JIRA NVGPU-677
Change-Id: I609fa138520cc7ccfdd5aa0e7fd28c8ca0b3a21c
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805598
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Move linux dependencies and CONFIG_DEBUG_FS to linux specific
code from common driver for gp106 clk debugfs. There is no
code change in functions moved from gp106/clk_gp106.c.
It uses nvgpu_os_linux_ops to add gp106 specific clk debugfs
ops. The linux specific part of nvgpu driver uses this op
to initialize gp106 clk debugfs.
As gv100 also uses gp106 clk debugfs ops, set up os ops for
gv100.
JIRA NVGPU-603
Change-Id: Ib55ef051b13366e5907e1d05376bb18bf42c8653
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797904
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces by introducing the braces.
JIRA NVGPU-671
Change-Id: Iedac7d50aa2ebd409434eea5fda902b16d9c6fea
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797695
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces by introducing the braces.
JIRA NVGPU-671
Change-Id: Icdeede22dd26fd70fae92aa791d35b115ef49e32
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797691
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Adding a comptag_mem_deduct in the platform_gk20a has certain problems:
1) It's not really convenient for platform users to configure it.
2) All products using the same GPU have to share the same configuration.
So this patch moves this comptag_mem_deduct from struct platform_gk20a
to struct gr_gk20a (per device). And it adds an sysfs node for products
or platform users to easily configure from user space.
Note: The comptag memory will not be allocated until the GPU driver goes
through the final poweron routine. So the user space has a small window
to configure this sysfs node.
Bug 2327574
Bug 2284925
Change-Id: Ie7d00b082704e422645c0ea254b59e22f9fc3b7f
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810334
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
| |
HUB and GPC MMU debug modes were set in the same function. This
introduced a dependency from FB code to GR registers. Split setting
of GPC MMU debug mode to GR HAL.
Change-Id: I003446f9dfa147f526bd01d3b6130f4037d9b183
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801420
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch corrects a handful of MISRA 10.1 violations involving
illegal arithmetic operations (e.g. bitwise OR) on boolean values:
* fix to status handling in regops validation code
* fix to debugger event handling in gr code
* fix to entries_left tracking in runlist construct code
* fix to verbose channel dumping and reset tracking in fifo code
JIRA NVGPU-650
Change-Id: I3c3d9123b5a0e08fc936d0e63d51de99fc310ade
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810957
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
g->clk_arb is currently initialized as a part of gk20a_finalize_poweron().
Any subsequent call to gk20a_finalize_poweron reinitializes the clk_arb
and leading to memory leaks. This is resolved by protecting the
g->clk_arb initialization with a mutex clk_arb_enable_lock in struct
gk20a. We skip initializing the g->clk_arb if its not NULL.
Bug 2061372
Change-Id: I59158e0a5e4c827fdbd6d9ea2d04c78d0986347a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1811650
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Currently, clock arbiter code is extensively using dgpu specific
implementation. This patch restructures the clk_arbiter code and moves
gp106 specific code into HAL. Following changes are made in this patch
1) clk_domain_get_f_points is now invoked via HAL for gp106 i.e.
g->ops.clk.clk_domain_get_f_points.
2) moved nvgpu_clk_arb_change_vf_point and other related static
functions to clk_arb_gp106.c.
3) Instead of only checking if get_arbiter_clk_domain is empty, a
check for support_clk_freq_controller is also added. This is to enable
the clk_arbiter based on support from both the OS and the chips.
Bug 2061372
Change-Id: I65b0a4e02145a86fbbfb420ed591b1fa3c86f6dc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774279
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Moved the SM_MASK_TYPE variable from GR to
TSG struct. SM error registers are context based.
In dbg_session IOCTL to SET_SM_MASK_TYPE, kernel
code iterate the TSG associated with first channel
and set the mask_type to that context.
Bug 200412641
Change-Id: Ic91944037ad2447f403b4803d5266ae6250ba4c9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809322
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Debug fused chips do not have production signature. Use debug
signature for memory unlock binary. Requires also exporting a HAL
for checking debug mode from PMU.
Bug 200445202
Change-Id: I7f88ed6db2fe1c614fe9d4074dbf974c3817f453
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809225
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- Remove the usage of NVGPU_CTXSW_FILTER_ISSET splattered
across nvgpu, and replace with a MACRO defined in common code.
The usage is still inside Linux, but this helps the
subsequent unification efforts, e.g. to unify the fecs trace
path.
- Remove "uapi/linux/nvgpu.h" from common code.
EVLR-3078
Change-Id: I60b0e1627576a4b255671d58530d8c773ea6154c
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803210
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Convert linux nvgpu ctxsw tags type of the form
of NVGPU_CTXSW_TAG_* into common nvgpu ctxsw tags
type of the form of NVGPU_GPU_CTXSW_TAG_*
EVLR-3078
Change-Id: I337487722c103c05003457f74ad6e05bf3bd38fc
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803209
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- Remove the usage of nvgpu_ctxsw_trace_entry splattered
across nvgpu, and replace with a struct defined in common code.
The usage is still inside Linux, but this helps the
subsequent unification efforts, e.g. to unify the fecs trace
path.
- Remove "asm/barrier.h" as "nvgpu/barrier.h" is already
included.
EVLR-3078
Change-Id: Iabfb105b891b0078ed326a8047ef14ebe1888cf2
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803208
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This reverts commit 96d53bff8598a44fcec3f2492c8ec630d71d5dd0.
Bug 2330230
Change-Id: Icd146e80bac0425fcb59f266f1d3582c40211739
Signed-off-by: Daniel Fu <danifu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804753
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
|