| Commit message (Collapse) | Author | Age |
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Allow platforms to choose whether or not to have unified GPU
VA spaces. This is useful for the dGPU where having a unified
address space has no problems. On iGPUs testing issues is
getting in the way of enabling this feature.
Bug 1396644
Bug 1729947
Change-Id: I65985f1f9a818f4b06219715cc09619911e4824b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1265303
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Remove the special VMA that could be used for allocating fixed
addresses. This feature was never used and is not worth maintaining.
Bug 1396644
Bug 1729947
Change-Id: I06f92caa01623535516935acc03ce38dbdb0e318
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1265302
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Cleanup and simplify the gk20a_init_vm() function to ease the
implementation of a platform dependent address space unification
decision.
Bug 1396644
Bug 1729947
Change-Id: Id8487d0e3d3c65e3357e3528063fb17c8a85f7da
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1265301
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The basic structure of this patch is to make the small page allocator
and the large page allocator into pointers (where they used to be just
structs). Then assign each of those pointers to the same actual
allocator since the buddy allocator has supported mixed page sizes
since its inception.
For the rest of the driver some changes had to be made in order to
actually support mixed pages in a single address space.
1. Unifying the allocation page size determination
Since the allocation and map operations happen at distinct
times both mapping and allocation of GVA space must agree
on page size. This is because the allocation has to separate
allocations into separate PDEs to avoid the necessity of
supporting mixed PDEs.
To this end a function __get_pte_size() was introduced which
is used both by the balloc code and the core GPU MM code. It
determines page size based only on the length of the mapping/
allocation.
2. Fixed address allocation + page size
Similar to regular mappings/GVA allocations fixed address
mapping page size determination had to be modified. In the
past the address of the mapping determined page size since
the address space split was by address (low addresses were
small pages, high addresses large pages). Since that is no
longer the case the page size field in the reserve memory
ioctl is now honored by the mapping code. When, for instance,
CUDA makes a memory reservation it specifies small or large
pages. When CUDA requests mappings to be made within that
address range the page size is then looked up in the reserved
memory struct.
Fixed address reservations were also modified to now always
allocate at a PDE granularity (64M or 128M depending on
large page size. This prevents non-fixed allocations from
ending up in the same PDE and causing kernel panics or GMMU
faults.
3. The rest...
The rest of the changes are just by products of the above.
Lots of places required minor updates to use a pointer to
the GVA allocator struct instead of the struct itself.
Lastly, this change is not truly complete. More work remains to be
done in order to fully remove the notion that there was such a thing
as separate address spaces for different page sizes. Basically after
this patch what remains is cleanup and proper documentation.
Bug 1396644
Bug 1729947
Change-Id: If51ab396a37ba16c69e434adb47edeef083dce57
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1265300
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Make sure that map_offset is set to the fixed map address or 0)
before determining PTE size. Then use map_offset instead of
offset_align for computing the PTE size since offset_align
could be either an alignment ora fixed mapping offset.
Also is the minimum of the buffer size and the buffer alignment
for computing page size. This is necessary is the GMMU is doing
page gathering (i.e the buffer does not appear as a continguous
IOMMU range to the GPU). Is such cases a large page sized buffer
may be made up of a bunch of discontiguous 4k pages.
Bug 1396644
Bug 1729947
Change-Id: I6464ee6a4ccab2495ccb31cd1ddf1db467d2b215
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1271359
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use hardware headers instead of hardcoded register numbers in priv
ring. This required updating the priv ring headers to add all the
registers and fields needed.
Incidentally this also gets rid of a lot of GPC priv ring registers
as they're not used in our code.
Also delete duplicate prints for the same information. We were
dumping GPC error also in gk20a_pbus_isr(), and we dumped master
information twice.
Dump status of each GPC separately instead of supporting only GPC0.
Change-Id: Ic50817ecc50892618fa27947fa83b05148b2cd6a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1295481
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
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Clear error address and code from timer registers. This allows
following errors to report correctly.
Change-Id: I9845ce77347ea7b9231e33f4164098cbb8694ba3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1294682
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
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We did not follow the proper sequence to reset priv ring on error.
Instead we just re-enabled priv ring, which does not reset anything.
Rename the gk20a_reset_priv_ring() to gk20a_enable_priv_ring() to
indicate its proper use. Add another gk20a_reset_priv_ring() which
actually resets priv ring properly.
Change-Id: Ied74465b1215daa447a565b7e9cafef7fbe67d1b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1294681
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Devfreq and gpcclk require GPU v/f tables for registering correctly.
Fix this by deferring the nvgpu_probe if GPU-DVFS is not completely
initialized. Change applicable to kernels with Common Clock Framework
enabled.
Bug 200233943
Change-Id: I82dadc1b0970d47e839d6bec935330966402e93b
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: http://git-master/r/1280832
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Allow NA_GPCPLL to be enabled on T210 K4.4
Bug 200233943
Change-Id: I5ea0b9d1de51b510f5c6671339dee2953bf1ec80
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: http://git-master/r/1280829
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This reverts commit a918003694984b6fca9e6b6c07fd7cdf3503055e.
Change-Id: Idf39cc0946c5c4df82c7c4b6afa225b1f8d5a923
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: http://git-master/r/1280827
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Instead of checking if a job is complete, only check that channel is
making progress by checking its gp_get is advancing.
This will make the watchdog conservative. Previously a whole job had
x seconds to complete. Now channel has x seconds to get host to
consume each push buffer segment.
Bug 1861838
Bug 200273419
Bug 200263100
Change-Id: I70adc1f50301bce8db7dac675771c251c0f11b70
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1294850
Reviewed-by: Automatic_Commit_Validation_User
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To test semaphore-related bugs with igpus, add a debugfs node called
"disable_syncpoints" to override the "has_syncpoints" platform flag.
This makes job synchronization use semaphores, for example.
NVGPU_GPU_FLAGS_HAS_SYNCPOINTS is still reported in gpu characteristics
if the platform supports that, because it is filled in during boot.
Jira NVGPU-18
Change-Id: I58c815f896a6054df472f571012c239f1478bf07
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1293972
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Update zcull and perfmon buffer pointers in context
header through function pointers.
JIRA GV11B-48
Change-Id: Iaa6dd065128cb0c39e308cecf17b9d68a826d865
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1291850
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Remove including gk20a.h from pmu_gk20a.h. This causes a fallout
as some #includes were missing.
gr_gp10b.h uses mem_desc, but did not include mm_gk20a.h. Add the
include.
Including mm_gk20a.h in gr_gp10b.h causes recursive include, as
mm_gk20a.h has some gr defines. Move the defines to gr_gk20a.h to
remove the dependency.
gr_ctx_gk20a.h used struct gk20a pointers, but did not forward
declare it. Add a forward declaration.
gr_gk20a.h uses dbg_session_gk20a, but was missing forward
declaration.
gr_gk20a.h did not include nvgpu.h but it uses preemption types from
that header. Add include.
Change-Id: I2168e2303b55e0d187b816bcb26f37c8af1649ba
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1283717
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Semaphore acquire timeout is configured to half of watchdog timeout.
This is too short, so bump it to 80% of watchdog timeout.
Bug 200261389
Change-Id: Ie906ea3d3520c2e3f547cff7ffbb1e37459e6d2f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1283623
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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API gk20a_wait_for_idle() right now always waits for
0 usage count
But in case railgating is disabled through sysfs,
usage count will never get to 0
Hence in this case we should wait for usage count
of 1
If platform->user_railgate_disabled is set,
keep target usage count of 1, otherwise keep
target usage count as 0
Bug 200260926
Change-Id: I1a80621ca61babbd6566989dc09a7b20670c649c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1291421
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Make the GPU bind and rebind operations work when the driver
is idle. This required two changes.
1. Reset the GPU before doing SW init for PCI GPUs. This clears
the SW state which may be stale in the case of a rebind attempt.
2. Cleanup the interrupt enable/disables. Firstly there was one
place where nvgpu would accidentally disable the stalling
interrupt twice when the stalling interrupt and non-stalling
interrupt are the same. Secondly make sure when exiting nvgpu
that the interrupt enable/disables are balanced. Leaving the
interrupt in the -1 disable state means that next time the
driver runs interrupts never quite get enabled.
Bug 1816516
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1287643
Reviewed-on: http://git-master/r/1287649
(cherry picked from commit aa15af0aae5d0a95a8e765469be4354ab7ddd9f8)
Change-Id: I945e21c1fbb3f096834acf850616b71b2aab9ee3
Reviewed-on: http://git-master/r/1292700
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add a full GPU reset function to the XVE block. This allows
the driver to reset the GPU (except the XVE and XP interfaces)
to clear the GPU's state.
This is necessary for the GPU rebind to work. The state of the
GPU needs to be cleared before the new driver instance can work.
Bug 1816516
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1287642
Reviewed-on: http://git-master/r/1287648
(cherry picked from commit 7e751c0eb2c0f7d9d0b2020600c33fc8b4381878)
Change-Id: Ie2b721bf1b40acbab34de2436dea4e70d33b5611
Reviewed-on: http://git-master/r/1292698
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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When removing the driver nodes make sure to use the correct class
to free the dev-node.
Bug 1816516
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1287641
Reviewed-on: http://git-master/r/1287647
(cherry picked from commit acf97306b4950d8397bb511784b3391a3530ff77)
Change-Id: I983a2106eff6f4839c52a2e16bdd036facb501c0
Reviewed-on: http://git-master/r/1292697
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Prints out Timeslice value, Interleave level, Graphics preemption
mode and compute preempt mode along with chid, tsgid, pid.
Enable it with setting dbg_mask with 8192
Bug 1855710
Change-Id: I60efef9810587f8fedd4e2ba62ba67d06d84faea
Signed-off-by: Mihir Thakkar <mthakkar@nvidia.com>
Reviewed-on: http://git-master/r/1287141
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gk20a_tegra_dump_debug() is set in a platform where host1x support
is not enabled.
Change-Id: Ic57f9081d75be976a092827b253cb2a195d8f16d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1284336
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Copy and restore golden context correctly with
context header. Removed parallel fecs bind method,
which can cause issues for context in execution.
Also added function pointer to freeing context
header during channel context free.
Bug 1834201
Change-Id: I7962d68338d5144f624375ab81436e86cb31051e
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1275201
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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We right now compare requested value to the last
freq value. Last freq value is always a rounded
value, whereas requested value need not be a
rounded value
Hence it is incorrect to compare requested value
to last freq value
Fix this by comparing rounded value to last_freq
Change-Id: I7c6ea7c4e57105598c9af75efe70016b7fa8038b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1287360
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The soc tegra headers are unified and moved all the content of
linux/tegra-soc.h to the soc/tegra/chip-id.h to have the
single soc header for Tegra.
Change-Id: I281e19dd3eb1538b8dfbea4eb0779fb64d1fcffa
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1288365
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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bug 200269171
Updating PMU firmware to fix voltage raise when switching mclk to 810mhz
with CLFC and MSCG enabled. The fix is to make sure that clock domain is
not evaluated in CLFC if MSCG has engaged anytime after the previous
evaluation
Change-Id: I2b6979ed3361f47273f2643c27c005deac49dc8b
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1286437
(cherry picked from commit dbfccb42614ec9361628b3c3427a65d3fe908597)
Reviewed-on: http://git-master/r/1287461
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The recently added refcount tracking support had a slight mishap in
refactoring some printks. Fix a typo to make the support compile again
when enabled.
Bug 1826754
Change-Id: Ifd76d644932fa219751db82a0beb3c8482ea68c3
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1285922
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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update perfmon id for t19x in get_perfmon_id().
JIRA GV11B-30
Change-Id: I7c76b49cc47f8de1e6fa9492e2986830dcff901f
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1284763
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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pmu_queue_head() & pmu_queue_tail() are updated
to use gops to include chip specific PMU queue
head/tail registers.
JIRA GV11B-30
Change-Id: I9c3d6a4601ba2767f9ada95642052044e2b79747
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1283266
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Use the timers API in the gk20a code instead of Linux specific
API calls.
This also changes the behavior of several functions to wait for
the full timeout for each operation that can timeout. Previously
the timeout was shared across each operation.
Bug 1799159
Change-Id: I2bbed54630667b2b879b56a63a853266afc1e5d8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1273826
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-GV11B PMU ucode is added in nvgpu supported
ucodes.
-PMU INIT msg structure(v4) is added
JIRA GV11B-30
Change-Id: Ifced87b1ca2692c277ae11f562cb36b328da3fe4
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1259274
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Added infrastructure for supporting
new zbc features
JIRA GV11B-9
Change-Id: Id8408348759488e8b0393dd89dd0faacfb111f01
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1235525
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Hold debug_s->ioctl_lock for all debug session
IOCTLs to prevent multi-threaded user space
IOCTL calls
debug session IOCTL calls are not thread-safe
and hence this serialization is required
Bug 1832267
Change-Id: I847ac951601d4f0093546b592bdb8c8f00185317
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1286436
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In gk20a_pm_shutdown(), we currently do not wait
for IOCTLs or threads in progress and directly
proceed with shutdown sequence
This can cause random hangs during system shutdown
Fix this by calling gk20a_wait_for_idle() after
we disable runtime PM in gk20a_pm_shutdown()
Bug 200260926
Change-Id: I0f06ba9232263fcb09c6e9d246be89deec053d44
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1286522
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- lpwr_debug node to dump current pstate &
PG status.
JIRA DNVGPU-165
Change-Id: I8240aea7145c3016946f4322fe0781d78ee2ec73
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1253509
(cherry picked from commit 4852997df5b89aeb8544ed9092ccc9ee8b8c375e)
Reviewed-on: http://git-master/r/1271618
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Added HAL support to get current
pstate from clk_arb
Note - This function is inherently unsafe to call while
arbiter is running arbiter must be blocked
before calling this function
JIRA DNVGPU-165
Change-Id: I4e9f5eba7739280bddd9ee661fd314288c129516
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1286378
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- with help of WRITE_ONCE() & ACCESS_ONCE()
make sure variable pmu->mscg_stat read/write goes through
without optimization
- Added WRITE_ONCE() define for kernel-3.18 version & below
to support backward compatibility
issue: inconsistencies on getting MSCG to trigger consistently in P5
due to a lack of memory barrier around and volatile accesses to the
variable pmu->mscg_stat
JIRA DNVGPU-71
Change-Id: I04d30493d42c52710304dbdfb9cb4a1e9a76f2c0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1252524
(cherry picked from commit 8af7fc68e7ab06a856ba4ef4e44de7336682361b)
Reviewed-on: http://git-master/r/1271614
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Print process name if we fail submit due to gk20a_busy()
failure
This is helpful in debugging and to know the process name
submitting jobs to nvgpu after system shutdown was
already triggered
Bug 200262275
Change-Id: I34d8c07fc96fd5556afa982bfd56f7f3964449d0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1284113
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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When gpu host is executing a context, there should not be any calls
to fecs that can change the current context in execution. For some
reason legacy fmodels are calling fecs method to golden
context restore while loading golden context for new channel.
This call is not required and should not be called. Only first
time during golden context creation, fecs methods like bind can be
called and it is pretty safe to do.
Bug 1834201
Change-Id: Ia6178e875e3ac37fb1cf10e27976c26b9a02c56f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1284512
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Setting timeslice for virtualized case was not effective,
because both ioctls NVGPU_TSG_IOCTL_SET_TIMESLICE and
NVGPU_SCHED_IOCTL_TSG_SET_TIMESLICE were calling the
native function to set TSG timeslice.
- Fixed wrapper function to call HAL
- Defined HAL function for "native" set TSG timeslice
- Also, properly update timeout_us in TSG context, in
virtualized case.
This change also moves the min/max bounds checking for
tsg timeslice into the native function implementation.
There is no sysfs node for these parameters for vgpu,
as RM server is ultimately responsible for this check.
Bug 200263575
Change-Id: Ibceab9427561ad58ec28abfff0c96ca8f592bdb9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1283180
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Added sysfs node to control RPPG/MSCG enable/disable
- RPPG is controlled with elpg_enable node, same node used to
control ELPG.
- MSCG is controlled with mscg_enable node
JIRA DNVGPU-71
Change-Id: I1a1b33d7425c25c9cfd466f7cabce08f3152326d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1251611
(cherry picked from commit eaf255f2dd3d20c071714dd509a785e9172399bf)
Reviewed-on: http://git-master/r/1274645
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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HAL to query LPWR feautre's RPPG/MSCG support
based on current pstate configured.
JIRA DNVGPU-71
Change-Id: I58a34c6dca68e3eb76e222bd781578bf682eac34
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1283916
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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The timeslice values that can be selected for a particular channel/tsg
are bounded by a static min/max. This change introduces two sysfs
nodes that allow these bounds to be configured from userspace.
min_timeslice_us
max_timeslice_us
Bug 200251974
Bug 1854791
Change-Id: I5d5a14225eee4090e418c7e43629324114f60768
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1280372
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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When kernel adds patches to a context, kernel needs to update
the patch count in order for FECS to pick up the new patches.
Previously patching was done only at the context creation
time. Now patching is used also when changing preemption mode,
but the patches did not take effect due to not updating count.
Update patch count every time we end patching of a context.
Bug 1852094
Change-Id: Ic2150741609d1d1956769e439ce1c5f2edcacb84
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1280424
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Reorganize the HW headers of gk20a. The headers are moved to a
new directory:
include/nvgpu/hw/gk20a
And from the code are included like so:
#include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
This is the first step in reorganizing all of the HW headers for
gm20b, gm206, etc. This is part of a larger effort to re-structure
and make the driver more readable and scalable.
Bug 1799159
Change-Id: Ic151155cbc2e6f75009f2d9d597b364a1bed2c4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1244790
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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If enabled, track actions (gets and puts) on channel reference counters.
Dump the most recent actions to syslog when
gk20a_wait_until_counter_is_N gets stuck when closing a channel.
GK20A_CHANNEL_REFCOUNT_TRACKING specifies the size of the action
history. Default is to disable completely, as this has some runtime
overhead.
Bug 1826754
Change-Id: I880b0efe8881044d02ae224c243a51cb6c2db8c1
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1262424
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Queue full message is not an error, it informs queue is full
& wait till it gets space in queue to upload pending request.
Bug 200256603
Change-Id: I14f4196b391cd54e1b9616f0555a5ce0856af428
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1260494
(cherry picked from commit e7360fb52b2030c9c68aa5ed06ecd7c32b47a8c5)
Reviewed-on: http://git-master/r/1271619
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Added mscg_transition_state to know
mscg allow/disallow status
- reused ELPG state transition defines
for mscg state transition
JIRA DNVGPU-71
Change-Id: Ie0214a174ceecf7e97a1086f53fd965b0b655d14
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1253508
(cherry picked from commit 726dde9cff1da38525518a91e756598a5ab71f73)
Reviewed-on: http://git-master/r/1271617
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- set pmu->pmu_state to PMU_STATE_ELPG_BOOTED
only for ELPG after PMU_STATE_ELPG_BOOTING
state
Bug N/A
Change-Id: I08480e2afd5a5050a903327b91e43b25780cdaf8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1254429
(cherry picked from commit d68f4f91796d1d98dbc1b5b24d526fe2e487966f)
Reviewed-on: http://git-master/r/1271616
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Added the thermal alarm notification handling for UMD
JIRA DNVGPU-130
Bug 200231080
Change-Id: I034c7b35a18a091ef7659ff992f1950576623cad
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1251760
(cherry picked from commit 9e66f2e2f7fbcab29e25c976c1d5fa29671afcd0)
Reviewed-on: http://git-master/r/1282084
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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