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path: root/drivers/gpu/nvgpu/gk20a
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* gpu: nvgpu: remove NVGPU_ALLOC_OBJ_FLAGS_* from common codeDeepak Nibade2017-11-10
| | | | | | | | | | | | | | | | | | | | In gr_gp10b_alloc_gr_ctx(), we use linux specific flags NVGPU_ALLOC_OBJ_FLAGS_* Since common code should be independent of linux specific code, define new flags NVGPU_OBJ_CTX_FLAGS_SUPPORT_* in common code and use them wherever needed Linux code will parse the user flags and send appropriate flags to g->ops.gr.alloc_obj_ctx() Also remove use of NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO since this seems to be deadcode anyways Jira NVGPU-382 Change-Id: Id82efe0d46ddc3e2c063610025ea57f283bc3510 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594452 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove NVGPU_ALLOC_GPFIFO_EX_FLAGS_* from common codeDeepak Nibade2017-11-10
| | | | | | | | | | | | | | | | | | | | | In gk20a_channel_alloc_gpfifo(), we use linux specific flags NVGPU_ALLOC_GPFIFO_EX_FLAGS_* Since common code should be independent of linux specific code, define new flags NVGPU_GPFIFO_FLAGS_SUPPORT_* in common code and use them in gk20a_channel_alloc_gpfifo() Linux code will parse the user flags and send appropriate flags to gk20a_channel_alloc_gpfifo() Jira NVGPU-381 Change-Id: Ibec51903b3407175fbba727208483b0dc36a5772 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594422 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove PTE kind logicSami Kiminki2017-11-10
| | | | | | | | | | | | | | | | Since NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL was made mandatory, kernel does not need to know the details about the PTE kinds anymore. Thus, we can remove the kind_gk20a.h header and the code related to kind table setup, as well as simplify buffer mapping code a bit. Bug 1902982 Change-Id: Iaf798023c219a64fb0a84da09431c5ce4bc046eb Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1560933 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add can_elpg check before elpg callSupriya2017-11-10
| | | | | | | | | | | | | This CL is as part of phased changes to support NO LSPMU Changes done is to add missing can_elpg check JIRA NVGPU-296 Change-Id: Ic4e5ebf208e08a0a9fce6b449f15a2e768281bb1 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1592629 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move sm_arch to nvgpu_gpu_paramsTerje Bergstrom2017-11-09
| | | | | | | | | | | | | Move sm_arch_* fields to nvgpu_gpu_params to make them available from common code without accessing Linux specific GPU characteristics. JIRA NVGPU-259 Change-Id: Ieffb2ddde81b27af53dfedb9fe3972d20757cc35 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593686 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Return GPU classes in get_litter_valueTerje Bergstrom2017-11-09
| | | | | | | | | | | | | Return GPU classes in HAL get_litter_value() instead of assigning them to GPU characteristics at HAL initialization time. JIRA NVGPU-259 Change-Id: Ife7a5cb38df3d33ce98a1caa43d3873fb1431234 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593683 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move fuse override DT handlingTerje Bergstrom2017-11-09
| | | | | | | | | | | | | | | | | | | | | | Move fuse override DT handling to Linux code. All the chip specific fuse override functions did the same thing, so delete the HAL and call the same function to read the DT overrides on all chips. Also remove the fuse override functionality from dGPU. There are no DT entries for PCIe devices, so it would've failed anyway. JIRA NVGPU-259 Change-Id: Iba64a5d53bf4eb94198c0408a462620efc2ddde4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593687 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use only contig CBCsAlex Waterman2017-11-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the LTC code to only use a contiguous CompBit Cache (CBC). The original code had two allocation schemes: "physical" and "virtual" - what they meant was virtually contiguous or physically contiguous. The CBC must appear contiguous to the GPU be it either from the IOMMU or from physical pages allocated contiguously. This change makes the CBC get allocated with the FORCE_CONTIGUOUS flag if the GPU is not IOMMU'able. If we can get contiguous mem with the IOMMU then no need to force the underlying pages to be contiguous. However, not all GPUs may be IOMMU'able so we do need to handle that case. Also delete the gk20a/ltc_gk20a.[ch] code. All that remained in these files was the CBC alloc functions which were completely chip agnostic. As a result these functions were consolidated and moved to common/ltc.c. Bug 2015747 Change-Id: I3f41961b4f94378b954e7502a6b27cf0bc627375 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593666 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Hard code regops max batch sizeTerje Bergstrom2017-11-08
| | | | | | | | | | | | | | | | | | We set the regops limit in common code to a hard coded value and access it in Linux code. Change the responsibility so that regops limit is set in Linux code in the GPU characteristics query to a hard coded value and just use the same hard coded value in the IOCTL limit check. JIRA NVGPU-259 Change-Id: I2f78a7ea8f1cb68a08633a2dc74b71b3b001e5c9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593682 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: define runlist level in common codeDeepak Nibade2017-11-08
| | | | | | | | | | | | | | | | | | | | | | | | | All the runlist levels NVGPU_RUNLIST_INTERLEAVE_LEVEL_* are declared in linux specific uapi header and used in common code But since common code should be linux-independent, move these uses out of common code Define new runlist levels NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* in common code and use them wherever required Add new API nvgpu_get_common_runlist_level() to get common runlist level of the form NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* from linux specific runlist level of the form NVGPU_RUNLIST_INTERLEAVE_LEVEL_* Jira NVGPU-259 Change-Id: Ic19239f0f8275683d5d1b981df530acd90e6dfbb Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594327 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove support for legacy mappingSami Kiminki2017-11-08
| | | | | | | | | | | | | | | | | | | | Make NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL mandatory for all map IOCTLs. We'll clean up the legacy kernel code in subsequent patches. Remove support for NVGPU_AS_IOCTL_MAP_BUFFER. It has been superseded by NVGPU_AS_IOCTL_MAP_BUFFER_EX. Remove legacy definitions to nvgpu_map_buffer_args and the related flags, and update the in-kernel map calls accordingly by switching to the newer definitions. Bug 1902982 Change-Id: Ie9a7f02b8d5d0ec7c3722c4481afab6d39b4fbd0 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1560932 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove use of linux specific powergate_mode flagDeepak Nibade2017-11-08
| | | | | | | | | | | | | | | | | | | | | In dbg_set_powergate(), we use flags NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE/ENABLE which are defined in linux specific uapi header Hence we need to remove those flags from common code Update dbg_set_powergate() to receive boolean flag to disable/enable powergate instead of NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE/ENABLE Also update corresponding HALs as per above change Jira NVGPU-259 Change-Id: I9c4eb30e29ea5ce0d8e25517a6a072fb9f0e92e5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594326 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable pbus intr for si/fpgaSeema Khowala2017-11-08
| | | | | | | | | | | | | | | | | Enable pri squash, fecs err and pri_timeout pbus interrupt for si and fpga platforms only. Bug 200350539 Change-Id: Id452edf92eac0209d3b43d98b3ff6efd0764e40a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1569590 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: spew err for pbus interruptSeema Khowala2017-11-08
| | | | | | | | | | | | | | | | | | | | | | | Spew err message for pri_squash, fecserr and pri_timeout pbus interrupts. If FECS_TGT is set in timeout_save_0, addr, write fields are not reliable. Also timeout_save_1 is unreliable. For both squash and timeout should have correct data most of the time. Even for FECS_TGT, a timeout for a read should indicate the correct transaction as Host only supports one read at a time. It's mostly just writes to FECS that have potentially incorrect information. Bug 200246808 Bug 200350539 Change-Id: I8a992d924ff6c740a8dacecaaaf4ef257756d01d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1568860 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Introduce queries for big page sizesTerje Bergstrom2017-11-08
| | | | | | | | | | | | | | Introduce query functions for default big page size and available big page sizes. Move initialization of GPU characteristics big page sizes to the GPU characteristics query function. JIRA NVGPU-259 Change-Id: Ie66cc2fbfcd88205593056f8d5010ac2539c8bc2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593685 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Store VBIOS version in g->biosTerje Bergstrom2017-11-08
| | | | | | | | | | | | | | Store VBIOS version in g->bios instead of GPU characteristics. This removes a few Linux dependencies from common code, because GPU characteristics is defined in Linux IOCTL header. JIRA NVGPU-259 Change-Id: I9aab3d37b7ca000edd59c92b8601a96ee288e2bb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593684 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix type defs in dbg_gpu_gk20a.hTerje Bergstrom2017-11-07
| | | | | | | | | | | | | | | | | dbg_gpu_gk20a.h used implictly definitions that it did not forward declare or #include definitions for. Also regops_whitelist fields were unused. The type itself is not defined anywhere. Delete the fields. Change-Id: I4b002247c67a4ce4cb54810720b0bbc06381bf83 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593681 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: drop user callback support in CEKonsta Holtta2017-11-07
| | | | | | | | | | | | | | | | | | | | | | | Simplify the copyengine code by deleting support for the ce_event_callback feature that has never been used. Similarly, create a channel without the finish callback to get rid of that Linux dependency, and delete the finish callback function as it now serves no purpose. Delete also the submitted_seq_number and completed_seq_number fields that are only written to. Jira NVGPU-259 Change-Id: I02d15bdcb546f4dd8895a6bfb5130caf88a104e2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1589320 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add elcg/blcg/slcg enabled checksDeepak Goyal2017-11-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Power features should be enabled only if s/w flags xxcg_enabled are set for corresponding features. These flags control whether feature should be kept disabled in the hardware or not. For disable case, register programming will happen for CG registers and they will be set to disabled. For ELPG, init command will be sent to PMU, but “ELPG_ALLOW” will not be sent to PMU. Also these flags can be modified using sysfs. These flags are noop if corresponding can_xxxg flags are set to flase. S/w flags can_xxxg tell the ability of platform to support a power feature and cannot be modified by syfs. Setting these flags to false will avoid any HW register write or init sequence for the power feature from executing. For ELPG, no commands will be sent to PMU. -g->elcg_enabled flag should not be modified here. It should be modified only by sysfs. This will be cleaned up in follow up implementation where debug session will have some kind of lock where it will keep power features disabled as long as it wants to. Debugger cannot rely on this flag to keep power management disabled as these flags can be changed from sysfs. Due to this issue someone can easily break debugging session by accidentally changing something in sysfs. Proper fix for this is being tracked in NVGPU-320 Bug 1982434 Change-Id: I660ef02491f4df9910bf4dea3561ac8a0838e1b1 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1587205 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: call destructor for boardobj and boardobjgrpThomas Fleury2017-11-06
| | | | | | | | | | | | | | | | | | Maintain a list of boardobj and boardobjgrp, so that we can free related objects when removing pmu support. A flag is added in boardobj so that the destructor can determine if it should free the object. This 'allocated' flag is false when the object is embedded into another structure, which should be freed through other means. JIRA EVLR-1959 Bug 200352099 Change-Id: I6a3ff3c57f7428dd145deacf98f2992a9be9796d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586596 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support tuning per-ch deterministic optsKonsta Holtta2017-11-06
| | | | | | | | | | | | | | | | Add a new ioctl NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS to adjust deterministic options on a per-channel basis. Currently, the only supported option is to relax the no-railgating requirement on open deterministic channels. This also disallows submits on such channels, until the railgate option is reset. Bug 200327089 Change-Id: If4f0f51fd1d40ad7407d13638150d7402479aff0 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1554563 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: define EVENT_IDs in common codeDeepak Nibade2017-11-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All the event ids NVGPU_IOCTL_CHANNEL_EVENT_ID_* are defined in linux specific user header uapi/linux/nvgpu.h and can't be used in common code Hence add new definitions of type NVGPU_EVENT_ID_* for all the events in common code and use them wherever required in common code For future additions to event ids, we need to update both NVGPU_IOCTL_CHANNEL_EVENT_ID_* and NVGPU_EVENT_ID_* fields Also add new API nvgpu_event_id_to_ioctl_channel_event_id() to convert common event_id of the form NVGPU_EVENT_ID_* to Linux specific event_id of the form NVGPU_IOCTL_CHANNEL_EVENT_ID_* Use this API in gk20a_channel/tsg_event_id_post_event() to get correct event_id Jira NVGPU-259 Change-Id: I15a7f41181fdbb8f1876f88bbcd044447d88325f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1591434 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: protect stacktrace.h include with configDeepak Nibade2017-11-06
| | | | | | | | | | | | | | | | struct stack_trace is protected with config GK20A_CHANNEL_REFCOUNT_TRACKING and hence protect linux/stacktrace.h header include in gk20a/channel_gk20a.h with same config Jira NVGPU-259 Change-Id: I365a4faa7eb071dd559e9b27fe03377dede7484d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1592603 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu_udelay and optimize do while loopSeema Khowala2017-11-06
| | | | | | | | | | | | | | | | | - For interrupt context, use nvgpu_udelay() instead of nvgpu_usleep_range() - Use while loop instead of do while loop for polling as this will help minimize overall delay Bug 200350539 Change-Id: Icc05911082877df7f9e807da8f16e4d54e620cd8 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1573303 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use a callback to free struct gk20aTerje Bergstrom2017-11-06
| | | | | | | | | | | | | | | | | struct gk20a is now part of nvgpu_os_linux in Linux builds. gk20a.c still frees struct gk20a by kfree(struct gk20a *), which is wrong. Create a new function pointer in struct gk20a for freeing the structure and call kfree(struct nvgpu_os_linux *) instead. JIRA NVGPU-259 Change-Id: I412ee993002cb2a42f0db015fc676de43418ec2f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1591012 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: fix patch buf count update for vidmem"Timo Alho2017-11-03
| | | | | | | | | | | | | | This reverts commit de399ccb0019513a5f9e8f2bcadb02486f99bc80. Bug 2012077 Change-Id: Ie608c3b41aa91f9aaed3fad240ed882a0c6f1ea2 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1591423 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix patch buf count update for vidmemPeter Daifuku2017-11-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | gr_gk20a_ctx_patch_write_begin() updates the patch buffer data_count when the associated graphics context memory buffer has been CPU-mapped; it was doing so by looking for a non-null cpu_va. However, if the graphics context has been allocated from vidmem, cpu_va is always 0, so we can't tell if nvgpu_mem_begin() was called for the context buffer or not. Instead: - add a cpu_accessible flag to the nvgpu_mem struct and set it in nvgpu_mem_begin() - return the value of that flag in nvgpu_mem_cpu_accessible() - gr_gk20a_ctx_patch_write_begin() now calls this new function instead of checking cpu_va. Bug 2012077 JIRA ESRM-74 Change-Id: I8401699f30b4ae7154111721c25c7ec3ff95d329 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1587293 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use nvgpu_is_enabled() for ASPMTerje Bergstrom2017-11-02
| | | | | | | | | | | | | | | | Convert disable_aspm and references to that field to use nvgpu_is_enabled(NVGPU_SUPPORT_ASPM). Initialize it from gk20a_platform struct at probe time. This removes another dependency to struct gk20a_platform. JIRA NVGPU-259 Change-Id: I32e30160f817ea275aa190dcf86c5fd594138d75 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1590124 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move platform_gk20a.h to linuxDeepak Nibade2017-11-02
| | | | | | | | | | | | | | | | | | | | | Move gk20a/platform_gk20a.h to linux specific directory as common/linux/platform_gk20a.h since this file includes all linux specific stuff Fix #includes in all the files to include this file with correct path Remove #include of this file where it is no more needed Fix gk20a_init_sim_support() to receive struct gk20a as parameter instead of receiving linux specific struct platform_device NVGPU-316 Change-Id: I5ec08e776b753af4d39d11c11f6f068be2ac236f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1589938 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Initialize Linux sched in Linux codeTerje Bergstrom2017-11-02
| | | | | | | | | | | | | Initialize Linux scheduling extensions from Linux code. This removes a dependency between common and Linux code. JIRA NVGPU-259 Change-Id: Ibd882f82479eaac05ecc8cf743dd4a89bd7386f2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588663 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: WAR: unbind_channel_verify_status ret val"Deepak Nibade2017-11-02
| | | | | | | | | | | | | | | | | | | This reverts commit a8643b3a99af5011f4e933967f8a09f227ce4949. Proper resolution is implemented in user space (nvrm_gpu) to idle all channels of TSG before unbinding a channel from it And with that we should not see NEXT bit set on channel while unbinding Hence revert the WAR and again return error if we find NEXT bit set on channel Also restore the error print Bug 200327095 Change-Id: Id58e00c4602a4a5c9f65e5ee1329b606f45993d7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1585991 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix mutex leak on fecs_mutexDeepak Nibade2017-11-02
| | | | | | | | | | | | | | | | | | In gk20a_gr_reset(), we acquire g->gr.fecs_mutex and call a bunch of APIs But in case any of these APIs fail, we don't release the mutex and just return the error leaking the mutex So the next attempt to acquire g->gr.fecs_mutex results in a deadlock Fix this by releasing the mutex before returning error Bug 2015370 Change-Id: I9a0214ff53515f819c6566c7d44d1898027416e1 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1589062 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use struct gk20a for create_gr_sysfsDeepak Nibade2017-11-02
| | | | | | | | | | | | | | | | | | API gr_gp10b_create_sysfs() and GR HAL create_gr_sysfs() right now receive linux specific struct device But since this function is called from/declared in common code, we need to remove linux dependency from it Hence update the API and GR HAL to receive struct gk20a pointer instead of device pointer Jira NVGPU-259 Change-Id: I7effa16407d47a2ab5f9562ec4a4dec975a32d6c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588464 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add t19x specific TSG fields.Deepak Goyal2017-11-02
| | | | | | | | | | | | | | | TSG struct is extended to accomodate t19x specific args. JIRA GPUT19x-16 Change-Id: I52b6613d84878f68861fe2515bafba92f83d9572 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586855 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move submit path to linuxDeepak Nibade2017-11-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nvgpu submit path has a lot of dependency on Linux framework e.g. use of copy_from_user, use of structures defined in uapi/nvgpu headers, dma_buf_* calls for trace support etc Hence to keep common code independent of Linux code, move submit path to Linux directory Move below APIs to common/linux/channel.c trace_write_pushbuffer() trace_write_pushbuffer_range() gk20a_submit_prepare_syncs() gk20a_submit_append_priv_cmdbuf() gk20a_submit_append_gpfifo() gk20a_submit_channel_gpfifo() Move below APIs to common/linux/ce2.c gk20a_ce_execute_ops() Define gk20a_ce_execute_ops() in common/linux/ce2.c, and declare it in gk20a/ce2_gk20a.h since it is needed in common/mm code too Each OS needs to implement this API separately gk20a_channel_alloc_gpfifo() use sizeof(nvgpu_gpfifo) to get size of one gpfifo entry, but structure nvgpu_gpfifo is linux specific Define new nvgpu_get_gpfifo_entry_size() in linux specific code and use it in gk20a_channel_alloc_gpfifo() to get gpfifo entry size Each OS needs to implement this API separately Export some APIs from gk20a/ce2_gk20a.h and gk20a/channel_gk20a.h that are needed in linux code Jira NVGPU-259 Jira NVGPU-313 Change-Id: I360c6cb8ce4494b1e50c66af334a2a379f0d2dc4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586277 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Split ctxsw_trace API into non-Linux componentAlex Waterman2017-11-01
| | | | | | | | | | | | | | | | | | | Split the ctxsw trace "core" API code into <nvgpu/ctxsw_trace.h>. This is not perect though since there's some Linuxisms present in the HAL and as such that code has to be hidden by the ctxsw tracing CONFIG. But this patch should work for QNX such that it will allow the code to build as long as CONFIG_GK20A_CTXSW_TRACE is not set. Also fix the copywrite notice in the ctxsw code present under common/linux to be GPL. JIRA NVGPU-287 Change-Id: I94715864caf335b7220185492e4629d713b025e0 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1589429 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove use of platform_gk20a.h from gk20a.cTerje Bergstrom2017-11-01
| | | | | | | | | | | | | gk20a.c does not depend on platform_gk20a.h anymore. As the header is inux specific, remove its use entirely. JIRA NVGPU-259 Change-Id: I6c8934a7a3d4f51e4ca1d7fc580619a3ba248e68 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1590125 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Introduce ecc_gk20a.hash_node only if SYSFS supportedTerje Bergstrom2017-11-01
| | | | | | | | | | | | | | | ecc_gk20a structure has field hash_node for sysfs operations. Make that field conditional to CONFIG_SYSFS to allow building the code in systems without sysfs. JIRA NVGPU-259 Change-Id: Ic153272daa2ae6d9099b95280d10c085f1bef796 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1589506 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove pg419 emulation on pg418Terje Bergstrom2017-11-01
| | | | | | | | | | | | | Remove emulation of pg419 board with a pg418 which does not have a power sensor, but claims to have one in VBIOS. JIRA NVGPU-259 Change-Id: I6527d08dd05b79f96e505561685504bb239ab4ac Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588732 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: save act_eng_bitmask in runlist_infoSeema Khowala2017-11-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue Currently bitmask of engine indices is being saved. This will give wrong active engine ids for a given runlist and s/w will end up checking/polling wrong engine_status registers as these registers are indexed by active engine ids. Also reset_eng_bitmask will end up having wrong value for active engine ids to be reset. Details for runlists serving engines ids for gv11b are:- runlist id 0: gr = 0, grcopy 0 = 2, grcopy1 = 3 runlist id 1: async ce = 1 Incorrect values init_runlist:705 [DBG] runlist 0 : eng bitmask 7 (eng 0, 1, 2) init_runlist:705 [DBG] runlist 1 : eng bitmask 8 (eng 3) Fix Save bitmask of active engine ids in runlist info. Right value init_runlist:705 [DBG] runlist 0 : eng bitmask d (eng 0, 2, 3) init_runlist:705 [DBG] runlist 1 : eng bitmask 2 (eng 1) Bug 200277163 Bug 1945121 Change-Id: Ia299aa0881c4a258080bb0daa3a542fef0d94e4f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1584066 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: halt gr pipe & gr_reset do not work on fmodelSeema Khowala2017-11-01
| | | | | | | | | | | | | | | | Do not halt gr pipe as it will hang simulator. Also during ch/tsg teardown, gr_reset without halting gr pipe crashes simulator. Bug 1958308 Change-Id: I4036b4a4999932f05a0f292d4fc51de21d3a030a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1566575 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move gk20a_scale to be Linux onlyTerje Bergstrom2017-11-01
| | | | | | | | | | | | | | | Move gk20a_scale.[ch] to be common/linux/scale.[ch]. The code is Linux specific, and only referred from Linux specific source files. Change the license back to GPL. JIRA NVGPU-259 Change-Id: I89fa905a1fea4f93c826ddfe2ffce34aefc1b0a2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588650 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use get_maxfreq HALTerje Bergstrom2017-11-01
| | | | | | | | | | | | | Use the get_maxfreq HAL for filling max frequency for GPU characteristics. JIRA NVGPU-259 Change-Id: I754495ae83a5e513cc09497649f6bf4eee7057ad Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588661 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add GPU arch and impl to common structureTerje Bergstrom2017-11-01
| | | | | | | | | | | | | | | | Add GPU architecture and implentation to a new struct nvgpu_gpu_params which is defined in common header file gk20a/gk20.h. JIRA NVGPU-259 Change-Id: I9113d188037c9ad7bfc2200e0e41b39cac576985 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588032 GVS: Gerrit_Virtual_Submit Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix pte location functionsDavid Nieto2017-11-01
| | | | | | | | | | | | | | | | | | Modify the recursive loop in pte_find to make sure it is targeting the proper pde page size. JIRA NVGPUGV100-36 Change-Id: Ib3673d8d9f1bd3c907d532f9e2562ecdc5dda4af Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586739 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: clean linux headers from clk_gk20a.hDeepak Nibade2017-11-01
| | | | | | | | | | | | | | | | | | | | | gk20a/clk_gk20a.h is a common file but still includes linux specific headers Clean them up as below - put linux/clk-provider.h include under config CONFIG_COMMON_CLK - move linux/clkdev.h include to common/linux/platform_gk20a_tegra.c as it is no longer needed in this file Jira NVGPU-259 Change-Id: I4f5b996d3dea91ec3d737d4caa45e0eff6a7ee74 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588220 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Define GPUIDs without referring to UAPITerje Bergstrom2017-10-29
| | | | | | | | | | | | | Define GPUIDs without referring to constants defined in <linux/uapi/nvgpu.h>. JIRA NVGPU-259 Change-Id: I87a677cb0d3377b718dc3aa90175db002df59c9d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1587280 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Make alloc_obj_ctx args Linux specificTerje Bergstrom2017-10-29
| | | | | | | | | | | | | | | | | Use nvgpu_alloc_obj_ctx_args structure specific to Linux code only. Pass the fields of the structure as separate arguments to all common functions. gr_ops_gp10b.h referred to the struct, but it's not used anywhere, so delete the file. JIRA NVGPU-259 Change-Id: Idba78d48de1c30f205a42da2fe47a9f8c03735f1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586563 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move ctxsw_trace_gk20a.c to common/linuxAlex Waterman2017-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Migrate ctxsw_trace_gk20a.c to common/linux/ctxsw_trace.c. This has been done becasue the ctxsw tracing code is currently too tightly tied to the Linux OS due to usage of a couple system calls: - poll() - mmap() And general Linux driver framework code. As a result pulling the logic out of the FECS tracing code is simply too large a scope for time time being. Instead the code was just copied as much as possible. The HAL ops for the FECS code was hidden behind the FECS tracing config so that the vm_area_struct is not used when QNX does not define said config. All other non-HAL functions called by the FECS ctxsw tracing code ha now also been hidden by this config. This is not pretty but for the time being it seems like the way to go. JIRA NVGPU-287 Change-Id: Ib880ab237f4abd330dc66998692c86c4507149c2 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586547 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: skip channel status verification if TSG has timed outDeepak Nibade2017-10-29
| | | | | | | | | | | | | | | | | | | In gk20a_fifo_tsg_unbind_channel(), we always verify channel status before unbinding a channel from TSG But in case TSG has alread timed out we never re-enable it so it does not make sense to inspect channel status anyways So skip channel status verification in case TSG has timed out Bug 200327095 Change-Id: Iccf601271290643c235c3f2656201549210a6886 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586015 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-12 18:58:22 -0400