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* gpu: nvgpu: remove clk_arb.h to gk20a.h circular dependencyDebarshi Dutta2018-08-08
| | | | | | | | | | | | | | | | | clk_arb.h and gk20a.h has circular dependencies to each other. This is removed by forward declaring struct gk20a in clk_arb.h and removing the header gk20a.h from clk_arb.h and similarly forward declaring struct nvgpu_clk_arb in gk20a.h and removing the header clk_arb.h from gk20a.h alongwith putting headers in every execution unit which calls clk_arb.h related methods. JIRA NVGPU-597 Change-Id: I7cedca17206c148b21d93e5d7f0d88c2f98b979a Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1790915 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add IOCTL for SM_EXCEPTION_TYPE_MASKVinod G2018-08-08
| | | | | | | | | | | | | | | | | Add new ioctl to set the SM_EXCEPTION_TYPE_MASK is added to dbg session. Currently support SM_EXCEPTION_TYPE_MASK_FATAL type If this type is set then the code will skip RC recovery, instead trigger CILP preemption. bug 200412641 JIRA NVGPU-702 Change-Id: I4b1f18379ee792cd324ccc555939e0f4f5c9e3b4 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729792 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix MISRA Rule 10.1 issues in gr reset codeScott Long2018-08-08
| | | | | | | | | | | | | | | | Fix MISRA rule 10.1 violations involving need_reset var in gk20a_gr_isr(). Changed type to bool and set it to true any time one of the pending condition checks returns non-zero. JIRA NVGPU-650 Change-Id: I2f87b68d455345080f7b4c68cacf515e074c671a Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1793633 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Rearrange some definitions from gk20a headerVinod G2018-08-07
| | | | | | | | | | | | | | | | | | Moved the gk20a_from_as and gk20a_from_pmu definitions from gk20a.h to as.h and pmu.h Correction for MISRA rule 21.1 error in as.h and pmu.h headers JIRA NVGPU-624 Change-Id: I57de604b47afc589a9778fe69e4856ffcabd9dfc Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1785951 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gk20a: Fix MISRA 15.6 violationsSrirangan2018-08-06
| | | | | | | | | | | | | | This fixes errors due to single statement loop bodies without braces, which is part of Rule 15.6 of MISRA. This patch covers in gpu/nvgpu/gk20a/ JIRA NVGPU-989 Change-Id: I2f422e9bc2b03229f4d2c3198613169ce5e7f3ee Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1791019 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix gpc_tpc_mask to use max_gpc_countRichard Zhao2018-08-06
| | | | | | | | | | | | | | | | | | gpc_tpc_mask uses gpc/tpc IDs directly read from fuse, so it needs to use max_gpc_count for any possible cases rather not gpc_count. Bug 2302005 Change-Id: I903ee3e0c10c4b329dd0d76c40d3516dc36ed303 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1790464 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix MISRA Rule 10.1 issues in SIM codeScott Long2018-08-02
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix MISRA rule 10.1 violations in gr_gk20a_init_ctx_vars_sim(). Instead of logically ORing alloc_xxx_list_yyy() results into the signed err variable just bail immediately if an allocation request fails. Also made changes to sync gr_gk20a_init_ctx_vars_sim() behavior with gr_gk20a_init_ctx_vars_fw() behavior: * return a valid errno on failure * free any previously allocated resources on failure JIRA NVGPU-650 Change-Id: Ie5ea78438da59896da2a9f562d01e46ffaf56dec Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1787042 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allow global regops before ctx is createdDeepak Nibade2018-08-02
| | | | | | | | | | | | | | | | | | | In nvgpu_ioctl_channel_reg_ops(), we right now first check if context is allocated or not and if context is not allocated we fail the regops operation But it is possible that the regops operation only includes global regops which does not need global context allocated So move this global context check from nvgpu_ioctl_channel_reg_ops() to exec_regops_gk20a() and only if we have context ops included in the regops Bug 200431958 Change-Id: Iaa4953235d95b2106d5f81a456141d3a57603fb9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1789262 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: mask intr before gpu power offNitin Kumbhar2018-07-31
| | | | | | | | | | | | | | | | | | | | | | | | | once gpu is powered off i.e. power_on set to false, nvgpu isr does not handle stall/nonstall irq. Depending upon state of gpu, this can result in either of following errors: 1) irq 458: nobody cared (try booting with the "irqpoll" option) 2) "HSM ERROR 42, GPU" from SCE if it detects that an interrupt is not in time. Fix these by masking all interrupts just before gpu power off as nvgpu won't be handling any irq anymore. While masking interrupts, if there are any pending interrupts, then report those with a log message. Bug 1987855 Bug 200424832 Change-Id: I95b087f5c24d439e5da26c6e4fff74d8a525f291 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770802 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon queue supportMahantesh Kumbar2018-07-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Renamed "struct pmu_queue" to "struct nvgpu_falcon_queue" & moved to falcon.h -Renamed pmu_queue_* functions to flcn_queue_* & moved to new file falcon_queue.c -Created ops for queue functions in struct nvgpu_falcon_queue to support different queue types like DMEM/FB-Q. -Created ops in nvgpu_falcon_engine_dependency_ops to add engine specific queue functionality & assigned correct HAL functions in hal*.c file. -Made changes in dependent functions as needed to replace struct pmu_queue & calling queue functions using nvgpu_falcon_queue data structure. -Replaced input param "struct nvgpu_pmu *pmu" with "struct gk20a *g" for pmu ops pmu_queue_head/pmu_queue_tail & also for functions gk20a_pmu_queue_head()/ gk20a_pmu_queue_tail(). -Made changes in nvgpu_pmu_queue_init() to use nvgpu_falcon_queue for PMU queue. -Modified Makefile to include falcon_queue.o -Modified Makefile.sources to include falcon_queue.c Change-Id: I956328f6631b7154267fd5a29eaa1826190d99d1 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1776070 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix MISRA Rule 11.6 issue with fence pool mgmtScott Long2018-07-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | MISRA Rule 11.6 prohibits the casting of an integer value to a void *. The nvgpu allocator used for the fence pool stores the base address of the associated memory as a u64 and returns it via nvgpu_alloc_base(). In gk20a_free_fence_pool() this u64 value was cast to a void * before being passed to nvgpu_vfree() (leading to the violation). This change modifies gk20a_free_fence_pool() to cast the base address back to the original struct gk20a_fence * to eliminate the violation. JIRA NVGPU-895: MISRA Rule 11.6 violations Change-Id: If89cf2c1bc8ea4b0b59da4cf8b1c167738f6badc Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774530 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gk20a: nvgpu: Remove io.h dependency from gk20a.hDebarshi Dutta2018-07-30
| | | | | | | | | | | | | | | | In the current code, gk20a.h includes io.h which gets directly included in a lot of other files. io.h contains methods which uses a struct gk20a as a parameter leading to a circular dependency between io.h and gk20a.h. This can be mitigated by removing io.h from gk20a.h as part of larger effort to moving gk20a.h to nvgpu/gk20a.h JIRA NVGPU-597 Change-Id: I93e504fa9371b88152737b342a75580c65e8f712 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1787316 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set preempt timeoutSeema Khowala2018-07-30
| | | | | | | | | | | | | | | | | | | | | | | | | | -For Si platforms, gk20a_get_gr_idle_timeout returns 3000 ms i.e. 3 sec. Currently this time is used for preempt polling and this conflicts with channel timeout if polling times out. Use fifo_eng_timeout_us converted to ms for preempt polling. -In case of preempt timeout, do not issue recovery for si platform. ctxsw timeout will trigger recovery if needed. For non si platforms, issue preempt timeout rc if preempt times out. Bug 2113657 Bug 2064553 Bug 2038366 Bug 2028993 Bug 200426402 Change-Id: I8d9f58be9ac634e94defa92a20fb737bf256d841 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1762076 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: acquire/release runlist_lock during teardown/mmu_faultSeema Khowala2018-07-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | -Recovery can be called for various types of faults. Acquire runlist_lock for all runlists so that current teardown is done before proceeding to next one. -For legacy chips teardown is done by triggering mmu fault so make sure runlist_locks are acquired during teardown and also during handling mmu fault. -gk20a_fifo_handle_mmu_fault is renamed as gk20a_fifo_handle_mmu_fault_locked -gk20a_fifo_handle_mmu_fault called from gk20a_fifo_teardown_ch_tsg is replaced with gk20a_fifo_handle_mmu_fault_locked -gk20a_fifo_handle_mmu_fault acquires/release runlist_lock for all runlists and calls gk20a_fifo_handle_mmu_fault_locked Bug 2113657 Bug 2064553 Bug 2038366 Bug 2028993 Change-Id: I973d7ddb6924b50bae2d095152867e99c87e780a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761197 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: shutdown nvlink in driver removeNitin Kumbhar2018-07-26
| | | | | | | | | | | | | During driver remove, if nvlink is set up, gracefully shut it down so that it can be enumerated again. Bug 1987855 Change-Id: Ibd83a5e29364b22264e689aa879569a9cccf0f79 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1746073 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Rearrange the static inline codeVinod G2018-07-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to avoid the circular dependencies, rearrange the static inline functions from gk20a.h file. Moved gk20a_gr_flush_channel_tlb function to gr_gk20a.c and removed the #include gr_gk20a.h from gk20a.h Added a helper function utils.h to move all generic static inline functions which have no reference to gpu related structures. ptimer related functions are moved to ptimer.h Implementations for as and pmu are moved to corresponding files. JIRA NVGPU-624 Change-Id: I4e956326e773ba037bf3a1696cc4c462085dbbe5 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1781941 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: debugfs node to enable/disable ltc_illegal_compstat intrseshendra Gadagottu2018-07-24
| | | | | | | | | | | | | | | | | | | Added debugfs node under ltc directory with name: intr_illegal_compstat_enable Enabling/disabling of ltc_illegal_compstat intr is possible through debugfs node. Since ltc state is lost with rail gate, this setting is cached and will be populated during ltc initialization. Bug 2099406 Change-Id: I4bf62228dfd2bbb94f87f923f9f4f6e5ad0b07f0 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774683 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: tpc powergating through sysfsDeepak Goyal2018-07-24
| | | | | | | | | | | | | | | | | | | | | | | - adds static tpc-powergating through sysfs. - active tpc count will remain till the GPU/systems is not booted again. - tpc_pg_mask can be written only after GPU probe finishes and GPU boot is triggered. Note: To be able to use this feature, we need to change boot/init scripts of the OS(used with nvgpu driver) to write to sysfs nodes before posting discover image size query to FECS. Bug 200406784 Change-Id: Id749c7a617422c625f77d0c1a9aada2eb960c4d0 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1742422 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: disable fb fault buffer in prepare poweroffAparna Das2018-07-20
| | | | | | | | | | | | | | | FB fault buffer is enabled on finalize poweron. Disable the buffer in prepare poweroff. This also eliminates the need to disable the buffer in fault info mem destroy which otherwise accesses GPU registers after these are locked in prepare poweroff. Bug 200427479 Change-Id: I1ca3e6ed4417847731c09b887134f215a2ba331c Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1776387 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rework ecc structure and sysfsRichard Zhao2018-07-19
| | | | | | | | | | | | | | | | | | | | | - create common file common/ecc.c which include common functions for add ecc counters and remove counters. - common code will create a list of all counter which make it easier to iterate all counters. - Add chip specific file for adding ecc counters. - add linux specific file os/linux/ecc_sysfs.c to export counters to sysfs. - remove obsolete code - MISRA violation for using snprintf is not solved, tracking with jira NVGPU-859 Jira NVGPUT-115 Change-Id: I1905c43c5c9b2b131199807533dee8e63ddc12f4 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1763536 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: issue runlist preempt during teardownSeema Khowala2018-07-19
| | | | | | | | | | | | | | | | -During teardown issue runlist preempt -preempt_ch_tsg hal is removed as it is no more required. This hal was added to be called from teardown so that if there is preempt timeout, preempt timeout recovery is not triggered. Bug 200426402 Change-Id: I679e3306aa890ff0cfa211cfcc7d5405b7cb1211 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1775443 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "Revert: GV11B runlist preemption patches"Seema Khowala2018-07-19
| | | | | | | | | | | | | | | | | | | This reverts commit 0b02c8589dcc507865a8fd398431c45fbda2ba9c. Originally change was reverted as it was making ap_compute test on embedded-qnx-hv e3550-t194 fail. With fixes related to replacing tsg preempt with runlist preempt during teardown, preempt timeout set to 100 ms (earlier this was set to 1000ms for t194 and 3000ms for legacy chips) and not issuing preempt timeout recovery if preempt fails, helped resolve the issue. Bug 200426402 Change-Id: If9a68d028a155075444cc1bdf411057e3388d48e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1762563 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gv11b: Rearrange gr functionVinod G2018-07-19
| | | | | | | | | | | | | | | | | | | | | | | | | | Moved gv11b_detect_ecc_enabled_units function from gv11b.c to gr_gv11b.c, as this is being used only in gr_gv11b file. In order to avoid GR code touching fuse registers, as it need to include fuse HW headers in GR code, introduced two fuse HALs which are being called from GR code. is_opt_ecc_enable for checking whether ecc enable bit is set in fuse register and is_opt_feature_overide_disable for checking whether feature override disable bit is set in fuse register. Initialized fuse HAL functions for chips that make use of those HAL functions. JIRA NVGPU-615 Change-Id: Iafe5a3940bb19cb3da51e270403450b63c2f67a3 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1775564 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: avoid redundant enable/disable PGDaniel Fu2018-07-18
| | | | | | | | | | | | | | | | | | ELPG powergate is refcounted. We should not enable/disable it, if it's already so. Or it will break the PG disable/enable function. Bug 200410661 Change-Id: Ife60f373b877d1ffc441578ffa53fe0d4409eba6 Signed-off-by: Daniel Fu <danifu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774265 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove NEXT_2 GPU supportDeepak Nibade2018-07-16
| | | | | | | | | | | | | | | | | | | NVGPU_GPUID_NEXT_2 is no more supported, hence remove it's support from common code Jira NVGPUT-109 Change-Id: I1bb0e5e0c19765f9a05b5a6492706090af300fd6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1764262 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move FB to commonTerje Bergstrom2018-07-12
| | | | | | | | | | | | Move all FB HAL implementations to common/fb. JIRA NVGPU-596 Change-Id: Id4ea09d608f5d6d1b245bddac09ecf1444b8ab30 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769724 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use HAL for calls from MM to FBTerje Bergstrom2018-07-12
| | | | | | | | | | | | | | | | | | | mm_gv11b.c has several direct calls to fb_gv11b.h. Redirect them to go via a HAL. Also make sure the HALs are using parameter with correct signedness and prefix the parameter constants with NVGPU_FB_MMU_. MMU buffer table indices were also defined in fb_gv11b.h, even though the tables themselves are defined in include/nvgpu/mm.h. Move the indices to include/nvgpu/mm.h and prefix them with NVGPU_MM_MMU_. JIRA NVGPU-714 Change-Id: Ieeae7c5664b8f53f8313cfad0a771d14637caa08 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1776131 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Simplify FB hub intr enableTerje Bergstrom2018-07-11
| | | | | | | | | | | | Hard code flags for enabling and disabling FB hub interrupts. JIRA NVGPU-714 Change-Id: I806ef443cb9e27e221d407d633ca91d8fb40d075 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769853 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Initialize hwpm perfmons (engine_sel)Vaibhav Kachore2018-07-10
| | | | | | | | | | | | | | - For Mode-E ctxsw it is required that engine_sel is set to 0xFFFFFFFF. - Default 0 is a valid signal and causes problems. Bug 2106999 Change-Id: I5cdb4441a8e6d7e8133c31a9e361b54611dd2995 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770755 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable HWPM Mode-E context switchVaibhav Kachore2018-07-10
| | | | | | | | | | | | | | | | | | - Write new pm mode to context buffer header. Ucode use this mode to enable mode-e context switch. This is Mode-B context switch of PMs with Mode-E streamout on one context. If this mode is set, Ucode makes sure that Mode-E pipe (perfmons, routers, pma) is idle before it context switches PMs. - This allows us to collect counters in a secure way (i.e. on context basis) with stream out. Bug 2106999 Change-Id: I5a7435f09d1bf053ca428e538b0a57f3a175ac37 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1760366 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon code cleanupMahantesh Kumbar2018-07-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | -Created common falcon function nvgpu_flcn_bl_bootstrap() to bootstrap falcon bootloader -Created HAL gk20a_falcon_bl_bootstrap() which does actual bootloader bootstrap by fetching parameters and loading code/parameters as needed. -Created HAL ops bl_bootstrap under nvgpu_falcon_ops. -Created struct nvgpu_falcon_bl_info to hold info required for bootloader to pass to common function -Removed falcons bootstrap code in multiple file & made changes to fill struct nvgpu_falcon_bl_info & call nvgpu_flcn_bl_bootstrap(). Change-Id: Iee275233915ff11f9afb5207ac0c3338ca9dacc1 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1756104 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move FB MMU query to FB HALTerje Bergstrom2018-07-09
| | | | | | | | | | | | | | Move queries of FB MMU configuration to FB HAL. Also use g->ltc_count instead of reading the number of LTCs from FB. These changes together remove last direct uses of FB registers from GR. JIRA NVGPU-714 Change-Id: I1b4b46fc2f636f5c1904e4174040a47a27948999 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1773076 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Conditional enable for replayable faultTerje Bergstrom2018-07-09
| | | | | | | | | | | | | | | | Enable replayable fault only for contexts where they are requested. This required moving the code to initialize subcontexts to happen later. Fix signedness issues in definition of flags. JIRA NVGPU-714 Change-Id: I472004e13b1ea46c1bd202f9b12d2ce221b756f9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1773262 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Call handle_replayable_fault via HALTerje Bergstrom2018-07-08
| | | | | | | | | | | | | | gr_gv11b.c had a direct dependency to fb_gv11b.c because it calls FB to process replayable faults while waiting for SM lockdown. Redirect that call via HAL to remove the dependency. JIRA NVGPU-714 Change-Id: Ie6df3658f06b1f867893bc98fe581c95813f0431 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1772884 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add error check for init_runlistNitin Kumbhar2018-07-06
| | | | | | | | | | | | | | | | | | Allocations in init_runlist can fail. Check for such a failure during fifo setup is being done. Bug 1987855 Change-Id: I1771a15ebeac81ab2e3ebc9a75363445a0b6f20d Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770801 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Clean up include/nvgpu/vidmem.hTerje Bergstrom2018-07-06
| | | | | | | | | | | | | | | | | vidmem.h had a forward declaration for a Linux specific struct work_struct. Removed that. vidmem.h also #included nvgpu_mem.h even though there was no use for it. As a follow-up css_gr_gk20a.h did refer to nvgpu_mem but did not #include it, so added that. Change-Id: Ifea88adae86ed95302465641821fbb107d7cc233 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1768260 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to invalidate replay mmu faultDeepak Nibade2018-07-05
| | | | | | | | | | | | | | | | Add new HAL gops.fb.mmu_invalidate_replay() to invalidate replay mmu fault Use existing API gv11b_fb_mmu_invalidate_replay() to set to this HAL on all Volta chips Bug 2228914 Jira NVGPU-838 Jira NVGPUT-73 Change-Id: I394901857d41499f3ea44023393fe271fb664260 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1767970 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix ppc broadcast address splitDeepak Nibade2018-07-05
| | | | | | | | | | | | | | | | | | | | | | In gr_gk20a_split_ppc_broadcast_addr() we convert a PPC broadcast address to its corresponding unicast address list But we consider gr.pe_count_per_gpc instead of actual number of PPCs and that leads to generating incorrect list of addresses Fix this by using gr.gpc_ppc_count[gpc_num] which gives correct number of PPC count Jira NVGPUT-117 Change-Id: If7e7c19244b90cb3c405dcba4ae7a86c782972f7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1767838 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to get offset in gpccs segmentDeepak Nibade2018-07-05
| | | | | | | | | | | | | | | | | | | | | | In gr_gk20a_find_priv_offset_in_buffer() we right now calculate offset of a register in gpccs segment based on register address type Separate out sequence to find offset in gpccs segment and move it to new API gr_gk20a_get_offset_in_gpccs_segment() Introduce new HAL gops.gr.get_offset_in_gpccs_segment() and set above API to this HAL Call HAL from gr_gk20a_find_priv_offset_in_buffer() instead of calling direct API Jira NVGPUT-118 Change-Id: I0df798456cf63e3c3a43131f3c4ca7990b89ede0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761669 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move can_railgate to enabled.hKonsta Holtta2018-07-04
| | | | | | | | | | | | | The g->can_railgate flag is a global constant-ish property like the rest of the flags behind nvgpu_is_enabled() API, so move it there. Bug 200327089 Change-Id: Id1f2f16ea1975a03fb56f10c2f3c8c705574e341 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1764266 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove gk20a_channel_sync::incr_wfiKonsta Holtta2018-06-29
| | | | | | | | | | | | | | This explicit incr_wfi has not been used since commit 06be77da376f ("gpu: nvgpu: Do not send WFI when finishing channel"). Change-Id: I0213b0f728f83b483a7dbbef252912555b06815f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1765407 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove legacy comment noteKonsta Holtta2018-06-29
| | | | | | | | | | | | | | | | gk20a_channel_clean_up_jobs hasn't needed a barrier since commit d20a501dcbf2 ("gpu: nvgpu: simplify job semaphore release in abort"). Bug 200327089 Change-Id: I64b9e3b7970de232ac553f570b8fd41aec3b7e21 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1764309 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove unnecessary nvgpu_memset callsKonsta Holtta2018-06-28
| | | | | | | | | | | | | | | | Some graphics context buffers are explicitly cleared to zero after allocation. That's not necessary because the allocator gives zero-initialized memory already, so remove the clears. Change-Id: I8f9913605801e35082762e7743762d97f88e1d12 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761578 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: don't mem_{begin,end}() for grKonsta Holtta2018-06-28
| | | | | | | | | | | | | | | | | | | | | Now that GR buffers always have a kernel mapping, remove the unnecessary calls to nvgpu_mem_begin() and nvgpu_mem_end() on these buffers: - global ctx buffer mem in gr - gr ctx mem in a tsg - patch ctx mem in a gr ctx - pm ctx mem in a gr ctx - ctx_header mem in a channel (subctx header) Change-Id: Id2a8ad108aef8db8b16dce5bae8003bbcd3b23e4 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1760599 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move submit code to commonKonsta Holtta2018-06-27
| | | | | | | | | | | | | | | | To finish OS unification of the submit path, move the gk20a_submit_channel_gpfifo* functions to a file that's accessible also outside Linux code. Also change the prefix of the submit functions from gk20a_ to nvgpu_. Jira NVGPU-705 Change-Id: I8ca355d1eb69771fb016c7a21fc7f102ca7967d7 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1760421 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert: GV11B runlist preemption patchesAlex Waterman2018-06-26
| | | | | | | | | | | | | | | | | | | | This reverts commit 2d397e34a5aafb5feed406a13f3db536eadae5bb. This reverts commit cd6e821cf66837a2c3479e928414007064b9c496. This reverts commit 5cf1eb145fef763f7153e449be60f1a7602e2c81. This reverts commit a8d6f31bde3ccef22ee77023eaff4a62f6f88199. This reverts commit 067ddbc4e4df3f1f756f03e7865c369a46f420aa. This reverts commit 3eede64de058fcb1e39d723dd146bcd5d06c6f43. This reverts commit 1407133b7e1b27a92ee8c116009541904d2ff691. This reverts commit 797dde3e32647df3b616cea67f4defae59d38b3f. Looks like this makes the ap_compute test on embedded-qnx-hv e3550-t194 quite bad. Might also affect ap_resmgr. Signed-off-by: Alex Waterman <alexw@nvidia.com> Change-Id: Ib9f06514d554d1a67993f0f2bd3d180147385e0a Reviewed-on: https://git-master.nvidia.com/r/1761864 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: add runlist abort & remove bare channelSeema Khowala2018-06-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Add support for aborting runlist/s. Aborting runlist/s, will abort all active tsgs and associated active channels within these active tsgs -Bare channels are no longer supported. Remove recovery support for bare channels. In case there are bare channels, recovery will trigger runlist abort Bug 2125776 Bug 2108544 Bug 2105322 Bug 2092051 Bug 2048824 Bug 2043838 Bug 2039587 Bug 2028993 Bug 2029245 Bug 2065990 Bug 1945121 Bug 200401707 Bug 200393631 Bug 200327596 Change-Id: I6bec8a0004508cf65ea128bf641a26bf4c2f236d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640567 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove timeout_rc_type i/p paramSeema Khowala2018-06-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -is_preempt_pending hal does not need timeout_rc_type input param as for volta, reset_eng_bitmask is saved if preempt times out. For legacy chips, recovery triggers mmu fault and mmu fault handler takes care of resetting engines. -For volta, no special input param needed to differentiate between preempt polling during normal scenario and preempt polling during recovery. Recovery path uses preempt_ch_tsg hal to issue preempt. This hal does not issue recovery if preempt times out. Bug 2125776 Bug 2108544 Bug 2105322 Bug 2092051 Bug 2048824 Bug 2043838 Bug 2039587 Bug 2028993 Bug 2029245 Bug 2065990 Bug 1945121 Bug 200401707 Bug 200393631 Bug 200327596 Change-Id: Ie76a18ae0be880cfbeee615859a08179fb974fa8 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709799 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: do not poll preempt done if eng intr pendingSeema Khowala2018-06-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | -During polling eng preempt done, reset eng only if eng stall intr is pending. Also stop polling for eng preempt done if eng intr is pending. -Add max retries for pre-si platforms for poll pbdma and eng preempt done polling loops. Bug 2125776 Bug 2108544 Bug 2105322 Bug 2092051 Bug 2048824 Bug 2043838 Bug 2039587 Bug 2028993 Bug 2029245 Bug 2065990 Bug 1945121 Bug 200401707 Bug 200393631 Bug 200327596 Change-Id: I66b07be9647f141bd03801f83e3cda797e88272f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694137 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: zero prealloc indices on initKonsta Holtta2018-06-21
| | | | | | | | | | | | | | | | | | Initialize the prealloc job list put and get indices to zero when allocating these resources. Otherwise we'd get whatever got left from the channel's previous lifetime. Change-Id: Idb17ec7bfbd0c1e2121c7a63e41dc5845560e988 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1756871 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sami Kiminki <skiminki@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-23 08:12:40 -0400