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path: root/drivers/gpu/nvgpu/gk20a
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* gpu: nvgpu: gpu railgate handling with runtime pmseshendra Gadagottu2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Earlier implementation of railgate disable config is disabling runtime pm during pm_init. This is causing multiple issues: 1. gpu rail will be on as soon as nvgpu driver probe is called. Actual gpu hw init may happen at much later point of time. 2. This is breaking railgate_enable sysfs node functionality. railgate_enable is not working if runtime pm is disabled. To avoid all these issues for railgate disable, enable runtime pm during pm_init and set auto-suspend delay to negative (-1), which will disable runtime pm suspend calls. Also fixed following issues along with this: 1. Updated railgate_enable debugfs implementation to use auto-suspend delay. To disable railgating: Set auto-suspend delay with negative value(-1) which will disable runtime pm suspend. To enable railgating: Set auto-suspend delay with railgate_delay value. Also removed redundant user_railgate_disabled gk20a device data and replaced with can_railgate, where ever it is applicable. 2. Initialized default railgate_delay to 500msec to avoid railgate on/off transitions with railigate enable from disabled state. 3. Created railgate_residency debug fs node irrespective of can_railgate initial state. This is helping with the case, where initial state of railgate state off and then railgate enable is done through sysfs node. Bug 2073029 Change-Id: I531da6d93ba8907e806f65a1de2a447c1ec2665c Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694944 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set gv10x boot clockVaikundanathan S2018-06-14
| | | | | | | | | | | | | | | - Set gv10x boot gpcclk to 952 MHz - Created ops to set gv10x boot gpcclk instead of using clk arbiter to set clocks Bug 200399373 Change-Id: Ice5956f79d4a52abf455506a798cf7b914f3d3ed Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700788 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Add gops to load pstate functionsVaikundanathan S2018-06-14
| | | | | | | | | | | | | | | Add gops to choose to/not to enable 1. clk_freq_controller 2. pmgr_domain 3. lpwr_pg Bug 200399373 Change-Id: Ie5131f9ea260f777fded8392f24815acef6cfbea Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702216 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Update vfe_load for GV100Vaikundanathan S2018-06-14
| | | | | | | | | | | | Add gops to choose vfe_load between GP and GV. Bug 200399373 Change-Id: I73e0fbd2f1956e81c241f09639c69f33082e617b Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702143 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Add option for split rail supportVaikundanathan S2018-06-14
| | | | | | | | | | | | Add gops to check whether split rail is suported in the chip Bug 200399373 Change-Id: I5e955127e06d1fbc9b3eca0a895afa0a06f39d91 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702130 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: Add HAL for pll setupTejal Kudav2018-06-14
| | | | | | | | | | | | | | | | | | Before nvlink 2.2, driver was responsible for setting the NVLink clocks during NVLink initialization. For the purpose of security, NVLink PLL handling is moved to Minion in nvlink 2.2 and driver should stop writing to these registers. JIRA NVLINK-167 Change-Id: I18392a29c322da55053037bfde62c8f74ee75288 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730597 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: Add HAL for RXDETTejal Kudav2018-06-14
| | | | | | | | | | | | | | | | | | | RXDET is supported only on nvlink 2.2 devices and forward. Add HAL to run RXDET selectively based on chip. RXDET needs to be done after the links are out of reset but before any other link level initialization. minion_send_cmd is also made non-static to support RXDET functionality. JIRA NVLINK-160 Change-Id: Ic65b8dbc7281743f62072089ff3c805521ac9b38 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729525 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: initialze bundle64 stateDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | We receive bundle with address and 64 bit values from ucode on some platforms This patch adds the support to handle 64 bit values Add struct av64_gk20a to store an address and corresponding 64 bit value Add struct av64_list_gk20a to store count and list of av64_gk20a Add API alloc_av64_list_gk20a() to allocate the list that supports 64bit values In gr_gk20a_init_ctx_vars_fw(), if we see NETLIST_REGIONID_SW_BUNDLE64_INIT, load the bundle64 state into above local structures Add new HAL gops.gr.init_sw_bundle64() and call it from gk20a_init_sw_bundle() if defined Also load the bundle for simulation cases in gr_gk20a_init_ctx_vars_sim() Jira NVGPUT-96 Change-Id: I1ab7fb37ff91c5fbd968c93d714725b01fd4f59b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1736450 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix crash due to accessing incorrect TSG pointerDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_gr_isr(), we handle various errors including GPC/TPC errors. And then if BPT errors are pending we call gk20a_gr_post_bpt_events() at the end and pass channel pointer to it gk20a_gr_post_bpt_events() extracts TSG pointer based on ch->tsgid But in some race conditions it is possible that we clear the error and trigger recovery and as a result channel is unbounded from TSG and closed by user space before calling gk20a_gr_post_bpt_events() And in that case the code above results in getting incorrect TSG pointer and hence crashes as below Unable to handle kernel paging request at virtual address ffffff8012000c08 ... [<ffffff8008081f84>] el1_da+0x24/0xb4 [<ffffff80086e72e0>] gk20a_tsg_get_event_data_from_id+0x30/0xb0 [<ffffff80086e7560>] gk20a_tsg_event_id_post_event+0x50/0xc8 [<ffffff800872922c>] gk20a_gr_isr+0x27c/0x12e0 To fix this extract the TSG pointer before handling all the errors and pass this pointer to gk20a_gr_post_bpt_events() will post the events if they are enabled and if TSG is still open Bug 200404720 Change-Id: I4861c72e338a2cec96f31cb9488af665c5f2be39 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735415 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: initialize HAL for NEXT_2 gpuDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | In gpu_init_hal(), call NVGPU_NEXT_2_INIT_HAL() if we detect chip NVGPU_GPUID_NEXT_2 Jira NVGPUT-95 Change-Id: Ie1121591e53a1587766ea03bb62d0aae01d9ccbf Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1734099 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add g->fifo_eng_timeout_usThomas Fleury2018-06-14
| | | | | | | | | | | | | | Add g->fifo_eng_timeout_us to define engine timeout in microseconds. It is initialized with GRFIFO_TIMEOUT_CHECK_PERIOD_US. In RM server case, it can be overriden with value defined in device tree. Jira EVLR-2674 Change-Id: I69ac2ce779fe575566c8ba48e8cd2d0e6b2d93cf Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1728391 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support CAU ctxsw listDeepak Nibade2018-05-30
| | | | | | | | | | | | | | | | | | | | | | | CAU (Counter Aggregation Unit) registers might be split out from SMPC registers and moved into their own list on some platforms In gr_gk20a_init_ctx_vars_fw() add support to check if pm_cau list is available If list is available, count will be set to non-zero here In add_ctxsw_buffer_map_entries_gpcs(), parse the pm_cau list if count is non-zero Bug 2139870 Change-Id: Ia630e7d03481a6f927c6739d28ebfe49f221326f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1733208 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Braun (SW-GPU) <matthewb@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: abstract submit profilingKonsta Holtta2018-05-25
| | | | | | | | | | | | | | | | Add gk20a_fifo_profile_snapshot() to store the submit time in a profiling entry that was acquired from gk20a_fifo_profile_acquire(). Also get rid of ifdef CONFIG_DEBUG_FS by stubbing the acquire and free functions when debugfs is not enabled. This reduces some cyclomatic complexity in the submit path. Jira NVGPU-708 Change-Id: I39829a6475cfe3aa582620219e420bde62228e52 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729545 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove unused function declarationsAlex Waterman2018-05-25
| | | | | | | | | | | | Change-Id: I36f2d13ed3797719137c670afef9b644d48ea16e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1727485 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move bus HAL to commonTerje Bergstrom2018-05-25
| | | | | | | | | | | Move implementation of bus HAL to common/bus. Change-Id: Ia89350f9d94f3ccfd5500a340e6a677cd7d4cfaa Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1726337 GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove __uXX typedefsAlex Waterman2018-05-24
| | | | | | | | | | | | | | | | | Integrity already typedefs these and complains if you override them even with the same underlying type. Since we only use these in the regops_gk20a.h header file (outside of the Linux specific code, that is) this patch just changes the __uXX to uXX. With that we can delete the now unnecessary __uXX defs. JIRA NVGPU-525 Change-Id: I01dd2723b68db2170449342f73c711ee5a589adb Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1721186 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs to enable/disable hub interruptsDeepak Nibade2018-05-24
| | | | | | | | | | | | | | | | | | Add below two new HALs gops.fb.enable_hub_intr() to enable hub interrupts gops.fb.disable_hub_intr() to disable hub interrupts Set existing APIs gv11b_fb_enable/disable_hub_intr() to these HALs Call the HALs everywhere instead of calling the APIs directly Jira NVGPUT-44 Change-Id: Id299c6d228733ed365a71be6b180186776cc1306 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1725977 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove broken force_pramin featureKonsta Holtta2018-05-24
| | | | | | | | | | | | | | The forced PRAMIN reads and writes for sysmem buffers haven't worked in a while since the PRAMIN access code was refactored to work with vidmem-only sgt allocs. This feature was only ever meant for testing and debugging PRAMIN access and early dGPU support, but that is stable enough now so just delete the broken feature instead of fixing it. Change-Id: Ib31dae4550f3b6fea3c426a2e4ad126864bf85d2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1723725 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: populate gpu rev based on soc checkseshendra Gadagottu2018-05-24
| | | | | | | | | | | | | | | | | | Populate gpu rev as 0xa2 for gv11b with t194 A02 soc. Bug 2053668 Change-Id: I22a2bc7026162e34e9a605dfda3d83fa989b5248 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1713096 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Wei Sun <wsun@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Code updates for MISRA violationsVinod G2018-05-21
| | | | | | | | | | | | | | | | As part of the MISRA fixes, moving all the gating_reglist files to common/clock_gating dir, the new directory structure suggested to follow. Removed unused gating_reglist files for gk20a JIRA NVGPU-646 Change-Id: I388855befcf991ee68eeffed10fe9ac456210649 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1722330 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: release runlist_lock before issuing recoverySeema Khowala2018-05-18
| | | | | | | | | | | | | Release runlist_lock before issuing runlist update timeout recovery. Bug 2115080 Change-Id: I22cd0dd8ab6828412fcc98f587e4a5cdce907651 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1722308 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add timeouts_disabled_refcount for enabling timeoutSeema Khowala2018-05-18
| | | | | | | | | | | | | | | | -timeouts will be enabled only when timeouts_disabled_refcount will reach 0 -timeouts_enabled debugfs will change from u32 type to file type to avoid race enabling/disabling timeout from debugfs and ioctl -unify setting timeouts_enabled from debugfs and ioctl Bug 1982434 Change-Id: I54bab778f1ae533872146dfb8d80deafd2a685c7 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588690 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Code updates for MISRA violationsVinod G2018-05-18
| | | | | | | | | | | | | | | | | | | | | | | | | Code related to MC module is updated for handling MISRA violations Rule 10.1: Operands shalln't be an inappropriate essential type. Rule 10.3: Value of expression shalln't be assigned to an object with a narrow essential type. Rule 10.4: Both operands in an operator shall have the same essential type. Rule 14.4: Controlling if statement shall have essentially Boolean type. Rule 15.6: Enclose if() sequences with braces. JIRA NVGPU-646 JIRA NVGPU-659 JIRA NVGPU-671 Change-Id: Ia7ada40068eab5c164b8bad99bf8103b37a2fbc9 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1720926 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs for devinit and preos bios operationsDeepak Nibade2018-05-18
| | | | | | | | | | | | | | | | | | | | | | | Add below new HALs for bios operations gops.bios.devinit() gops.bios.preos() gops.bios.verify_devinit() Export existing APIs gp106_bios_devinit() and gp106_bios_preos() and set them to above HALs on gp106 and gv100 And call new HALs from gp106_bios_init() if supported instead of directly calling APIs Jira NVGPUT-48 Change-Id: Ic89f1c86cf6e3e0785b3663fe733b201d6f2f773 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1708382 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLISTDavid Li2018-05-18
| | | | | | | | | | | | | | | | | | | | | | | Add NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST ioctl to reschedule runlist, and optionally check host and FECS status to preempt pending load of context not belonging to the calling channel on GR engine during context switch. This should be called immediately after a submit to decrease worst case submit to start latency for high interleave channel. There is less than 0.002% chance that the ioctl blocks up to couple miliseconds due to race condition of FECS status changing while being read. For GV11B it will always preempt pending load of unwanted context since there is no chance that ioctl blocks due to race condition. Also fix bug with host reschedule for multiple runlists which needs to write both runlist registers. Bug 1987640 Bug 1924808 Change-Id: I0b7e2f91bd18b0b20928e5a3311b9426b1bf1848 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1549050 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: runlist_lock released before preempt timeout recoverySeema Khowala2018-05-17
| | | | | | | | | | | | | | | | | Release runlist_lock and then initiate recovery if preempt timed out. Also do not issue preempt if ch, tsg or runlist id is invalid. tsgid could be invalid for below call trace gk20a_prepare_poweroff->gk20a_channel_suspend-> *_fifo_preempt_channel->*_fifo_preempt_tsg Bug 2065990 Bug 2043838 Change-Id: Ia1e3c134f06743e1258254a4a6f7256831706185 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1662656 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to insert semaphore commandsDeepak Nibade2018-05-16
| | | | | | | | | | | | | | | | | | | | | Add below new HALs gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer Separate out new API gk20a_fifo_add_sema_cmd() to implement semaphore acquire/ release sequence and set it to gops.fifo.add_sema_cmd() Add gk20a_fifo_get_sema_wait_cmd_size() and gk20a_fifo_get_sema_incr_cmd_size() to return respective command buffer sizes Jira NVGPUT-16 Change-Id: Ia81a50921a6a56ebc237f2f90b137268aaa2d749 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704490 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vf inject changesVaikundanathan S2018-05-14
| | | | | | | | | | | | | | | | | | | | - Added vf change inject support for gv10x - Updated clk_pmu_vf_inject() to fill required data for pascal or volta vf change inject support - Added new ctrl clk interface for gv10x clk domain list - Added pmu interface for gv10x clk domain list & vf change inject request - Modified clk cmd, msg & RPC id's to match with chips_a_23609936 branch Bug 200399373 Change-Id: Ib9dc10073386f63bdfd92110c7ec3e09b1c484ce Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700746 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move sync_gk20a under common/linux directoryDebarshi Dutta2018-05-14
| | | | | | | | | | | | | | | | sync_gk20a.* files are no longer used by core code and only invoked from linux specific implementations of the OS_FENCE framework which are under the common/linux directory. Hence, sync_gk20a.* files are also moved under common/linux. JIRA NVGPU-66 Change-Id: If623524611373d2da39b63cfb3c1e40089bf8d22 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1712900 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix Gpu sysfs access to Fmax@VminAlex Frid2018-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | Currently gpu sysfs retrieves Fmax@Vmin by direct call into Tegra DVFS driver that introduces compile time dependencies on CONFIG_TEGRA_DVFS. In addition incorrect clock is used for DVFS information access. Re-factored sysfs node to use generic GPU clock operation for Fmax@Vmin read. This would fix a bug in target clock selection, and allows to remove dependency of sysfs on CONFIG_TEGRA_DVFS. Updated nvgpu_linux_get_fmax_at_vmin_safe operation itself so it can be called on platforms that does not support Tegra DVFS, although 0 will still be returned as Fmax@Vmin on such platforms. Bug 2045903 Change-Id: I32cce25320df026288c82458c913b0cde9ad4f72 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1710924 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: poll watchdog status activelyKonsta Holtta2018-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read GP_GET and GET from hardware every time when the poll timer expires instead of when the watchdog timer expires. Restart the watchdog timer if the get pointers have increased since the previous read. This way stuck channels are detected quicker. Previously it could have taken at most twice the watchdog timeout limit for a stuck channel to get recovered; with this change, a coarse sliding window is used. The polling period is still 100 ms. The difference is illustrated in the following diagram: time 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 get a b b b b b b b b b b b b b b b b b b b b prev - n n n n n n n n n A n n n n n n n n n S next - A s s s s s s s s s S "time" represents wall time in polling units; 0 is submit time. For simplicity, watchdog timeout is ten units. "get" is the GP_GET that advances a little from a and then gets stuck at b. "prev" is the previous behaviour, "next" is after this patch. "A" is when the channel is detected as advanced, and "S" when it's found stuck and recovered; small "s" is when it's found stuck but when the time limit has not yet expired and "n" is when the hw state is not read. Bug 1700277 Bug 1982826 Change-Id: Ie2921920d5396cee652729c6a7162b740d7a1f06 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1710554 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: dump fecs method data and push adrSeema Khowala2018-05-10
| | | | | | | | | | | Dump fecs method data and adr if ucode times out or errors out. This is good to have for debugging. Change-Id: I79c4bc3bc30cfd09f273f4eb6b53863653227ecd Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1707761 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove access to mc_enable_pb_r()Deepak Nibade2018-05-10
| | | | | | | | | | | | | We don't need to configure mc_enable_pb_r() register in any of the supported chips, so remove access to this register Jira NVGPUT-52 Change-Id: I8a7a524367ce7953f926143242c6d63bc8fd5ed1 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1711245 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove sync_fence dependencies from fence_gk20aDebarshi Dutta2018-05-10
| | | | | | | | | | | | | | | | | Replaced all instances of sync_fence in gk20a_fence* code with nvgpu_os_fence. Added the API install_fence for the nvgpu_os_fence abstraction. sync_fence mechanism and its dependencies are completely removed from the fence_gk20a methods. Due to the recent os_fence changes and the changes to fence_gk20a, we can finally get rid of all the CONFIG_SYNCS present in the submit path. JIRA NVGPU-66 Change-Id: I3551dab04b93b1e94db83fc102a41872be89e9ed Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1701245 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: adapt gk20a_channel_syncpt to use os_fenceDebarshi Dutta2018-05-10
| | | | | | | | | | | | | This patch adapts gk20a_channel_syncpt to use os_fence for post fence as well as pre-fence(wait) use cases. Jira NVGPU-66 Change-Id: I49627d1f88d52a53511a02f5de60fed6df8350de Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1676631 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: create a wrapper over sync_fencesDebarshi Dutta2018-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch constructs an abstraction to hide the sync_fence functionality from the common code. struct nvgpu_os_fence acts as an abstraction for struct sync_fence. struct nvgpu_os_fence consists of an ops structure named nvgpu_os_fence_ops which contains an API to do pushbuffer programming to generate wait commands for the fence. The current implementation of nvgpu only allows for wait method on a sync_fence which was generated using a similar backend(i.e. either Nvhost Syncpoints or Semaphores). In this patch, a generic API is introduced which will decide the type of the underlying implementation of the struct nvgpu_os_fence at runtime and run the corresponding wait implementation on it. This patch changes the channel_sync_gk20a's semaphore specific implementation to use the abstract API. A subsequent patch will make the changes for the nvhost_syncpoint based implementations as well. JIRA NVGPU-66 Change-Id: If6675bfde5885c3d15d2ca380bb6c7c0e240e734 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1667218 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support TSG IOCTL to unbind channelDeepak Nibade2018-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We so far do not support unbinding a channel from TSG explicitly through IOCTL Channel is unbound from TSG when channel fd is closed But this could create issue in case process is forked and fd is duplicated In worst case it is possible that duplicate fd is closed sometime later when TSG is active and that could lead to corruption of TSG state Fix this by implementing NVGPU_TSG_IOCTL_UNBIND_CHANNEL API This API will simply call gk20a_tsg_unbind_channel() API to unbind the channel Note that we also mark the channel has_timedout since unbound channel does not have any context of its own and it cannot serve any job Remove call to gk20a_disable_channel() while closing the channel. We do not support bare channels without TSG, and if channel is not part of TSG then it means channel is already unbound from TSG with call to NVGPU_TSG_IOCTL_UNBIND_CHANNEL, and there is nothing to do while closing the channel Bug 200327095 Jira NVGPU-229 Change-Id: Ib7f6710f0dc8125caafabe7bee737622c3dd9fa3 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1708902 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove gk20a_dbg* functionsTerje Bergstrom2018-05-09
| | | | | | | | | | | | | | | Switch all logging to nvgpu_log*(). gk20a_dbg* macros are intentionally left there because of use from other repositories. Because the new functions do not work without a pointer to struct gk20a, and piping it just for logging is excessive, some log messages are deleted. Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704148 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: created os-agnostic sim header.Antony Clince Alex2018-05-09
| | | | | | | | | | | | | | added a os-agnostic sim.h header which could be included in by any platform, moved out os specific headers to nvgpu/linux. JIRA VQRM-2368 Change-Id: I3861bfa75a6b8d2d909bc7223467fd68c208275b Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702816 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: os-agnostic segregation of sim/sim_pciAntony Clince Alex2018-05-09
| | | | | | | | | | | | | | | | | | segregated os-agnostic function from linux/sim.c and linux/sim_pci.c to sim.c and sim_pci.c, while retaining os-specific functions. renamed all gk20a_* api's to nvgpu_*. renamed hw_sim_gk20a.h to nvgpu/hw_sim.h moved hw_sim_pci.h to nvgpu/hw_sim_pci.h JIRA VQRM-2368 Change-Id: I040a6b12b19111a0b99280245808ea2b0f344cdd Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702425 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: refactored struct sim_gk20aAntony Clince Alex2018-05-09
| | | | | | | | | | | | | | | | | | moved sim buffer(send, recv and msg) from os-specific structure to OS agnostic structure. JIRA VQRM-2368 Change-Id: I10ff23fe24d86f2bd372f1bae0369cc45aadfb80 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702178 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add LDIV slowdown factor in INIT cmd.Deepak Goyal2018-05-09
| | | | | | | | | | | | | | | | PMU ucode is updated to include LDIV slowdown factor in gr_init_param command. - Defined a new version gr_init_param_v2. - Updated the PMU FW version code. - Set the LDIV slowdown factor to 0x1e by default. - Added sysfs entry to program ldiv_slowdown factor at runtime. Bug 200391931 Change-Id: Ic66049588c3b20e934faff3f29283f66c30303e4 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1674208 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: enable syncpt shim for nvlinkThomas Fleury2018-05-07
| | | | | | | | | | | | | | Get host1x node reference from c1_rp device tree node, and enable syncpoints shim in case of nvlink. JIRA EVLR-2441 JIRA EVLR-2585 Change-Id: Idbf1edf656557f2ed2d3bd27393c2f4d5d1ad75a Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1663360 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to handle nonstall interruptsDeepak Nibade2018-05-07
| | | | | | | | | | | | | | | | | | | | | Add new HAL gops.mc.isr_nonstall() to handle nonstall interrupts We already handle nonstall interrupts in nvgpu_intr_nonstall() But this API is completely in linux specific code Separate out os-independent code to handle nonstall interrupts in new API mc_gk20a_isr_nonstall() and set it to HAL gops.mc.isr_nonstall() for all existing chips Call this HAL from nvgpu_intr_nonstall() Jira NVGPUT-8 Change-Id: Iec6a56db03158a72a256f7eee8989a0a8a42ae2f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1706589 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add worker for clk arb work handlingSourab Gupta2018-05-07
| | | | | | | | | | | | | | | | | | | | | | | | Implement a worker thread to replace the workqueue based handling for clk arbiter update callbacks. The work items scheduled with the thread are of two types, update_vf_table and arb_update. Previously, there were two workqueues for handling these two work struct's separately. Now the single worker thread would process these two events. If a work item of a particular type is scheduled to be run on the worker, another instance of same type won't be scheduled, which mirrors the linux workqueue behavior. This also removes dependency on linux workqueues/work struct and makes code portable to be used by QNX also. Jira VQRM-3741 Change-Id: Ic27ce718c62c7d7c3f8820fbd1db386a159e28f2 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1706032 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fixups for tmake buildAlex Waterman2018-05-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly just including necessary includes to make sure that global function declarations actually match their implementations. Also work around pointer munging warning: /build/ddpx/linux/kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/pmu.c: In function 'nvgpu_pmu_process_init_msg': /build/ddpx/linux/kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/pmu.c:348:4: error: dereferencing type-punned pointer will break strict-aliasing rules [-Werror=strict-aliasing] (*(u32 *)gid_data.signature == PMU_SHA1_GID_SIGNATURE); Work around this warning by simply moving the type punning. This code is certainly dangerous - it assumes the endianness of the header data is the same as the machine this code is running on. Apparently it works, though, so this ignores the warning. JIRA NVGPU-525 Change-Id: Id704bae7805440bebfad51c8c8365e6d2b7a39eb Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1692454 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update clk_vin interface as per chips_aVaikundanathan S2018-05-04
| | | | | | | | | | | | | | | | clk_vin data structures updated as new calibration type (v20) is added. GP106 header does not have vin calibration type. Assuming V10 if calibration type is not V20. Add fuse calibration for V20 type. Bug 200399373 Change-Id: I9449de1ecb0d0873f3bc16f46660f93fab5b9eac Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1687591 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs to mmu fault descriptors.Vinod G2018-05-04
| | | | | | | | | | | | | | | mmu fault information for client and gpc differ on various chip. Add separate table for each chip based on that change and add hal functions to access those descriptors. bug 2050564 Change-Id: If15a4757762569d60d4ce1a6a47b8c9a93c11cb0 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704105 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add rc_type i/p param to gk20a_fifo_recoverSeema Khowala2018-05-04
| | | | | | | | | | | | | | | | | | | | | Add below rc_types to be passed to gk20a_fifo_recover MMU_FAULT PBDMA_FAULT GR_FAULT PREEMPT_TIMEOUT CTXSW_TIMEOUT RUNLIST_UPDATE_TIMEOUT FORCE_RESET SCHED_ERR This is nice to have to know what triggered recovery. Bug 2065990 Change-Id: I202268c5f237be2180b438e8ba027fce684967b6 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1662619 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename mutex to runlist_lockSeema Khowala2018-05-04
| | | | | | | | | | | | | | Rename mutex to runlist_lock in fifo_runlist_info_gk20a struct. This is good to have for code readability. Bug 2065990 Bug 2043838 Change-Id: I716685e3fad538458181d2a9fe592410401862b9 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1662587 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 18:30:14 -0400