| Commit message (Collapse) | Author | Age |
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Move much of the remaining generic MM code to a new common location:
common/mm/mm.c. Also add a corresponding <nvgpu/mm.h> header. This
mostly consists of init and cleanup code to handle the common MM
data structures like the VIDMEM code, address spaces for various
engines, etc.
A few more indepth changes were made as well.
1. alloc_inst_block() has been added to the MM HAL. This used to be
defined directly in the gk20a code but it used a register. As a
result, if this register hypothetically changes in the future,
it would need to become a HAL anyway. This path preempts that
and for now just defines all HALs to use the gk20a version.
2. Rename as much as possible: global functions are, for the most
part, prepended with nvgpu (there are a few exceptions which I
have yet to decide what to do with). Functions that are static
are renamed to be as consistent with their functionality as
possible since in some cases function effect and function name
have diverged.
JIRA NVGPU-30
Change-Id: Ic948f1ecc2f7976eba4bb7169a44b7226bb7c0b5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574499
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move functions to query preemption type names to the user of the
function: ioctl_channel.c. This removes a dependency to
<uapi/linux/nvgpu.h> from gr_gk20a.h.
JIRA NVGPU-259
Change-Id: I6cafda986eb4659fcfc1b19eac77e43aaaeaec76
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577248
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Function to query interleave name depends on IOCTL flag definition.
Move that code to fifo_gk20a.c to remove Linux dependency in header.
Change-Id: I6d6a80e550bf30973b2be09febc2347890b77d25
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577249
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Updated gk20a_gr_handle_class_error with
sub channel info, mme related info.
Also printing the correct method info from
isr_data->offset by left shifting it by 2.
Generated following hw definitions for gk20a/gm20b/gp10b/gp106
to dump relevant data in gk20a_gr_handle_class_error:
gr_trapped_addr_mme_generated_v
gr_trapped_addr_datahigh_v
gr_trapped_addr_priv_v
gr_trapped_data_lo_r
gr_trapped_data_mme_r
gr_trapped_data_mme_pc_v
Bug 2003671
Change-Id: I02e15ef16d7498b6a7dc2af547a14e84d570e8a7
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574061
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add functions to get per-chip cache maintenance timeout overrides.
JIRA: NVGPUGV100-GV100
Change-Id: Ie14efc616e7af52ede60031c789bd2ae70857a6e
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1582768
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Add methods to read/write falcon mailbox
at interface layer
- Created falcon mailbox read/write HAL
- Added HAL methods to read/write mailbox
- Added macro to get next block based on address
- Added macro to get IMEM tag using IMEM address
- Added ucode header format
Change-Id: I879b1df4538d403cac40fd4ed6e723190f62922c
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
(cherry picked from commit 30e8b76a7be9d9e6d8225bdc08e441f408692f63)
Reviewed-on: https://git-master.nvidia.com/r/1509469
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Created "mem_unlock" HAL under fb to support memory
unlock
- Called as part of gk20a_finalize_poweron() if memory unlock
support needed by checking HAL
- Assigned "mem_unlock" HAL to NULL for chips which don't
need memory unlocks.
Change-Id: I68d0910f15d293feaacfcbf6bd17ecccd3b5219d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
(cherry picked from commit 586894eb84860bbbe4c75dae4715bdf27432a480)
Reviewed-on: https://git-master.nvidia.com/r/1564703
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Added "nvgpu_flacon nvdec_flcn" member to gk20a
- Added base address & flacon id of NVDEC falcon
- Included nvdec falcon to access common falcon code
- Enabled nvdec falcon support for GP106
- Disabled nvdec falcon support for iGPU
- Made call to enable nvdec falcon support if supported
Change-Id: Ia928d082275a720e4e8c6852384e489c8ec444f8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
(cherry picked from commit 3d80aeff295bad8365af6022555ad151f1a32cf6)
Reviewed-on: https://git-master.nvidia.com/r/1564305
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Patch buffer can hold 128 u32 entries. Each patch write
takes total of 2 u32 entries, 1 u32 for addr and 1 u32
for data. Ideally 64 entries could be written before buffer
overflows. Driver patch some things when creating the channel,
and later when context switch type is changed after channel is loaded.
Reset patch_ctx.data_count before beginning patch
write otherwise system might not be in a state to accept all
patch writes even if patch buffer has valid entries.
If the patch buffer has non-zero entries, then the patch buffer
would be read and all pri writes would be sent out. Once done,
ucode updates the main header patch buffer count to 0.
Without this fix, below priv errors seen on t186 platforms
SYS Write error for ADR 0, INFO 0d000200 and CODE badf1100
Error info decodes as:
NV_PPRIV_SYS_PRIV_ERROR_INFO R[0x00122128]
SUBID [29:24] 13 (?)
LOCAL_ORDERING [22:22] 0 (I)
PRIV_LEVEL [21:20] 0 (I)
SENDING_RS [17:12] 0 (I)
PENDING [ 9: 9] 1 (?)
ORPHAN [ 8: 8] 0 (I)
PRIV_MASTER [ 5: 0] 0 (I)
Ctxsw ucode(subid 13 i.e. 0xd) makes only few pri transactions
at priv level 0. Patch buffer pri writes are one of those.
Bug 200350539
Change-Id: If9e71b5fef4d85600d72a8a633a082d9261c3e1b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1581591
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Use priv_ring.isr gops to call priv ring
interrupt handler
Bug 200350539
Change-Id: I21b39bd19d281290fee6728286b0a24a32358ae4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1570372
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Convert the work_struct used by the vidmem background clearing to
a thread to make it more cross platform. The thread waits on a
condition variable to determine when work needs to be done. The
signal comes from the DMA API when it enqueues a new nvgpu_mem that
needs clearing.
Add logic for handling suspend: the CE cannot be accessed while
the GPU is suspended. As such the background thread must be paused
while the GPU is suspended and the CE is not available.
Several other changes were also made:
o Move the code that enqueues a nvgpu_mem from the DMA API
code to a function in the VIDMEM code.
o Move nvgpu_vidmem_get_pending_alloc() to the Linux specific
code as this function is only used there. It's a trivial
function that QNX can easily implement as well.
o Remove the was_empty logic from the enqueue. Now just always
signal the condition variable when anew nvgpu_mem comes in.
o Move CE suspend to after MM suspend.
JIRA NVGPU-30
JIRA NVGPU-138
Change-Id: Ie9286ae5a127c3fced86dfb9794e7d81eab0491c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574498
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Handle the possibility of failing gr init due to smid table initialization
failures
bug 2004378
Change-Id: I904b918a0ea31c32292edb3ab8ac3b1459c38a28
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1581661
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Remove unused HAL for restore_context_header.
This function pointer is not getting used since
no need for restoring context header during golden
context creation.
Change-Id: I0fb018226c7560fdb69f77a4f53387d39cc79e97
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1581431
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move sched parameter APIs to be Linux specific implementation. At
the same time the sched_ctrl fields were moved to nvgpu_os_linux.
JIRA NVGPU-259
Change-Id: I2397e2602e1c4783f2bebf3aec462634b7f86d4a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1580649
GVS: Gerrit_Virtual_Submit
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Use mc reset HAL function to reset perfmon unit.
This will take care of delays after writing to
mc_enable register.
Change-Id: I6118bdd2a9fc9192f7ffc44617a170b7982c26ba
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1581753
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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ecc_gk20a.h has no use for Linux IOCTL interface definitions. Remove
the stray #include.
JIRA NVGPU-259
Change-Id: I47a837ac86f1f83976d94cb9b30082fee827445a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1580678
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Refactor the last nvgpu_vm functions from the mm_gk20a.c code. This
removes some usages of dma_buf from the mm_gk20a.c code, too, which
helps make mm_gk20a.c less Linux specific.
Also delete some header files that are no longer necessary in
gk20a/mm_gk20a.c which are Linux specific. The mm_gk20a.c code is now
quite close to being Linux free.
JIRA NVGPU-30
JIRA NVGPU-138
Change-Id: I72b370bd85a7b029768b0fb4827d6abba42007c3
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566629
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move most of the dma_buf usage present in the mm_gk20a.c code
out to Linux specific code and some commom/mm code. There's
two primary groups of code:
1. dma_buf priv field code (for holding comptag data)
2. Comptag usage that relies on dma_buf pointers
For (1) the dma_buf code was simply moved to common/linux/dmabuf.c
since most of this code is clearly Linux specific.
The comptag code was a bit more complicated since there is two
parts to the comptag code. Firstly there's the code that manages
the comptag memory. This is essentially a simple allocator. This
was moved to common/mm/comptags.c since it can be shared across
all chips. The second set of code is moved to
common/linux/comptags.c since it is the interface between dma_bufs
and the comptag memory.
Two other fixes were done as well:
- Add struct gk20a to the comptag allocator init so that
the proper nvgpu_vzalloc() function could be used.
- Add necessary includes to common/linux/vm_priv.h.
JIRA NVGPU-30
JIRA NVGPU-138
Change-Id: I96c57f2763e5ebe18a2f2ee4b33e0e1a2597848c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566628
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Allocate syncpt_mem only if is not allocated.
JIRA GPUT19X-2
Change-Id: I081d27bb784fbe653890b5f8d36a4295c7ccc19b
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1580731
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use abstract nvgpu_rwsem as TSG channel list lock instead of the Linux
specific rw_semaphore.
JIRA NVGPU-259
Change-Id: I41a38b29d4651838b1962d69f102af1384e12cb6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1579935
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This change contains a generic cleanup of linux dependent parts of the
dbg_gpu_gk20a.* files. The following changes have been made
1) Moving methods into ioctl_dbg.* inside common/linux/
2) The structures dbg_session_gk20a and dbg_session_channel_data have
been split into two parts. struct device *dev is removed from
struct dbg_session_gk20a and instead packed into struct
dbg_session_gk20a_linux alongwith dbg_session_gk20a and is moved into
ioctl_dbg. dbg_session_gk20a is now rid of any linux dependencies and
remains in dbg_gpu_gk20a. Similarly, struct file is removed from
struct dbg_session_channel_data and is now packed into struct
dbg_session_channel_data_linux alongwith dbg_session_channel_data and
is moved into ioctl_dbg. struct dbg_session_channel_data is now rid of
linux dependencies and remains in dbg_gpu_gk20a.
3) A callback function is added in order to release the
dbg_session_channel_data.
JIRA NVGPU-205
Change-Id: I853da6dfbf9a96b7cd210beb77f2304445ff7ea6
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1575191
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move rest of CDE structures to common/linux. This includes moving
the per-chip firmware file interpretation functions, and removing CDE
ops from HAL and adding it to nvgpu_os_linux.
JIRA NVGPU-259
Change-Id: I59d8f44bddadecef81ad3c455b363a14034c5e13
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1570403
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Replace use of ioctl structure warpstate with internal
nvgpu_warptate.
JIRA NVGPU-259
Change-Id: I5170364d0443235cee471b87fa332fc09588f5d3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1578684
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- timers and bug header files should be
included directly. Linux maybe getting
it via indirect includes. Also, QNX
requires non-static function to be
declared explicitly.
Change-Id: I2458654f535d8079347e4a0be744530f56388238
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577527
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
Tested-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Replace existing usages of wait_queue_head_t with struct nvgpu_cond and
using the corresponding APIs in order to reduce Linux dependencies in NVGPU.
JIRA NVGPU-205
Change-Id: I85850369c3c47d3e1704e4171b1d172361842423
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1575778
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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linux/debugfs.h was included in gk20a.h because of the debugfs entry
bios_blob, which can be used for checking contents of VBIOS. That
has never been used, so instead of abstracting it, this patch removes
the feature altogether.
Two files were using debugfs but did not #include <linux/debugfs.h>.
They failed to build now that gk20a.h no longer #includes it, so
added explit #include.
JIRA NVGPU-259
Change-Id: Ie1ea9be1a8920441b1616f34e64e505e6e10e38c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1570404
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Abstract implementation of rw_semaphore. In Linux it's implemented
in terms of rw_semaphore. Change deterministic_busy to use the new
implementation.
JIRA NVGPU-259
Change-Id: Ia9c1b6e397581bff7711c5ab6fb76ef6d23cff87
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1570405
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In gk20a.h, we use these multichar constants
'DONE', '0R32', '0W32'
But these constants fail compilation on some cross-os compilers
Hence remove them by creating a specific MULTICHAR_TAG()
All the User space components also form these constants in similar
fashion
Jira NVGPU-259
Change-Id: Ibe83617a8d15b657e450fdd59dbc171b3d822842
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1576933
Reviewed-by: Automatic_Commit_Validation_User
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We use struct stack_trace in struct channel_gk20a_ref_action
But since channel_gk20a_ref_action is needed only if
GK20A_CHANNEL_REFCOUNT_TRACKING is set, protect it with that config
Jira NVGPU-259
Change-Id: I6b2d6f470bf924bb1ddfd31ba9968b56c63c2372
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1576929
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Enhanced pbdma error output to print pbdma interrupt
error.
Generated following hw definitions to dump relevant data:
pbdma_gp_shadow_0_r
pbdma_gp_shadow_1_r
Updated gk20a_dump_pbdma_status to dump this additional
info:
pbdma_gp_put_r
pbdma_gp_get_r
pbdma_gp_shadow_0_r
pbdma_gp_shadow_1_r
Bug 2003671
Change-Id: Iaa75d936e00470a2b8d1151f60dbeb741b3f9bce
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1572182
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add abstraction of IO aperture accessors. Add new functions
gk20a_io_exists() and gk20a_io_valid_reg() to remove dependencies to
aperture fields from common code.
Implement Linux version of the abstraction by moving gk20a_readl()
and gk20a_writel() to new Linux specific io.c. Move the fields
defining IO aperture to nvgpu_os_linux.
Add t19x specific IO aperture initialization functions and add t19x
specific section to nvgpu_os_linux.
JIRA NVGPU-259
Change-Id: I09e79cda60d11a20d1099a9aaa6d2375236e94ce
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569698
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Split the core vidmem allocation from the Linux component of vidmem
allocation. The core vidmem allocation allocates the nvgpu_mem struct
that defines the vidmem buffer in the core MM code. The Linux code
now allocates some Linux specific stuff (dma_buf, etc) and also
allocates the core vidmem buf.
JIRA NVGPU-30
JIRA NVGPU-138
Change-Id: I88e87e0abd5ec714610eacc6eac17e148bcee3ce
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1540708
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Rename the VIDMEM APIs to be prefixed by nvgpu_ to ensure
consistency and that all the non-static vidmem functions are
properly namespaced.
JIRA NVGPU-30
JIRA NVGPU-138
Change-Id: I9986ee8f2c8f95a4b7c5e2b9607bc1e77933ccfc
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1540707
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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For sync-point read map:
1. Added nvgpu_mem memory allocator in gk20a struct and
allocated memory for this in gk20a_finalize_poweron()
and freed this memory in gk20a_remove().
2. Added "u64 syncpt_ro_map_gpu_va" in vm_gk20a struct
for read map in vm.
Added nvgpu_quiesce() in nvgpu_remove() before freeing
syncpoint read map to ensure that nvgpu is idle.
JIRA GPUT19X-2
Change-Id: I7cbfec57f0992682dd833a1b0d92d694bcaf1eb3
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514338
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For non fake mmu fault, both tsg and ch pointers
could be valid. If tsg pointer is non null, issue
ctxsw_trace for tsg instead of channel only.
Change-Id: I161c40e8d43c7ae4d953ef4768ad75d4e993c87e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577915
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Do not return error if channel to be removed has
NEXT set. This is a WAR until proper fix is
identified and implemented.
Bug 200327095
Change-Id: Ia77f3b834e8e577ac2dad8281f1dd562079adcef
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577133
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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While unbindin a channel from TSG, we first disable all the channels,
then examine the status of channel being removed in
gk20a_fifo_tsg_unbind_channel_verify_status(), and if this API fails we
re-enable all the channel and kill whole TSG
And in gk20a_fifo_tsg_unbind_channel_verify_status() we first check ctx_reload
and fault status and then check NEXT status
If channel has NEXT set we bail out
But since we have already changed the TSG ctx_reload status re-enabling all
channels in TSG might cause issues
Hence fix this by correcting sequence so that we first ensure that NEXT is
not set on channel and then only alter the status
Bug 200327095
Change-Id: I4f0786bc507fad5462d4cdd8d0ca91ea611ee3b5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1575905
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Some GPUs require all channels to be on TSG and also have larger than 4GB
vidmem sizes which were not supported on the previous CE2 code.
This change creates a new property to track if the copy engine needs to
encapsulate its kernel context on tsg and also modifies the copy engine code
to support much larger copies without dramatically increasing the PB size.
JIRA: EVLR-1990
Change-Id: Ieb4acba0c787eb96cb9c7cd97f884d2119d445aa
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1573216
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
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Change the wait for work pending condition to interruptible in the
channel worker thread, as there's no reason to be noninterruptible.
A noninterruptible wait, even one with a timeout, causes the worker to
be printed in the Linux blocked tasks list which is confusing.
Change the cond signal to interruptible to match this.
Change-Id: I71d848b7f449a5d53fecae90c6a450c98c675c7f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1570166
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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There is no current need for a virtualized version of
nvgpu_dbg_gpu_ioctl_write_single_sm_error_state, so return
-ENOSYS when virtual.
Bug 200331110
Change-Id: I2a8cf07b2962de4c91b752b276678bee4eea6e80
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1568906
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Remove an SGL reference from the mm_gk20a.c code. This code is
common code and as such all linuxisms need to be fixed. It just
so happens that this particular function is only used by the
CDE code which is only present in Linux. So simply move this
function over to the CDE code.
JIRA NVGPU-30
JIRA NVGPU-225
JIRA NVGPU-226
Change-Id: Ifb0cb427c742c6d9cada382ace4a52f52474c379
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1576436
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Remove phys_addr_t from common code and replace it with u64. This
faciliates QNX compiling the common code since phys_addr_t is a
Linux specific type.
JIRA NVGPU-30
JIRA NVGPU-226
Change-Id: I15fe2078f9cd0b07c7e90ad6e359c493afa56714
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1576432
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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As with GR's semaphore acquires that timeout, report
NVGPU_CHANNEL_GR_SEMAPHORE_TIMEOUT to userspace in the error notifier
also when a semaphore acquire timeout interrupt is received from PBDMA.
This timeout is used when the kernel watchdog timer is enabled.
Bug 1782480
Change-Id: I1ceb8632548c5e89febb2b80a5850116a2d4b670
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574293
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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The functions are gk20a_user_init() and gk20a_user_deinit() are
defined in ioctl.c. Move declaration of the functions to new
header file ioctl.h.
JIRA NVGPU-259
Change-Id: If348b51e9032083f252a7c7717ed7bc153dbba52
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569696
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gk20a->busy_lock is a Linux specific rw_semaphore used only
by Linux code. Move it to os_linux.
JIRA NVGPU-259
Change-Id: I220a8a080a5050732683b875d3c1d0539ba0f40e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569695
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Below APIs are already declared in ioctl_channel.h, and hence remove duplicate
declaration from channel_gk20a.h
gk20a_channel_open()
gk20a_channel_ioctl()
gk20a_channel_release()
And move declaration of gk20a_channel_open_ioctl() from channel_gk20a.h to
ioctl_channel.h
Jira NVGPU-259
Change-Id: I46702ca481e41a19f92f4fe0169f95e31360abe0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1573106
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Pre-os firmware takes care, among others, of the control of FAN till
the driver takes over its control. On some GPUs not enabling this FW can lead
tp physical board damage, hence it is needed to run this firmware.
JIRA: NVGPUGV100-9
Change-Id: I18d54cfd5eb64ecec79c5dae67ac8d5bb1facf36
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1549035
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This is needed to disable/enable features on new chips
Bug 200352825
Change-Id: I02eb58e6fdd554ed20866fe8a8553a667541f512
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574481
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Split VIDMEM support into its own code files organized as such:
common/mm/vidmem.c - Base vidmem support
common/linux/vidmem.c - Linux specific user-space interaction
include/nvgpu/vidmem.h - Vidmem API definitions
Also use the config to enable/disable VIDMEM support in the makefile
and remove as many CONFIG_GK20A_VIDMEM preprocessor checks as possible
from the source code.
And lastly update a while-loop that iterated over an SGT to use the
new for_each construct for iterating over SGTs.
Currently this organization is not perfectly adhered to. More patches
will fix that.
JIRA NVGPU-30
JIRA NVGPU-138
Change-Id: Ic0f4d2cf38b65849c7dc350a69b175421477069c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1540705
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Currently if channel has NEXT bit set while closing the channel we just print
an error and continue channel unbind sequence from TSG
But since channel with NEXT set is active killing it can potentially corrupt
the TSG context and cause unpredictable errors on remaining channels/TSG
Hence fix this by killing whole TSG context if channel being closed has
NEXT bit set
if gk20a_fifo_tsg_unbind_channel() API returns error, kill the TSG
otherwise continue with channel unbind sequence
Bug 200327095
Change-Id: I2abf1a3db8ba6f105b6ca86e78006c7b2a7726cc
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1568566
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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