| Commit message (Collapse) | Author | Age |
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Pass flags as mask in event initialization
JIRA: DNVGPU-189$
Change-Id: Ied22a585a8f59f44e577bc678f8cef380432c9a2
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1252474
(cherry picked from commit 56fa34b8ac0ebafaf09a8760bec6200adf9f3c39)
Reviewed-on: http://git-master/r/1280886
GVS: Gerrit_Virtual_Submit
Tested-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In gk20a_busy() we check if dev is NULL and return -ENODEV if so. But
before that we've already dereferenced dev by passing it to
get_gk20a(). Defer call to get_gk20a() until after the NULL check.
Bug 200192125
Change-Id: I943a9e96d13ff8cb4333fe20a941c8e95d159a66
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1280349
GVS: Gerrit_Virtual_Submit
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Fix slab-out-of-bounds issue reported by KASAN
[ 28.464077] BUG: KASAN: slab-out-of-bounds in
gr_gk20a_init_map_tiles+0x624/0x708 at addr ffffffc1a098ee01
...
[ 28.503241] INFO: Allocated in gr_gk20a_init_map_tiles+0x2dc/0x708
age=11 cpu=5 pid=1
out-of-bound access from below 3 stacks :
[1]
[ 28.782886] [<ffffffc0007d5f64>] gr_gk20a_init_map_tiles+0x624/0x708
[ 28.789228] [<ffffffc0007eadf0>] gk20a_init_gr_support+0x2d0/0xeb0
[ 28.795397] [<ffffffc00079d9c8>]
gk20a_pm_finalize_poweron+0x738/0xd10
[2]
[ 29.268070] [<ffffffc0007d618c>] gr_gk20a_zcull_init_hw+0x144/0x730
[ 29.274329] [<ffffffc0007d6a00>] gk20a_init_gr_setup_hw+0x288/0x1530
[ 29.280677] [<ffffffc0007eac6c>] gk20a_init_gr_support+0x14c/0xeb0
[ 29.286938] [<ffffffc00079d9c8>]
gk20a_pm_finalize_poweron+0x738/0xd10
[3]
[ 50.076223] [<ffffffc000d1df14>]
gr_gk20a_setup_rop_mapping+0x5e4/0x2018
[ 50.082913] [<ffffffc000d2559c>] gr_gk20a_init_fs_state+0x80c/0x1028
[ 50.089259] [<ffffffc000ddcbc8>] gr_gm20b_init_fs_state+0xc8/0x960
[ 50.095430] [<ffffffc000e413f8>] gr_gp10b_init_fs_state+0x5c0/0x5d8
[ 50.101687] [<ffffffc000d2ed30>] gk20a_init_gr_setup_hw+0x1b48/0x2418
[ 50.108115] [<ffffffc000d50bc0>] gk20a_init_gr_support+0x19e0/0x1ab0
[ 50.114457] [<ffffffc000cc7af8>]
gk20a_pm_finalize_poweron+0xd20/0x1558
Fix this by adding below
- allocate gr->map_tiles[] with size of (num_gpc * num_tpc_per_gpc)
intead of num_gpc
- add new static API gr_gk20a_get_map_tile_count() which returns
tile count for given index, and returns 0 for out-of-bounds access
Bug 200257557
Change-Id: If572837ffb661f92a21be5ce855d0146b2609cb0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1279411
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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And reduce pri timeout to match PCIE specs
bug 200246808
Change-Id: I0225ae964b5635665fe774c43f773d0ce86650ab
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1264179
(cherry picked from commit 1c3dbf8324b7ec5d06bd0e57e7deee9a1c8e9411)
Reviewed-on: http://git-master/r/1280328
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add a platform flag and logic to disable ASPM on boot if a
platform does not want ASPM enabled.
Bug 200256272
Change-Id: I378997290377ef8ffa21bf8e7f3f59fa134b3d4d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1263271
(cherry picked from commit 01e4700b74f4b4c6f0b9ffb40747653f2b63ea3c)
Reviewed-on: http://git-master/r/1274477
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Handle possible asynchronous GPU driver shutdown more gracefully.
This occurs when the GPU disappears from the PCI bus, for example,
if it overheats or detects an over current event.
Also add a preprocessor check to make sure that the
gk20a_channel_cancel_pending_sema_waits()
is always defined. In some builds CONFIG_SYNC is disabled but the
gk20a_remove_support() code does not check for this.
Bug 1816516
Bug 1807277
Change-Id: I932e312291c5c6a6ac5e13525ce8ca56a1be3652
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250028
(cherry picked from commit 337810f8c478238a38d8553c1492622d5fa9aafa)
Reviewed-on: http://git-master/r/1274476
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move the code that waits for deferred interrupts to nvgpu_common.c and
make it global. Also rename that function to use nvgpu_ as the function
prefix.
Bug 1816516
Bug 1807277
Change-Id: I42c4982ea853af5489051534219bfe8b253c2784
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250027
(cherry picked from commit cb6fb03e20b08e5c3606ae8a5a9c237bfdf9e7da)
Reviewed-on: http://git-master/r/1274475
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fix miscellaneous issues seen during driver shutdown.
o Make sure pointers are valid before accessing them.
o Busy the GPU during channel timeout.
o Cancel delayed work on channels.
o Avoid access to channels that may have been freed.
Bug 1816516
Bug 1807277
Change-Id: I62df40373fdfb1c4a011364e8c435176a08a7a96
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250026
(cherry picked from commit 64a95fc96c8ef7c5af9c53c4bb3402626e0d2f60)
Reviewed-on: http://git-master/r/1274474
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In many helper functions like gk20a_readl() the code assumed that
the GPU is present and registers and available. However, during
GPU shutdown this may not be the case.
In theory the driver should not be accessing GPU registers during
GPU shutdown (since shutdown is triggered by GPU registers being
unavailable) but these changes handle any missed cases where this
may happen.
This goes for GPU device access as well. Many parts of the code
assume that if the struct gk20a is valid, the the GPU dev must be
there are well. This isn't always the case, it seems.
Bug 1816516
Bug 1807277
Change-Id: Icaf6fd56ab7860724e77bda0f5e8d48f0da15642
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250024
(cherry picked from commit e8c9997b2d7cd424d798ecfce1307e6193c0cf32)
Reviewed-on: http://git-master/r/1274473
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Enable FECS ctxsw tracing for gp106. Ensure that FECS records
have been written to memory before accessing the ring. Update
read index only once all records have been processed.
Jira EVLR-424
Change-Id: I1a21f841fcce1588397408906d77e2c3bf4a8c01
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1258243
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We use GPU reference clock as a divider. Check before division that
reference clock is not zero.
Change-Id: Ie453a78b422b2e740daeb7c12ce5b06faa52ba76
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1275743
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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In gk20a_submit_prepare_syncs(), after we have allocated wait_cmd
we check the results. If we failed to allocate wait_cmd, we still
jump to the error label that tries to free wait_cmd.
Create an own error labal for allocation before wait_cmd, and use
that if we fail to allocate wait_cmd.
Similarly create an error label for incr_cmd, and use that only once
incr_cmd has actually been allocated.
Change-Id: I1f8bc1d947c524038f5f237358a5e6b0dc2e6ac3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1275742
GVS: Gerrit_Virtual_Submit
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When allocating job channel_gk20a_job structure we assign the result
of allocation to *job_out, but we check the result of allocation
in job_out.
Change the check to check for result in *job_out.
Change-Id: Ia170cfa2dd5730665434b4c223c5a2f9502c744d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1275741
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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Fix slab-out-of-bounds issue reported by KASAN
[ 29.922710] BUG: KASAN: slab-out-of-bounds in
gr_gk20a_init_fs_state+0x1bc/0x898 at addr ffffffc1a0988c04
...
[ 29.961820] INFO: Allocated in gr_gk20a_init_gr_config+0x380/0x1b20
age=374 cpu=5 pid=1
...
Out-of-bound access from
[ 30.241943] [<ffffffc0007d2674>] gr_gk20a_init_fs_state+0x1bc/0x898
[ 30.248205] [<ffffffc000839a2c>] gr_gm20b_init_fs_state+0x4c/0x5c8
[ 30.254381] [<ffffffc000871670>] gr_gp10b_init_fs_state+0x160/0x3a8
[ 30.260643] [<ffffffc0007d70ec>] gk20a_init_gr_setup_hw+0x974/0x1530
[ 30.266991] [<ffffffc0007eac6c>] gk20a_init_gr_support+0x14c/0xeb0
[ 30.273164] [<ffffffc00079d9c8>]
gk20a_pm_finalize_poweron+0x738/0xd10
[ 30.279684] [<ffffffc00079dfd0>] gk20a_pm_runtime_resume+0x30/0x58
Fix this by using a separate API gr_gk20a_get_tpc_count()
which returns tpc count for a gpc and returns 0
if gpc index is greater than available gpcs
Bug 200257557
Change-Id: I78856ca93c0381cb4bcef7a56a5210fa269cf3ac
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1277692
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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We use &ch->error_notifier_mutex to protect
writes and free of error notifier
But we currently do not protect reading of
notifier in gk20a_fifo_set_ctx_mmu_error()
and vgpu_fifo_set_ctx_mmu_error()
Add new API gk20a_set_error_notifier_locked()
which is same as gk20a_set_error_notifier()
but without the locks.
In *_fifo_set_ctx_mmu_error() APIs, acquire
the mutex explicitly, and then use this new
API
gk20a_set_error_notifier() will now just call
gk20a_set_error_notifier_locked() within
a mutex
Bug 1824788
Bug 1844312
Change-Id: I1f3831dc63fe1daa761b2e17e4de3c155f505d6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1273471
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Call gk20a_driver_start_unload() in the beginning
of gk20a_pm_shutdown() so that we prevent new
calls to gk20a_busy()
Bug 200265373
Change-Id: I240cab4b505be4928341ab3deb13f37241d27aeb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1275486
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Process long regops lists in 4-kB fragments, overcoming the overly
low limit of 128 reg ops per IOCTL call. Bump the list limit to 1024
and report the limit in GPU characteristics.
Bug 200248726
Change-Id: I3ad49139409f32aea8b1226d6562e88edccc8053
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/1253716
(cherry picked from commit 22314619b28f52610cb8769cd4c3f9eb01904eab)
Reviewed-on: http://git-master/r/1266652
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- PG statistics read support for multiple engines
- updated stat_dmem_offset member to array to hold
dmem offset of PG engines
- PMU allocates memory in DMEM for each PG engine requested,
updated gk20a_pmu_get_elpg_residency_gating() to get
engine statistics for requested PG engine
JIRA DNVGPU-71
Change-Id: I2ddade37f85716f757bf33034dbff816184577eb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1250506
(cherry picked from commit 68ba7a97d6662b87d0e489365d8afb8e2d237a03)
Reviewed-on: http://git-master/r/1270972
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Added enable_mscg, mscg_enabled & mscg_stat flags,
mscg_enabled flag can be used to controll
mscg enable/disable at runtime along with mscg_stat flag.
- Added defines & interface to support ms/mclk-change/post-init-param
- Added defines for lpwr tables read from vbios.
- HAL to support post init param which is require
to setup clockgating interface in PMU & interfaces used during
mscg state machine.
- gk20a_pmu_pg_global_enable() can be called when pg support
required to enable/disable, this also checks & wait
if pstate switch is in progress till it complets
- pg_mutex to protect PG-RPPG/MSCG enable/disable
JIRA DNVGPU-71
Change-Id: If312cefc888a4de0a5c96898baeaac1a76e53e46
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247554
(cherry picked from commit e6c94948b8058ba642ea56677ad798fc56b8a28a)
Reviewed-on: http://git-master/r/1270971
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add defines and interface structures used for sending PMU
messages to control RPPG.
JIRA DNVGPU-71
Change-Id: Ibec975f3c976619542d8f088b24271796a03f03c
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247487
(cherry picked from commit dd3826abca0a51d473d5d9cb25dc84cada9e7878)
Reviewed-on: http://git-master/r/1270793
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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graphics and compute preemption modes are currently
defined as int
But it is more logical to have them as unsigned int
Also, we treat preemption modes as unsigned almost
everywhere in the code
Fix prints in gk20a_fifo_sched_debugfs_seq_show() to
print U32_MAX with %d which is same as printing -1
Bug 200263471
Change-Id: Iabd0ee3923b76d81620898e90a9b1fc5dd75b530
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1272514
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fix the build break caused by
"commit : I88d94542092f92e68dc63c40444a70991d1f6129"
Change-Id: Id457c26b17ba8fc05e26fb5ad3b3a4873362b950
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: http://git-master/r/1274496
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
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Fix use-after-free overity defect in page allocator. The alloc struct
was getting used after a call for __gk20a_free_pages() which frees
the alloc struct passed in.
Coverity ID: 468942
Bug 200192125
Change-Id: I4f5d32f245efae967050f93c7806290b4bf3591c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1272730
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move the sw initialization of the gpcclk from gpu rail ungate path
to the nvgpu probe path. This allows gpcclk to register itself
successfully with CCF and makes it discoverable for other clients
early on during boot.
Bug 200233943
Bug 200259437
Change-Id: I88d94542092f92e68dc63c40444a70991d1f6129
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: http://git-master/r/1265549
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
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Lock only for modifications to the tsg channel list, and allow multiple
concurrent readers.
Bug 1848834
Bug 1814773
Change-Id: Ie3938d4239cfe36a14211f4649ce72b7fc3e2fa4
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1269579
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- pmu_init_powergating loops & init multiple
PG engines based on PG engines supported
- generalize pg init param HAL to support
multiple PG-engine init based on PG engine
parameter
- HAL's to return supported PG engines on chip &
its sub features of engine.
- Send Allow/Disallow for PG engines which are
enabled & supported.
- Added defines for pg engines
JIRA DNVGPU-71
Change-Id: I236601e092e519a269fcb17c7d1c523a4b51405f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247409
(cherry-picked from commit 1c138cc475bac7d3c3fbbd5fb18cfcb2e7fdf67a)
Reviewed-on: http://git-master/r/1269319
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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If channel context has separate context header then
copy required info into context header instead of
main context header.
JIRA GV11B-21
Change-Id: I5e0bdde132fb83956fd6ac473148ad4de498e830
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1229243
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Change "check" to "expired" in nvgpu_timeout_check* and append _expired
to nvgpu_timeout_peek to clarify what the boolean-like return value
means and thus avoid bugs.
Bug 200260715
Change-Id: I47e097ee922e856005a79fa9e27eddb1c8d77f8b
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1269366
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fix a memory leak introduced when making the priv struct for
TSGs.
Fix another memory leak when introducing a priv struct for
channels.
Bug 1816516
Change-Id: I7b0e62bb6352f7e65acb5501cab9cef055d1f535
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1266889
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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When the user-supplied ioctl argument size is too large, just return
-EINVAL from the ioctl instead of crashing on a BUG_ON (for as, ctrl,
ctxsw, dbg and tsg nodes - channel and sched nodes are already okay).
Bug 1849661
Change-Id: I5b0d1d0c4ee47ce0136c424dda5975353f110c7e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1266606
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Store pending sema waits so that they can be explicitly handled when
the driver dies. If the sema_wait is freed before the pending wait is
either handled or canceled problems occur.
Internally the sync_fence_wait_async() function uses the kernel timers.
That uses a linked list of possible events. That means every so often
the kernel iterates through this list. If the list node that is in the
sync_fence_waiter struct is freed before it can be removed from the
pending timers list then the kernel timers list can be corrupted. When
the kernel then iterates through this list crashes and other related
problems can happen.
Bug 1816516
Bug 1807277
Change-Id: Iddc4be64583c19bfdd2d88b9098aafc6ae5c6475
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250025
(cherry picked from commit 01889e21bd31dbd7ee85313e98079138ed1d63be)
Reviewed-on: http://git-master/r/1261920
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Ensure that any open channel is definitely closed before freeing it.
Bug 1816516
Bug 1807277
Change-Id: I7f100db5ab6834176ec97d22374646d3336f2856
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250023
(cherry picked from commit 56f1b4b4312c5900f1c27eba55ad970c4b264f24)
Reviewed-on: http://git-master/r/1261919
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Allow forced channel freeing. This is useful when the driver is
being cleaned up and the gk20a_wait_until_counter_is_N() could
potentially hang.
Bug 1816516
Bug 1807277
Change-Id: I711f5f3f6413d0bb30b4857e785ca3b504b494ee
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250022
(cherry picked from commit e132d0e5ae77d758680ac708622a4883bbd69ba3)
Reviewed-on: http://git-master/r/1261918
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Reboot the GPU when it disappears instead of just printing a warning
message.
Bug 1805082
Bug 1816516
Bug 1807277
Change-Id: Ifd23c7e6876d5ea86032a82b7181e31d54e877b5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1260898
(cherry picked from commit 4fdc48c4e6dddf4299a49f387ac90404dd38950f)
Reviewed-on: http://git-master/r/1261917
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Check if the GPU is present after each register read. If the a register
read returns 0xffffffff then it's possible the GPU has fallen off the
bus for some reason or another. However, to confirm that a register read
is due to a dead GPU vs just a 0xffffffff being returned by happenstance
the chip ID register is read which should never return 0xffffffff. If
that read returns 0xffffffff as well then certainly the GPU is dead.
Bug 1805082
Bug 1816516
Bug 1807277
Change-Id: I4de61b56289217d9c0d8167e84615a67c8bde8a9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1239518
(cherry picked from commit bd50828de20aba9b2887ee99c2269602c21a793f)
Reviewed-on: http://git-master/r/1261916
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Allow SW to force a semaphore release. Typically SW waits for a
semaphore to reach the value right before the semaphore release
value before doing a release. For example, assuming a semaphore
is to be released by SW by writing a 10 into the semaphore, the
code waits for the semaphore to get to 9 before writing 10.
The problem with this happens when trying to shutdown the GPU
unexpectedly. When aborting a channel after the GPU has terminated
the GPU is potantially no longer processing anything. If a SW
semaphore release is waiting on the semaphore to reach N-1 before
writing N to the semaphore N-1 may never get written by the GPU.
This obviously causes a hang in the SW shutdown. The solution is
to let SW force a semaphore release in the channel_abort case.
Bug 1816516
Bug 1807277
Change-Id: Ib8b4afd86102eacf372362b1748fb6ca04e6fa66
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250021
(cherry picked from commit 2e9fa40902d2c4d5a1febe0bf2db420ce14bc633)
Reviewed-on: http://git-master/r/1261915
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add a private tsg struct for the TSG file descriptors. This allows
the TSG files to retain access to the gk20a struct without the TSG
data structure still being available.
Bug 1816516
Bug 1807277
Change-Id: If0e41d912bebb7906d72e7eee641f47604a16494
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250020
(cherry picked from commit 5d8dbbb939e10fecde341891807a0201a63b2b23)
Reviewed-on: http://git-master/r/1261914
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The private_data field in the file pointer passed to release() for
channels originally pointed directly to the referenced channel. The
problem with this is that when the driver is killed and the channel
mmeory is freed that pointer becomes invalid.
The necessity of that channel is to get access to the gk20a struct that
owns the channel. This can instead be accomplished by making a new
private data struct that has a pointer to the gk20a struct directly
instead of requiring the channel to be valid. This lets the release()
function work even if the channels are gone (though in such cases the
release function doesn't do very much).
Change-Id: I5e50bb5b6dd08d38974f8e7b46ba125e9a3f1922
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1246586
(cherry picked from commit 14b7c380c74d2caeb04c47ad3e33332a423a84bb)
Reviewed-on: http://git-master/r/1261913
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add reference counting for gk20a_busy() and gk20a_idle() so that
the driver can keep track of whether the driver is active.
Bug 1816516
Bug 1807277
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250019
(cherry picked from commit 7f558019735bb34cf00dd1ec17df1797501cff60)
Change-Id: I64c2ff1719673912ae127707e58ee557966c4d4d
Reviewed-on: http://git-master/r/1261922
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add HAL interface for TSG open, which is intended to
be called from the exisiting gk20a_tsg_open function.
The tsg_open entryoint is only implemented for vgpu,
as the server needs to clear metadata when a tsg is opened.
Bug 200215060
Change-Id: Icc8fd602f31e52d9fa9b2e7786b665b9e7b9294e
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1249218
(cherry picked from commit 35c86f7c796c6574d3dc336e20012ea5c16d7cb4)
Reviewed-on: http://git-master/r/1256468
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Update vsms_mapping ioctl to copy from the internal sm_to_cluster array to
new nvgpu_gpu_vsms_mapping_entry array before copying the latter back to user.
Bug 200260086
Change-Id: I0fccc6fb6e0d6b6f737b3a44818d2b47438cd3c8
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1266174
(cherry picked from commit e28882c05491cb8f9573ff71c2d7309e5714e385)
Reviewed-on: http://git-master/r/1269623
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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JIRA DNVGPU-129
1)Add function hook for PMU VFE event handler which will do for VF
curve re-evaluation
2)Add function hook to send temperature limit of GPU sensor
3)Call VFE event handler from PMU's event handle function
Change-Id: I2e3577d3d895e97e6ad06e92f0f4827f9855d0b6
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1245393
(cherry picked from commit 1a5c6c32cdec73fb23735430f43577eda675e5af)
Reviewed-on: http://git-master/r/1268060
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add event definitions for:
- Clock alarm (target frequency not met)
- Thermal alarm (temperature above threshold)
- Power alarm (power above threshold)
- GPU shut down
Jira DNVGPU-186
Change-Id: I52edd44352ed0cba83033949272f41cc9e1c630f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1249342
(cherry picked from commit 67a6681aade241ff24982771778f7e2193d1cd7f)
Reviewed-on: http://git-master/r/1267157
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Jira DNVGPU-166
Change-Id: Id0561d49c64096ad5cbcd23bd371b49b2e0db57c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1245557
(cherry picked from commit 2e0269c76fdda5c8e1a30ca7ef73a08ebe644f88)
Reviewed-on: http://git-master/r/1267156
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In gk20a_scale_target(), to check for duplicate
freq requests we compare current frequency with
devfreq->previous_freq
But for very first request after boot, we have
devfreq->previous_freq set to MIN freq
And in case we evaluate new frew as MIN freq
then we skip calling postscale() and scaling
of EMC clock
This results in keeping EMC at MAX value
To fix this, add new variable last_freq in
gk20a structure.
Use this variable to store frequency value
and to compare for duplicate requests
Bug 200255163
Bug 200257544
Change-Id: Icfc57234c63f68cce8ccf8221237105272dad853
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1263747
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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JIRA DNVGPU-164
Adding export functions to gk20a and gk20a_clk structure
Change-Id: Ia448f17a6c456139544c1d36a3e17ceec0edd2f6
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1239465
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1268000
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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JIRA DNVGPU-71
Change-Id: I08668e17a258fe7c025c79ee2e00a0f4d7cb8a2d
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1243834
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1267999
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Add ioctls to retrieve voltage, current, power and temperature.
Add flags in GPU characteristics to indicate if feature is supported.
Jira DNVGPU-166
Change-Id: Idd5a767326c9d43630e8289ca7d2c27bb96a9f14
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1241862
Tested-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1267153
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JIRA DNVGPU-143
(1) Added conversion routines in ctrl_gk20a.c to
do conversions between Hz and MHZ
(2) Use new api to prevent corruption of requests
is multiple threads on same session commit
simultaneously
Change-Id: I87875e593d2cc90647d5c4f60a4e293ed3ea6b83
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1239460
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1267152
Reviewed-by: Automatic_Commit_Validation_User
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Add NVGPU_GPU_FLAGS_SUPPORT_CLOCK_CONTROLS bit to allow user library
to determine if GPU supports clock control ioctls.
Jira DNVGPU-125
Change-Id: Ia09808ed36aa85a7c520039bb336888e2b467076
Signed-off-by: David Martine Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1239379
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1267154
Reviewed-by: Automatic_Commit_Validation_User
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