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path: root/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
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* gpu: nvgpu: gm20b: Regenerate clock gating listsTerje Bergstrom2015-03-18
| | | | | | | | | | Regenerate clock gating lists. Add new blocks, and takes them into use. Also moves some clock gating settings to be applied at the earliest possible moment right after reset. Change-Id: I21888186c200f7a477c63bd3332e8ed578f63741 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/457698
* gpmu:nvgpu: Falcon debug prints.Vaikundanathan S2015-03-18
| | | | | | | | | | | | | | | Display the Falcon Trace prints in the right format. Embedd the parameters in the string instead of printing it separately. Bug NA Change-Id: Ia61fc43384cf6e44a867c7aa9cbb828127146099 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: http://git-master/r/488757 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: 3d.emc bandwidth ratio policySamuel Russell2015-03-18
| | | | | | | | | | | | | Modify the 3d.emc policy to use a formula based on bandwidth and utilization instead of the current sku-dependent policy. Bug 1364894 Change-Id: Id97f765a48f0aa9f5ebeb0c82bccb22db474a1ae Signed-off-by: Samuel Russell <samuelr@nvidia.com> Reviewed-on: http://git-master/r/453586 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove redundant lockDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | "isr_enable_lock" was used to protect pmu's isr_enabled flag and pmu enable/disable calls Instead of this extra lock, we can reuse "isr_mutex" for this purpose Bug 200014542 Bug 200014887 Change-Id: Ifbb7d6108effc132266a20517820e470d52a7110 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/453348 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add sw shadow for load valueArto Merilainen2015-03-18
| | | | | | | | | | | | | | | | Reading the load value may increase CPU power consumption temprorarily. In most cases we are ok with a value that was read a moment earlier. This patch introduces a software shadow for gpu load. The shadow is updated before starting scaling and all scaling code paths use the sw shadow. Change-Id: I53d2ccb8e7f83147f411a14d3104d890dd9af9a3 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/453347 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu:Added PROD settings for ELPG sequencingMahantesh Kumbar2015-03-18
| | | | | | | | | Added PROD settings for ELPG sequencing registers Bug 200023161 Change-Id: Id313f9bc800d3a57f45aff0f0f609887565971be Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
* gpu: nvgpu: return error from mutex_acquire()Deepak Nibade2015-03-18
| | | | | | | | | | return error from pmu_mutex_acquire() and release() if pmu->initialized is not set Bug 1533644 Change-Id: I341a5831bc5beeccb4587668f61c954ce7576226 Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
* nvgpu: new gpmu ucode compatibilitySupriya2015-03-18
| | | | | | | | | | | | | | For LS PMU new ucode needs to be used. Ucode has interface header file changes too. This patch also has fixes for pmu dmem copy failure Bug 1509680 Change-Id: I8c7018f889a82104dea590751e650e53e5524a54 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/441734 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "gpu: nvgpu: return error from mutex_acquire() if pmu not initialized"Deepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | This reverts commit 50497d4031103df1067f14ce4c1e14b15713efb9. Simply returning error from mutex_acquire() causes the code to call disable_elpg() which decreases elpg refcount But we already have a race condition between pmu initialization where we initialize elpg and runlist update where we call this mutex_acquire and decrease the refcount As a result of this race and returned error we might mess up with the elpg refcount and cause abnormal behaviour Hence revert this change for now until we have clean fix considering this race as well Bug 200024116 Change-Id: Ie64ca36f70aba6b15c2acc235a5d36d13c9025aa Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/441793 Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: return error from mutex_acquire() if pmu not initializedDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In pmu_mutex_acquire(), we return zero (success) if pmu->initialized is not set Since mutex_acquire() was successful, we then call pmu_mutex_release() If now pmu->initialized is set in some other thread then we proceed to validate the mutex owner and end up causing below warning : pmu_mutex_release: requester 0x00000000 NOT match owner 0x00000008 Hence to fix this return error from mutex_acquire() and mutex_release() if pmu->initialized is not yet set and in that case we proceed to call elpg enable/disable Bug 1533644 Change-Id: Ifbb9e6a8e13f6478a13e3f9d98ced11792cc881f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/439333 GVS: Gerrit_Virtual_Submit Reviewed-by: Naveen Kumar S <nkumars@nvidia.com> Tested-by: Naveen Kumar S <nkumars@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu:nvgpu: Enable Falcon trace printsVijayakumar2015-03-18
| | | | | | | | | | | Dump Falcon trace on PMU Crash and add debugfs node falc_trace. This needs Debug trace to be enabled in GPmu binary. Change-Id: I093ef196202958e46d8d9636a848bd6733b5e4cc Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/432732 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu:nvgpu:sysfs node to update aelpg parameterMahantesh Kumbar2015-03-18
| | | | | | | | | | | | | | | | Added sysfs node to update aelpg parameter. Pass parameter as below sequence, SAMPLING_PERIOD_PG_DEFAULT_US, MINIMUM_IDLE_FILTER_DEFAULT_US, MINIMUM_TARGET_SAVING_DEFAULT_US, POWER_BREAKEVEN_DEFAULT_US, CYCLES_PER_SAMPLE_MAX_DEFAULT Bug 1464737 Change-Id: I46873c463820f30f190c722d7ed038622cb2710f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/422702 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: fix possible PMU isr raceDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Possible race description : - while PMU is booting, it sends messages to kernel which we process in gk20a_pmu_isr() - but when messages are processed it is possible that we are on the way to rail gate the GPU and we have already called pmu_destroy() - this could lead to hangs if while processing messages, GR is already off To fix this, introduce another mutex isr_enable_lock and a flag to turn on/off ISRs - when we enable PMU, get the lock and set the flag - in pmu_destroy(), get the lock and remove the flag - in pmu_isr(), take the lock, check if flag is set or not. If flag is not set return, otherwise proceed with the messages Bug 200014542 Bug 200014887 Change-Id: I0204d8a00e4563859eebc807d4ac7d26161316ea Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/428371 (cherry picked from commit 9a37528314f2a2504e4530719f817a93db9a5bf0) Reviewed-on: http://git-master/r/428352 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Initialize PMU ucode only onceTerje Bergstrom2015-03-18
| | | | | | | | | | | Initialize PMU ucode only once, and skip on next GPU boot. Bug 1528275 Change-Id: Ifb95edb380518fae48fdc3b90b00b450fe30c439 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/428897 Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
* gpu: nvgpu: Boot FECS to secure modeTerje Bergstrom2015-03-18
| | | | | | | | | | Boot FECS to secure mode if ACR is enabled. Bug 200006956 Change-Id: Ifc107704a6456af837b7f6c513c04d152b2f4d3a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424251
* gu: nvgpu: Add PMU state ELPG bootingTerje Bergstrom2015-03-18
| | | | | | | | | | | Add PMU state ELPG booting. Prevent ISR processing when PMU is in OFF state. Bug 200006956 Change-Id: Ibcf69a2d81965cc87f520bf864c4425681f04531 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424769
* gpu: nvgpu: Separate PMU firmware load from initTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Separate the code to load PMU firmware from the software init. This allows folding ACR and non-ACR PMU software initialization sequences. Bug 200006956 Change-Id: I74b289747852167e8ebf1be63036c790ae634da4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424768 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Remove extra g field in pmu_gk20aTerje Bergstrom2015-03-18
| | | | | | | | | | | pmu_gk20a has a pointer to struct gk20a *. As pmu_gk20a is part of gk20a, there's no need to have the circular dependency. Bug 200006956 Change-Id: I6d5d10a93b2fba4a26a1e28b3c5206506dc6cc04 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424767
* nvgpu: Host side changes to support HS modeSupriya2015-03-18
| | | | | | | | | | | | | | | | | | | GM20B changes in PMU boot sequence to support booting in HS mode and LS mode Bug 1509680 Change-Id: I2832eda0efe17dd5e3a8f11dd06e7d4da267be70 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/423140 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Rewrite PMU boot-up sequenceTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Rewrite PMU boot sequence as a state machine. At PMU power-up send initial messages, and reset state machine. At each reply from PMU, do the next stage of PMU boot and set state. As now PMU and FECS boot are independent, we need to ensure engine idle before saving ZBC. Change-Id: I1ea747ab794ef08f1784eeabfdae7655d585ff21 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/410205
* gpu: nvgpu: update gpmu supported versionsSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Updated gmpu ucode versions supported for gm20b. Bug 1514021 Change-Id: If9cbde60449f5cc2b9c39c36ab5c79985d320bf8 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/418479 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Initialize FECS explicitly on recoveryTerje Bergstrom2015-03-18
| | | | | | | | | Instead of calling second phase of PMU boot sequence, initialize FECS directly. Change-Id: I7f9de0c5ec42049033839d244979f3f3daabf317 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/410204
* gpu: nvgpu: Remove deferred ELPG enableTerje Bergstrom2015-03-18
| | | | | | | | | | | Prevent the disable ELPG routine from calling deferred re enablement of ELPG. Remove code related to deferred ELPG enable.. Change-Id: I9401e6e0f26a4e332e50eb38439e2ef6fcb4225d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/410203 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: Add PMU sent/recvd messages to dbg logTerje Bergstrom2015-03-18
| | | | | | | | | Add debug log entries for received and sent PMU messages. Change-Id: I94cecca76257d74785c13f1c5f97a7233361019f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/410202 Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: Always initialize system vmTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | PMU, FECS and GPCCS use the same address space. We used to initialize the address space only if PMU is enabled. Create the system address space always. FECS and GPCCS used to have slower bit bang and faster DMA method for loading ucode. Slower method is needed when FECS and GPCCS do not have an address space. Remove the slower method as not anymore needed. Change-Id: I155619741ecc36aa6bf13a9c1ccb03c7c1330f0a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/406771
* gpu: nvgpu: Do not realloc perfmon sample bufferTerje Bergstrom2015-03-18
| | | | | | | | | | | | Allocate perfmon sample buffer only once. Bug 1512840 Change-Id: I3f2a62b0fa28e6ba984ae3068a1d56ba461a0c29 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/408180 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Thomas Cherry <tcherry@nvidia.com>
* gpu: nvgpu: Do not clear PMU state on rail gateTerje Bergstrom2015-03-18
| | | | | | | | | When rail gating, we cleared all PMU status. Clear only the relevant fields. Change-Id: I5b4e8d74339aae6f1c6b945f45b8378bb563e8be Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/406843
* gpu: nvgpu: gk20a: Update perfmon initPrashant Malani2015-03-18
| | | | | | | | | | | | | | | | | Make the perfmon sampling configurable, by adding an 'enabled' flag. This is set according to the CONFIG initially. Modify the perfmon event handler to not touch clock rates. Add a counter to count the number of perfmon events. Also add debugfs entries for the above. Bug 1410515 Change-Id: Ic8197eef0e46e35af1179a5b06140393541cfd43 Signed-off-by: Prashant Malani <pmalani@nvidia.com> Reviewed-on: http://git-master/r/351564 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix return value in pmu mutex releaseArto Merilainen2015-03-18
| | | | | | | | | | | | Bug 1495617 Change-Id: I689ed4303bb3959bb24bf79d52891de28431fc67 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/394904 (cherry-picked from commit a04c51430b186d23953960965ce3ab229968d1f7) Reviewed-on: http://git-master/r/399565 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gk20a: minor fixesKen Adams2015-03-18
| | | | | | | | | fixes one use of unitialized var renames a register to make it match dev_* file. Change-Id: Iafba659bbf2df509e0b494b2c5dab3819bf650ef Signed-off-by: Ken Adams <kadams@nvidia.com> Reviewed-on: http://git-master/r/394792
* gpu: nvgpu: Do not dump top_fs_statusTerje Bergstrom2015-03-18
| | | | | | | | | Result of top_fs_status_r() is always constant. Do not dump it anymore. Change-Id: Ie1cfe872d70b2c3c8a7cef4df3870dacae8f8793 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/395208
* gpu: nvgpu: Remove redundant locked variableArto Merilainen2015-03-18
| | | | | | | | | | | | | | | | Queue locked variable holds entirely redundant information about the queue status and having the variable causes a race between lock() and unlock() functions. This patch removes the locked variable. Bug 1495617 Change-Id: I05682bfe7a23acc77c2bfe405938ace7d2b3d081 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/393431 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Prashant Malani <pmalani@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* video: tegra: host: gk20a: reorder init save zbcPrashant Malani2015-03-18
| | | | | | | | | | | | | | | During the ELPG initialization routine, ELPG should be explicitly disabled before we save the zbc table. This ensures that even if there is a preemption from some other thread that calls ELPG enable/disable, the ref counting will ensure that ELPG remains disabled. Bug 1490085 Change-Id: Ie8eeaf48dda4e7f810aa26926facf63753e86abe Signed-off-by: Prashant Malani <pmalani@nvidia.com> Reviewed-on: http://git-master/r/382273 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: Add NVIDIA GPU DriverArto Merilainen2015-03-18
This patch moves the NVIDIA GPU driver to a new location. Bug 1482562 Change-Id: I24293810b9d0f1504fd9be00135e21dad656ccb6 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/383722 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 17:27:51 -0400