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* gpu: nvgpu: tegra: fix sparse errorsSeshendra Gadagottu2016-03-14
| | | | | | | | | | | | | | | | | Fixed following sparse errors: - therm_gm20b.c:68:6: warning: symbol 'gm20b_init_therm_ops' was not declared. Should it be static? - platform_gk20a_tegra.c:825:5: warning: symbol 'gk20a_set_clk_rate' was not declared. Should it be static? Bug 200067946 Change-Id: I485d5e76302fb294865854f314db2d27f71520f7 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1026685 GVS: Gerrit_Virtual_Submit Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: disable secure allocations on linsimDeepak Nibade2016-01-05
| | | | | | | | | | | | | | | | | | | Disable all secure allocations on linsim by returning an error from gk20a_tegra_secure_page_alloc() With this failure, no more secure allocations will be done from nvgpu Bug 200163671 Change-Id: I26604e45a684dde29c092dc34cc89259f5de5d91 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/928280 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
* gpu: nvgpu: scaling driver updateSeshendra Gadagottu2015-11-19
| | | | | | | | | | | | | | | | Update scaling driver to support to differnt clock frameworks. Bug 200147662 Reviewed-on: http://git-master/r/816929 (cherry picked from commit cbd4cb575fb2d27870089797ff2a8f22540b87e8) Change-Id: Ie50304b4a593d74bd43b271005cc9616fdb52a6e Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/834748 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use platform data for ptimer source rateSeshendra Gadagottu2015-11-04
| | | | | | | | | | | | | | | | Instead of depending on clock frame-work, use platform data for ptimer source rate. Removed ptimerscaling10x platform data, and use ptimer source frequency to calculate ptimerscaling factor. Reviewed-on: http://git-master/r/819030 (cherry picked from commit dd291334d54dab80cab7eb1656dffc48a59610b4) Change-Id: I7638ce9875a6e440bbfc2ba2da0d0b094b2700ff Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/827300 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: make wdt timeout per-platformDeepak Nibade2015-10-07
| | | | | | | | | | | | | | | | Channel watchdog timeout is set to a costant value of 5s as of now Make this timeout platform specific and set it to 5s for gm20b and 7s for gk20a Bug 200133289 Change-Id: I6e7f0fed93a8d5b197ae46807131311196c6636f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/810956 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: scale ptimer based timeoutsVijayakumar2015-10-06
| | | | | | | | | | | | | | | | | bug 1603226 host based timeouts use ptimer for detecting timeouts. on gk20a and gm20b ptimer runs 2.6x slower. scale the fifo_eng_timeout to account for this Change-Id: Ie44718382953e36436ea47d6e89b9a225d5c2070 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/799983 (cherry picked from commit d1d837fd09ff0f035feff1757c67488404c23cc6) Reviewed-on: http://git-master/r/808250 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Inject function address from nvgpuYogesh2015-08-19
| | | | | | | | | | | | | | | This patch inserts the function address of gk20a_debug_dump_device into host data struct once the nvgpu module loads and removes it during unload. Bug 1476801 Change-Id: If49262208325b2aa0807705c26086e6d7c81632c Signed-off-by: Yogesh Bhosale <ybhosale@nvidia.com> Reviewed-on: http://git-master/r/779397 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Implement own rail gating codeTerje Bergstrom2015-07-07
| | | | | | | | | | | Move rail gating sequence to happen in nvgpu driver instead of piggybacking on Tegra power gating APIs. Bug 200115454 Change-Id: I8514686c7b137f200021b05ead7157d0883bddc5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/761991
* gpu: nvgpu: Delete T132 specific configurationTerje Bergstrom2015-06-29
| | | | | | Change-Id: I1cd97a8ea0911a657fc4d5b7a3aee534474aea47 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/762558
* gpu: nvgpu: tegra gpu to emc frequency mappingAnders Kugler2015-05-18
| | | | | | | | | | | | | | | o emc clock scaling (bug fix): Take the gpu load into account for gpu frequencies less than or equal to fmax @ Vmin. Bug 1591643 Change-Id: I0298adfdd4b7111557907c3bd6022fd6005355f0 Signed-off-by: Anders Kugler <akugler@nvidia.com> Reviewed-on: http://git-master/r/735846 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Export VPR allocatorTerje Bergstrom2015-05-05
| | | | | | | | | | | | | | Export functions for VPR allocation. Bug 1625090 Change-Id: Ief54613402965da3f41d8dd4a463c75729a3941a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/737847 Reviewed-on: http://git-master/r/738574 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* platform: tegra: mc: Centralize header filesAlex Waterman2015-05-05
| | | | | | | | | | | | | | | Place all header files under linux/platform/tegra/. Also update all source files that include the moved headers to correctly reflect their new location. Change-Id: Iff5738d3ad75e93519d1a4b573b80d03e6a9b053 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/728636 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/733651 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
* gpu: nvgpu: Use common allocator for contextTerje Bergstrom2015-04-04
| | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by using common helpers, and common data structure for storing results of allocations. Bug 1605769 Change-Id: I10c226e2377aa867a5cf11be61d08a9d67206b1d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/720507
* gpu: nvgpu: tegra gpu to emc frequency mappingAnders Kugler2015-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | o emc clock scaling Only take the gpu load into account for gpu frequencies below fmax @ Vmin. The granularity of frequency steps is much larger in the gpu frequency range below fmax @ Vmin than in the upper frequency range. Above fmax @ Vmin, keep the gpu unblocked and disregard the gpu load when evaluating the emc target. o tegra_postscale() Round the new emc target to nearest discrete frequency. Set the emc frequency only if the new emc target is different from the previously requested emc frequency to avoid the penalty of the locks inside clk_set_rate(). Bug 1591643 Change-Id: I1a1a8734a74569c4d57b6e2bda4c11b2bda3f5f3 Signed-off-by: Anders Kugler <akugler@nvidia.com> Reviewed-on: http://git-master/r/680937 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ilan Aelion <iaelion@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add DT support for gpu power-domainSumit Singh2015-04-04
| | | | | | | | | | | | | First, defining a new structure to support gk20a power domain. Then making necessary modifications to add so as to add DT support for gpu power-domain. bug 200070810 Change-Id: I29e1c24b181e14743d3969103abfd1882d171f07 Signed-off-by: Sumit Singh <sumsingh@nvidia.com> Reviewed-on: http://git-master/r/668973 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Fix some GPU boot error pathsTerje Bergstrom2015-04-04
| | | | | | | | Fix panics in error path when FECS cannot be booted. Change-Id: I354e37579386e27f46b80cd4172fe12897a3b92f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/712698
* gpu: nvgpu: add flag for CAR reset in do_idle()Deepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "force_reset" flag to __gk20a_do_idle() For real world use cases like VPR resizing, we cannot wait for railgate_delay (which is 500 mS). Hence use CAR reset for this use case. (this is done via gk20a_do_idle() API with force_reset = true) Some of the test cases make use of sysfs "force_idle" and they expect GPU to be into really railgated state and not in CAR reset. Hence when called from sysfs, set force_reset = false. When global flag "force_reset_in_do_idle" is set, it will override local flags and force CAR reset case. This is desired in cases where railgating is not enabled Also, set force_reset_in_do_idle = false for GM20B since railgating has been enabled for GM20B Bug 1592997 Change-Id: I6c5af2977c7211ef82551a86a7c1eb51b8ccee60 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/711615 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: bypass smmu for VPR memory accessKrishna Reddy2015-04-04
| | | | | | | | | | | | | | SMMU translation should be bypassed for VPR accesses via GPU. clear sgt dma address to bypass smmu for VPR. Bug 1215470 Change-Id: I22df41a9afc447e2502055b7907cc1848a770f26 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/696509 (cherry picked from commit a699f55941fa22e90d41a53798956a542b212659) Reviewed-on: http://git-master/r/707889
* Revert "gpu: nvgpu: Enable syncpt reclaim only on gm20b"Timo Alho2015-03-18
| | | | | | | | | | This reverts commit 8eefb93c21934b101d7f423c38d9ea384a45fad6. Bug 1585422 Change-Id: I217e0ffe6c230ee3c63d9aec1c48ce9c41770468 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/659426
* gpu: nvgpu: Enable syncpt reclaim only on gm20bTerje Bergstrom2015-03-18
| | | | | | | | | | | | | gm20b has more channels than sync points. We use aggressive reclaim of sync points to offset that. Disable aggressive reclaim for gk20a because it is not needed there. Bug 1583849 Change-Id: I2a74b0504150a54cb8a97016effe20c5d905ac95 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/657095 Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: remove platform device on exitKonsta Holtta2015-03-18
| | | | | | | | | | | | | Add ->remove() for undoing the ->probe() and ->late_probe() in gk20a_platform devices, and call it when gk20a is removed. Bug 1476801 Change-Id: Ic9b29c0a7ea4a4cae7b5a0f66774bd799eb28434 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/594443 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gm20b: set rail gating delay to 500msecSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | | Enable gpu rail gating by setting rail-gating delay to 500msec instead of INT_MAX. Bug 1552464 Bug 200040882 Change-Id: I64e779fc5b3a0c04997d8874025c71812948602a Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/552700 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: force CAR reset in do_idle() for gm20bDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | In gk20a_do_idle(), we wait for platform->railgate_delay to allow GPU to go into rail gate But sometimes we set platform->railgate_delay = INT_MAX to disable GPU rail gating but allow it to suspend during low power state Due to this, force_idle API fails (it waits for INT_MAX) To fix this, allow forcing CAR reset instead of rail gating with flag "force_reset_in_do_idle" defined in gk20a_platform Set this flag for gm20b until we fix the railgate_delay Bug 1517584 Change-Id: I031aa56f87d4db3727e2c3a3e5eeaf18503dd449 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/593704 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix sparse warningsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | Fix below sparse warnings : warning: Using plain integer as NULL pointer warning: symbol <variable/funcion> was not declared. Should it be static? warning: Initializer entry defined twice Also, remove dead functions Bug 1573254 Change-Id: I29d71ecc01c841233cf6b26c9088ca8874773469 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/593363 Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: fix reset clock in gm20bDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | To assert reset on GPU, we store "gpu_ref" clock in platform->clk[0] and use it to assert/deassert reset But for gm20b, "gpu_ref" is no longer resettable. To fix this, add two callbacks in gk20a_platform : .reset_assert and .reset_deassert Also, add a pointer "clk_reset" to store the clock which needs to be reset For gk20a specific implementation, we continue to reset platform->clk[0] For gm20b specific implementation, we first request "gpu_gate" clock, store it and use it to assert reset Bug 1513685 Bug 1517584 Change-Id: I15a583a4a07eb663b442084be8b8c7d0c7c7a142 Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: Use generic clk_get_rateTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Instead of gk20a_clk_get_rate() use the generic clk_get_rate(). Bug 1567274 Change-Id: If955790408d2f4a5d917ea3993573ac3f254c7d3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/592094 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: T18x supportKenneth Adams2015-03-18
| | | | | | | | | | nvgpu framework and build for T18x Bug 1567274 Change-Id: I77835302a1110573008869d1106eface512bb9b1 Signed-off-by: Ken Adams <kadams@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: cde: move GK20A_CDE to platform dataKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | | | CONFIG_GK20A_CDE has not even been used for enabling CDE, just for initializing it at boot time, and it was disabled; initialization has been done late when the engine is first used. Remove the config setting and add information about CDE support in gk20a platform data, forcing the initialization at boot time. Boot time init removes rare race conditions when CDE would be initialized by first user. Bug 200046882 Change-Id: I85d5fb73dc27acbbe203138d25f6e342de030d93 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/562855 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement 64k large page supportTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | Implement support for 64kB large page size. Add an API to create an address space via IOCTL so that we can accept flags, and assign one flag for enabling 64kB large page size. Also adds APIs to set per-context large page size. This is possible only on Maxwell, so return error if caller tries to set large page size on Kepler. Default large page size is still 128kB. Change-Id: I20b51c8f6d4a984acae8411ace3de9000c78e82f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove unused symbolsTerje Bergstrom2015-03-18
| | | | | | | | | Remove unused symbols in platform file and gk20a.c. Bug 1558739 Change-Id: If160a75061ecb4ad9cbc4abfb9bc409457299738 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: fix issue with rail gating ref countSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | | gpu rail gating reference count is going wrong because "can_railgate" is set to false during probe(). For rail-gating to work no gpu re-work is needed and by default rail-gating is enabled with INT_MAX delay. Bug 200044987 Change-Id: I9367275cd18c34cb19a51193353585789ba44c03 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/556568 Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: Fix gpu identification for 3demcSamuel Russell2015-03-18
| | | | | | | | | | | | | | Modify GPU detection in 3demc-bw-ratio to use the SOC Id. Bug 1364894 Change-Id: If52e8c5153e76b29d67d28c52303b095df2e8bf0 Signed-off-by: Samuel Russell <samuelr@nvidia.com> Reviewed-on: http://git-master/r/542770 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: enable aelpgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Adaptive Engine Level Power Gating power feature for gm20b. Bug 1552466 Change-Id: I2659f80a567699eff64307800710d4978d02adc1 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/501343 Reviewed-by: Mitch Luban <mluban@nvidia.com> Tested-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: create new nvgpu ioctl headerKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | Move nvgpu ioctls from the many user space interface headers to a new single nvgpu.h header under include/uapi. No new code or replaced names are introduced; this change only moves the definitions and changes include directives accordingly. Bug 1434573 Change-Id: I4d02415148e437a4e3edad221e08785fac377e91 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542651 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: rename gpu ioctls and structs to nvgpuKonsta Holtta2015-03-18
| | | | | | | | | | | | | | To help remove the nvhost dependency from nvgpu, rename ioctl defines and structures used by nvgpu such that nvhost is replaced by nvgpu. Duplicate some structures as needed. Update header guards and such accordingly. Change-Id: Ifc3a867713072bae70256502735583ab38381877 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542620 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Require rework for DVFS and rgArto Merilainen2015-03-18
| | | | | | | | | | | | | | | | | | Boards require a rework to make railgating and DVFS work realiably. The information whether the board has been reworked or not will be available on DTS. This patch adds a DTS check to the GPU driver initialisation. If the rework information is not available (or the rework has been marked as disabled), railgating and DVFS are disabled. Bug 1555485 Change-Id: Ie86fe35fb94377403472faffcbcaec645b6e40d9 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/500218 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: enable elpgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Engine Level Power Gating power feature for gm20b. Bug 1552466 Change-Id: Ief9cf648270412f7a9f6f5b28a1fce08effdd670 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/499541 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: enable slcgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Second Level Clock Gating power feature for gm20b. Bug 1552466 Change-Id: I34a3d93a98f7b784ab26fb7940d50db262b35f57 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/499540 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: enable elcgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Engine Level Clock Gating power feature for gm20b. Bug 1552466 Change-Id: I6f0bc565700bfd183c703fc35389188906842a4e Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/499539 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: enable blcgSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | Enable Block Level Clock Gating power feature for gm20b. Bug 1552466 Change-Id: Ibdd611bc2932ae9c3ce2c0d9eb847fa46a3759c7 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/499538 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* edp: sysedp : CPU/GPU priority depends on fGPUMatt Longnecker2015-03-18
| | | | | | | | | | | | | | | | Provide sysedp_dynamic_capping with the instantaneous GPU frequency when notifying it of the GPU load. Modify the gpu/cpu priority decision logic to choose CPU priority until GPU frequency gets "near" the CPU-priority-limited-GPU-fmax. Introduce the priority_bias debugfs parameter to facilitate tuning of "near". priority_bias takes a value from 0 to 100. Change-Id: Ia2cba36b8ea024fb8b01b5ba195dcf6550e38121 Signed-off-by: Matt Longnecker <mlongnecker@nvidia.com> Reviewed-on: http://git-master/r/481720 GVS: Gerrit_Virtual_Submit Reviewed-on: http://git-master/r/498912 Reviewed-by: Timo Alho <talho@nvidia.com>
* gpu: nvgpu: gm20b: Enable rail-gating with max delaySeshendra Gadagottu2015-03-18
| | | | | | | | | | | Enable gpu rail gating with INT_MAX delay. This will allow teams to experiment with different rail-gate entry delay. Change-Id: I8c696140aba2374c797365282999b6589432047c Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/491615 GVS: Gerrit_Virtual_Submit Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: Do not rail gate in simulationTerje Bergstrom2015-03-18
| | | | | | | | | | | Simulation does not model rails, so do not try to control them. Change-Id: I52ec12e7865e18764274dd9ce7a2fbd196b6b9d1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/482181 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Thomas Cherry <tcherry@nvidia.com>
* gpu: nvgpu: gm20b: add pm callbacksSeshendra Gadagottu2015-03-18
| | | | | | | | | | | Add powergate/powerungate callbacks for gm20b configuration. Change-Id: Ieb681b74de7ea19d172922ef68260be81b675a56 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/457352 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: 3d.emc bandwidth ratio policySamuel Russell2015-03-18
| | | | | | | | | | | | | Modify the 3d.emc policy to use a formula based on bandwidth and utilization instead of the current sku-dependent policy. Bug 1364894 Change-Id: Id97f765a48f0aa9f5ebeb0c82bccb22db474a1ae Signed-off-by: Samuel Russell <samuelr@nvidia.com> Reviewed-on: http://git-master/r/453586 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: poweron host1x explicitlyDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | Currently gk20a gets reference of host1x via phandle in Device Tree. But runtime PM does not seem to be handling power dependencies too well in this case and hence some times host1x is off when we need it. To fix this, exlicitly power on host1x while powering gpu up. Do this via "busy" and "idle" callbacks from gk20a_platform Bug 1534272 Bug 200022536 Change-Id: Ia562ee19722cfc8edc5626a5a058ab8edfe3d206 Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: do not abort probe if secure page alloc failsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | Do not abort GPU probe if secure page alloc fails. We can just note that this allocation failed (using bool secure_alloc_ready) and prevent further secure memory allocation if this flag is not set. Bug 1525465 Change-Id: Ie4eb6393951690174013d2de3db507876d7b657f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/427730 GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: make pm config as platform dataSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | | | | Make gpu power management feature configurations as platform data. Keep existing sttaus for gk20a and disable all power features for gm20b. Bug 1523728 Change-Id: Ife7786863f18e21b882ac77085c7abc7c84d4cfc Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/426369 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add APIs to allocate/free dummy secure bufferDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | Add APIs to allocate and free dummy secure buffer of size PAGE_SIZE. Also, fix small errors during secure memory alloc/free. Bug 1487804 Change-Id: If078116fb973e81bfcee054b900c09a313e389c6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/421700 (cherry picked from commit 5391515dab27cc88b921cf81913085dea98197e0) Reviewed-on: http://git-master/r/419609 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add is_railgated() callbackDeepak Nibade2015-03-18
| | | | | | | | | | | Add is_railgated() platform callback to check status of gk20a power rail Bug 1376916 Bug 1487804 Change-Id: Ia0d909210dc409ab684eb6f20528b81500aecd5c Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 23:56:57 -0400