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* gpu: nvgpu: fix list_add_tail in dmabuf stateKonsta Holtta2015-04-04
| | | | | | | | | | | | | | | | | Fix a memory leak: add the newly created state to the dmabuf priv's state list, instead of the other way around. Bug 1594784 Bug 200064154 Change-Id: I939746a254bb8bf4d06de7fcecba06c191da665f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/668758 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: Fix/HACK for v3.18Dan Willemsen2015-03-18
| | | | Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
* gpu: nvgpu: Remove gk20a sparse texture & PTE freeingTerje Bergstrom2015-03-18
| | | | | | | | | | | | Remove support for gk20a sparse textures. We're using implementation from user space, so gk20a code is never invoked. Also removes ref_cnt for PTEs, so we never free PTEs when unmapping pages, but only at VM delete time. Change-Id: I04d7d43d9bff23ee46fd0570ad189faece35dd14 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/663294
* gpu: nvgpu: Generic mem_desc & allocationTerje Bergstrom2015-03-18
| | | | | | | | | | | | Make mem_desc a generic container for buffers. Add functions for allocating and mapping buffers to an address space which store their data in mem_desc. Change-Id: I031643442c6fd41f5e7222fe9b7bfcaf9b784db5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/660908 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: detect iommu'ability dynamicallyHiroshi Doyu2015-03-18
| | | | | | | | | | | | A device can be iommu'able whenever it's registered so that this patch detects its iommu'ability dynamically. Bug 1577389 Change-Id: I8ea20e5dd997fc1a399f517c17783323f238ecc3 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/606019 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Physical page bits to be per chipTerje Bergstrom2015-03-18
| | | | | | | | | | Retrieve number of physical page bits based on chip. Bug 1567274 Change-Id: I5a0f6a66be37f2cf720d66b5bdb2b704cd992234 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601700
* gpu: nvgpu: l2 invalidate/flush for off devicesKonsta Holtta2015-03-18
| | | | | | | | | | | | | When doing l2 invalidate or l2 flush, first check if the hw is powered on. If it is not, nothing is done, as there are no hardware registers available. As a side-effect, this may race so that the hardware stays unrailgated. Change-Id: I8bdbfcee3545355435d4ae01476188eb1b8b8817 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/594441 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Per-alloc alignmentTerje Bergstrom2015-03-18
| | | | | | | Change-Id: I8b7e86afb68adf6dd33b05995d0978f42d57e7b7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/554185 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: sanitize gk20a_vm_alloc_share()Sami Kiminki2015-03-18
| | | | | | | | | | | | | | Add sanity check for big_page_size parameter to avoid invoking gk20a_init_vm() with a bogus big page size, potentially hitting a BUG_ON there. Also, reorganize the code a bit to avoid memory leak in case of bogus big page size, and properly forward the return value from gk20a_init_vm(). Change-Id: I4eeada75415d2e9539b5e8859099cce35cd86db3 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/594469 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ALLOC_AS: don't fail on default big page sizeSami Kiminki2015-03-18
| | | | | | | | | | | | | gk20a_vm_alloc_share() fails when the default big page size is requested but ops.mm.set_big_page_size is unset. Rework the logic a bit to allow userspace to explicitly request the default big page size, too. Change-Id: I2a28c6d979fbf1dde5559ce9eb5f1310d232e27f Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/590456 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix comptag calculation for 64k pagesTerje Bergstrom2015-03-18
| | | | | | | | | Comptags are assigned per 128k. For 64k pages this means we need to assign same index to two pages. Change the logic to use byte sizes. Change-Id: If298d6b10f1c1cad8cd390f686d22db103b02d12 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/594403
* gpu: nvgpu: cde: Combine H and V passesJussi Rasanen2015-03-18
| | | | | | | | | | | | | | | | When using CDE firmware v1, combine H and V swizzling passes into one pushbuffer submission. This removes one GPU context switch, almost halving the time taken for swizzling. Map only the compbit part of the destination surface. Bug 1546619 Change-Id: I95ed4e4c2eefd6d24a58854d31929cdb91ff556b Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/553234 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: free all vm's when removing supportKonsta Holtta2015-03-18
| | | | | | | | | | | | Remove both bar1 and pmu. Bug 1476801 Change-Id: I0c194db06b576083ddaab3726b8575ebce473d84 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/592114 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: don't kfree vm's inside other structsKonsta Holtta2015-03-18
| | | | | | | | | | | | Trying to kfree pmu.vm or bar1.vm is not allowed, since they are not directly allocated. Separate the vm kfree from the actual vm support removal, so that they can be done individually. Change-Id: I7628f546b94e0de909371ce315e4cb065e5ef953 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/592112 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: destroy big page allocator only if setKonsta Holtta2015-03-18
| | | | | | | | | | | | Some vm's do not have big pages. Bug 1476801 Change-Id: Ic82ca7a1380834ea30582631af224c81fd01e4bb Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/592113 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix sparse warningsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | Fix below sparse warnings : warning: Using plain integer as NULL pointer warning: symbol <variable/funcion> was not declared. Should it be static? warning: Initializer entry defined twice Also, remove dead functions Bug 1573254 Change-Id: I29d71ecc01c841233cf6b26c9088ca8874773469 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/593363 Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* Revert "gpu: nvgpu: GR and LTC HAL to use const structs"Sam Payne2015-03-18
| | | | | | | | | | | This reverts commit 41b82e97164138f45fbdaef6ab6939d82ca9419e. Change-Id: Iabd01fcb124e0d22cd9be62151a6552cbb27fc94 Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/592221 Tested-by: Hoang Pham <hopham@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: Allow compression on 64k pagesTerje Bergstrom2015-03-18
| | | | | | | | | | | Allow compression always when page size matches the big page size for the context. Bug 1558739 Change-Id: I27b0aed06c24d69bd1555626b9affb1149536615 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590422
* gpu: nvgpu: GR and LTC HAL to use const structsTerje Bergstrom2015-03-18
| | | | | | | | | | | Convert GR and LTC HALs to use const structs, and initialize them with macros. Bug 1567274 Change-Id: Ia3f24a5eccb27578d9cba69755f636818d11275c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590371
* gpu: nvgpu: VM size should be u64Terje Bergstrom2015-03-18
| | | | | | | | | VM size should not depend on CPU architecture. It should be always u64. Change-Id: I81539807f6674877fd04f0079b2bec05b2a0640d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/562466
* gpu: nvgpu: Implement 64k large page supportTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | Implement support for 64kB large page size. Add an API to create an address space via IOCTL so that we can accept flags, and assign one flag for enabling 64kB large page size. Also adds APIs to set per-context large page size. This is possible only on Maxwell, so return error if caller tries to set large page size on Kepler. Default large page size is still 128kB. Change-Id: I20b51c8f6d4a984acae8411ace3de9000c78e82f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Common VM initializerTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | Merge initialization code from gk20a_init_system_vm(), gk20a_init_bar1_vm() and gk20a_vm_alloc_share() into gk20a_init_vm(). Remove redundant page size data, and move the page size fields to be VM specific. Bug 1558739 Bug 1560370 Change-Id: I4557d9e04d65ccb48fe1f2b116dd1bfa74cae98e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Report error on failed mapSami Kiminki2015-03-18
| | | | | | | | | | | gk20a_vm_map_buffer() used to ignore silently map requests for non-dmabuf fd:s. Fix this by returning the error code from dma_buf_get(). Bug 1566862 Change-Id: If01b03f43b67b17d9fb997d914db871520f50c6e Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
* gpu: nvgpu: require mapped buffer be inside vaKonsta Holtta2015-03-18
| | | | | | | | | | When validating buffers to be mapped, check that the buffer end does not overflow over the virtual address node space. Bug 1562361 Change-Id: I3c78ec7380584ae55f1e6bf576f524abee846ddd Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: create new nvgpu ioctl headerKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | Move nvgpu ioctls from the many user space interface headers to a new single nvgpu.h header under include/uapi. No new code or replaced names are introduced; this change only moves the definitions and changes include directives accordingly. Bug 1434573 Change-Id: I4d02415148e437a4e3edad221e08785fac377e91 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542651 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: rename gpu ioctls and structs to nvgpuKonsta Holtta2015-03-18
| | | | | | | | | | | | | | To help remove the nvhost dependency from nvgpu, rename ioctl defines and structures used by nvgpu such that nvhost is replaced by nvgpu. Duplicate some structures as needed. Update header guards and such accordingly. Change-Id: Ifc3a867713072bae70256502735583ab38381877 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542620 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ioctl support flags in gpu characteristicsKonsta Holtta2015-03-18
| | | | | | | | | | | | | | Expose supported nvgpu ioctls to userspace via bits in the flags field of nvhost_gpu_characteristics; currently define two bits for special memory allocation support. Bug 1539747 Change-Id: I1bc9333b12825d07a00b7a4136ae9d35816a5855 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/495942 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: check dma_buf_get retval with IS_ERRKonsta Holtta2015-03-18
| | | | | | | | | | | | | dma_buf_get returns PTR_ERRs, so fix checking for null to proper IS_ERR in gk20a_vm_map_buffer. Buffer mapping from user space with ioctls would also have paniced here if an improper handle would be passed. Change-Id: I245fe41cd209e49fc9265e56340c1c8215ffb1d2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/498320 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use pgsz_idx instead of page_sizeTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Alloc space writes the page size to a field that requires pgsz_idx. That can cause corruption in internal kernel structures. Clear_sparse treated a parameter as page size instead of index. Bug 1549451 Change-Id: I73ce17b99aae6865056facce72d2ab9ca8b3f81d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/495692
* gpu: nvgpu: gm20b: Regenerate clock gating listsTerje Bergstrom2015-03-18
| | | | | | | | | | Regenerate clock gating lists. Add new blocks, and takes them into use. Also moves some clock gating settings to be applied at the earliest possible moment right after reset. Change-Id: I21888186c200f7a477c63bd3332e8ed578f63741 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/457698
* gpu: nvgpu: support gk20a virtualizationAingara Paramakuru2015-03-18
| | | | | | | | | | | | | The nvgpu driver now supports using the Tegra graphics virtualization interfaces to support gk20a in a virtualized environment. Bug 1509608 Change-Id: I6ede15ee7bf0b0ad8a13e8eb5f557c3516ead676 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/440122 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: manage phys pages at runtimeDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | Current implementation is based on config GK20A_PHYS_PAGE_TABLES to have APIs to create/free/map/unmap phys pages Remove this config based implementaion and move the APIs so that they are called at runtime based on tegra_platform_is_linsim() In generic APIs, we first check if platform is linsim and if it is then we forward the call to phys page specific APIs Change-Id: I23eb6fa6a46b804441f18fc37e2390d938d62515 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/488843 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: use gpc_mmu to check debug modeKevin Huang2015-03-18
| | | | | | | | | | Bug 1534793 Change-Id: I8a4c35914b58dd13a7c10c668de9d4662d947d8c Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/441377 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: clear sparse in space freeKevin Huang2015-03-18
| | | | | | | | | | | | | | Gk20a unmaps the addresses binding to dummy page to clear sparse. On Gm20b, we need to free the allocated page table entry for sparse memory. Bug 1538384 Change-Id: Ie2409ab016c29f42c5f7d97dd7287b093b47f9df Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/448645 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Attach compression state to dma-bufLauri Peltonen2015-03-18
| | | | | | | | | | | Bug 1509620 Change-Id: I694fe43ef5d1f4f329d997a3d60e006785374cc3 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: http://git-master/r/439849 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add helpers for backing store accessArto Merilainen2015-03-18
| | | | | | | | | | | | | | This patch adds mm helpers to access compression backing store from in-kernel shader. Bug 1409151 Change-Id: Icb4f6dc0b5a35fdb97bc4221ab3657866f775fae Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/440263 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Bump unmap retries if not siliconTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | | | In simulation and emulation 50ms is not enough to ensure a job is complete. Bump it to 5s when not running on silicon. Bug 1510751 Change-Id: I90883b70ce2a75a8f07344f713d647b3fa0d0c7d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/432044 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chris Dragan <kdragan@nvidia.com> Tested-by: Chris Dragan <kdragan@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: remove unused vpr refetch functionsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | VPR resize is done by forcing GPU to idle and then updating VPR size from TLK. There is no need now to call vpr_resize funtion from kernel and hence these functions can be removed. Bug 1487804 Change-Id: I758a6e0a99a58757866f1138b0a89594e2a33908 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/421703 (cherry picked from commit 391d9bacf053fe0dacffc76c36768f82912ad1f4) Reviewed-on: http://git-master/r/419612 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove extraneous FB flush callsTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | gk20a_mm_fb_flush() invoked G_ELPG_FLUSH and FB_FLUSH. Remove the invokation of G_ELPG_FLUSH. Replace calls to gk20a_mm_fb_flush() with gk20a_mm_l2_flush() when appropriate. Bug 1421824 Change-Id: I02af4bdc3b7bd26d0f6a8d610f70349269775a36 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/408210 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add generic api for sparse memoryKevin Huang2015-03-18
| | | | | | | Bug 1442531 Change-Id: I97408b54e27f5ed6411792e73f079a6f86cbe5f6 Signed-off-by: Kevin Huang <kevinh@nvidia.com>
* gpu: nvgpu: implement mapping for sparse allocationKirill Artamonov2015-03-18
| | | | | | | | | | | | | | | | Implement support for partial buffer mappings. Whitelist gr_pri_bes_crop_hww_esr accessed by fec during sparse texture initialization. bug 1456562 bug 1369014 bug 1361532 Change-Id: Ib0d1ec6438257ac14b40c8466b37856b67e7e34d Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-on: http://git-master/r/375012 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: When rail gating, flush only onceTerje Bergstrom2015-03-18
| | | | | | | | | | When rail gating invoke G_ELPG_FLUSH only once. Bug 1421824 Change-Id: Ibde0e32b212e3b030e69a9cb837c87789887aabb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/408209
* gpu: nvgpu: Prune redundant cache maintenanceTerje Bergstrom2015-03-18
| | | | | | | | | | | | Remove redundant cache maintenance operations. Instance blocks and graphics context buffers are uncached, so they do not need any cache maintenance. Bug 1421824 Change-Id: Ie0be67bf0be493d9ec9e6f8226f2f9359cba9f54 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/406948
* gpu: nvgpu: Always initialize system vmTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | PMU, FECS and GPCCS use the same address space. We used to initialize the address space only if PMU is enabled. Create the system address space always. FECS and GPCCS used to have slower bit bang and faster DMA method for loading ucode. Slower method is needed when FECS and GPCCS do not have an address space. Remove the slower method as not anymore needed. Change-Id: I155619741ecc36aa6bf13a9c1ccb03c7c1330f0a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/406771
* gpu: nvgpu: halize ltc isrKevin Huang2015-03-18
| | | | | | | | | | Bug 1507804 Change-Id: I3cca0e83dbf911c94422f8bb0b2df675a170b990 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/403213 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fixes to static offset mappingsArto Merilainen2015-03-18
| | | | | | | | | | | | | | This patch addresses two issues in fixes offset mappings: - VA unmapping did not use lists safely. This caused an application hang if the application did not free all (fixed offset) buffers before quiting. - GPU was not powered closing AS node. If the address space had areas that were not freed, the driver tried to access hw without powering it up first. Change-Id: Ida526d222ea4e03b8d765eca16574ddc1823e60d Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/405872 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Handle missing DMA addressSami Kiminki2015-03-18
| | | | | | | | | | | | | If DMA address is not defined, use the physical address. Bug 1500983 Change-Id: Ic33b21f74c8c2760e43146b87eec7ea467fc87be Signed-off-by: Sami Kiminki <skiminki@nvidia.com> (cherry picked from commit 8ae9a6567349241ce1cfff383526b0d9d39c28a1) Reviewed-on: http://git-master/r/415238 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
* gpu: nvgpu: mm: free allocations on validate errorShridhar Rasal2015-03-18
| | | | | | | | | | | | | Free allocated virtual address when marking PTE for validation or update fails. Bug 1479803 Change-Id: I9a8bd7c245b478f4252a261f246002fcc65d750d Signed-off-by: Shridhar Rasal <srasal@nvidia.com> (cherry picked from commit b5c0ad4e00dfc86b65e8efe3d8691b5cfaafbe4c) Reviewed-on: http://git-master/r/415248 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: fix pte memory leakKirill Artamonov2015-03-18
| | | | | | | | | | | | | | | Force cleanup of all GMMU PTEs when releasing vm. bug 1514178 Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Change-Id: Ice1ff837ca4decbdec2d4a78ea5eb64bfeefc0db Reviewed-on: http://git-master/r/411198 (cherry picked from commit e14ee5646554fd6cd812f4e7edf220c40116d722) Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/411895 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
* gpu: nvgpu: Fix TLB invalidate raceTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | TLB invalidate can have a race if several contexts use the same address space. One thread starting an invalidate allows another thread to submit before invalidate is completed. Bug 1502332 Change-Id: I074ec493eac3b153c5f23d796a1dee1d8db24855 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/407578 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-27 06:06:02 -0400