| Commit message (Collapse) | Author | Age |
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gk20a_mm_fb_flush() invoked G_ELPG_FLUSH and FB_FLUSH. Remove the
invokation of G_ELPG_FLUSH. Replace calls to gk20a_mm_fb_flush() with
gk20a_mm_l2_flush() when appropriate.
Bug 1421824
Change-Id: I02af4bdc3b7bd26d0f6a8d610f70349269775a36
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/408210
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Bug 1442531
Change-Id: I97408b54e27f5ed6411792e73f079a6f86cbe5f6
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
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Implement support for partial buffer mappings.
Whitelist gr_pri_bes_crop_hww_esr accessed by
fec during sparse texture initialization.
bug 1456562
bug 1369014
bug 1361532
Change-Id: Ib0d1ec6438257ac14b40c8466b37856b67e7e34d
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/375012
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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When rail gating invoke G_ELPG_FLUSH only once.
Bug 1421824
Change-Id: Ibde0e32b212e3b030e69a9cb837c87789887aabb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/408209
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Remove redundant cache maintenance operations. Instance blocks and
graphics context buffers are uncached, so they do not need any cache
maintenance.
Bug 1421824
Change-Id: Ie0be67bf0be493d9ec9e6f8226f2f9359cba9f54
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/406948
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PMU, FECS and GPCCS use the same address space. We used to initialize
the address space only if PMU is enabled. Create the system address
space always.
FECS and GPCCS used to have slower bit bang and faster DMA method
for loading ucode. Slower method is needed when FECS and GPCCS do not
have an address space. Remove the slower method as not anymore
needed.
Change-Id: I155619741ecc36aa6bf13a9c1ccb03c7c1330f0a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/406771
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Bug 1507804
Change-Id: I3cca0e83dbf911c94422f8bb0b2df675a170b990
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/403213
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This patch addresses two issues in fixes offset mappings:
- VA unmapping did not use lists safely. This caused an application hang
if the application did not free all (fixed offset) buffers before quiting.
- GPU was not powered closing AS node. If the address space had areas that
were not freed, the driver tried to access hw without powering it up first.
Change-Id: Ida526d222ea4e03b8d765eca16574ddc1823e60d
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/405872
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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If DMA address is not defined, use the physical address.
Bug 1500983
Change-Id: Ic33b21f74c8c2760e43146b87eec7ea467fc87be
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
(cherry picked from commit 8ae9a6567349241ce1cfff383526b0d9d39c28a1)
Reviewed-on: http://git-master/r/415238
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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Free allocated virtual address when marking PTE for validation
or update fails.
Bug 1479803
Change-Id: I9a8bd7c245b478f4252a261f246002fcc65d750d
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
(cherry picked from commit b5c0ad4e00dfc86b65e8efe3d8691b5cfaafbe4c)
Reviewed-on: http://git-master/r/415248
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Force cleanup of all GMMU PTEs when releasing vm.
bug 1514178
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: Ice1ff837ca4decbdec2d4a78ea5eb64bfeefc0db
Reviewed-on: http://git-master/r/411198
(cherry picked from commit e14ee5646554fd6cd812f4e7edf220c40116d722)
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/411895
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
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TLB invalidate can have a race if several contexts use the same
address space. One thread starting an invalidate allows another
thread to submit before invalidate is completed.
Bug 1502332
Change-Id: I074ec493eac3b153c5f23d796a1dee1d8db24855
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/407578
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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Bug 1409151
Change-Id: I232af159d402f818cf972498d721c3b57846ce74
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
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This patch modifies the code to fall-back to 4k pages if the current
VA does not support 128k pages.
Bug 1409151
Change-Id: I94e9ca5953740388db689bc9306b0392191e29d2
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
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Bug 1443071
Change-Id: I225114835a5923061462e238395798b274cadd7b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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On 64 bit architecture, we have plenty of vmalloc space
so that we can keep all the ptes mapped always
But on 32 but architecture, vmalloc space is limited and
hence we have to map/unmap ptes when required
Hence add new APIs for arch64 and call them if
IS_ENABLED(CONFIG_ARM64) is true
Bug 1443071
Change-Id: I091d1d6a3883a1b158c5c88baeeff1882ea1fc8b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/387642
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add two fb flushes after bar1 bind. This should hang the thread instead
of whole system in case there is a BAR1 hang.
Change-Id: I2385a243711219297b889daa30c9fc81106e5825
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/390183
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This patch moves the NVIDIA GPU driver to a new location.
Bug 1482562
Change-Id: I24293810b9d0f1504fd9be00135e21dad656ccb6
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/383722
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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