| Commit message (Collapse) | Author | Age |
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This patch removes the dependency on the header file "uapi/linux/nvgpu.h"
for regops_gk20a.c. The original structure and definitions in the
uapi/linux/nvgpu.h is maintained for userspace libnvrm_gpu.h. The
following changes are made in this patch.
1) Defined common versions of the NVGPU_DBG_GPU_REG_OP* definitions inside
regops_gk20a.h.
2) Defined common version of struct nvgpu_dbg_gpu_reg_op inside
regops_gk20a.h naming it struct nvgpu_dbg_reg_op.
3) Constructed APIs to convert the NVGPU_DBG_GPU_REG_OP* definitions from
linux versions to common and vice versa.
4) Constructed APIs to convert from struct nvgpu_dbg_gpu_reg_op to
struct nvgpu_dbg_reg_op and vice versa.
5) The ioctl handler nvgpu_ioctl_channel_reg_ops first copies from
userspace into a local storage based on struct nvgpu_dbg_gpu_reg_op which
is copied into the struct nvgpu_dbg_reg_op using the APIs above and
after executing the regops handler passes the data back into userspace
by copying back data from struct nvgpu_dbg_reg_op to struct
nvgpu_dbg_gpu_reg_opi.
JIRA NVGPU-417
Change-Id: I23bad48d2967a629a6308c7484f3741a89db6537
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596972
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Remove separation of t18x specific code and fields and the associated
ifdefs. We can build T18x code in always.
Change-Id: I4e8eae9c30335632a2da48b418c6138193831b4f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595431
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Remove #include of <uapi/linux/nvgpu.h> from gr_gk20a.h.
vgpu_mm_gp10b.c uses UAPI definitions, so add an explicit #include
there.
JIRA NVGPU-363
Change-Id: Ieabd7240d62495d2719d7fdbc25cc238de13c75e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1598981
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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We use linux specific graphics/compute preemption modes defined in uapi header
(and of below form) in all over common code
NVGPU_GRAPHICS_PREEMPTION_MODE_*
NVGPU_COMPUTE_PREEMPTION_MODE_*
Since common code should be independent of linux specific code, define new modes
of the form in common code and used them everywhere
NVGPU_PREEMPTION_MODE_GRAPHICS_*
NVGPU_PREEMPTION_MODE_COMPUTE_*
Add required parser functions to convert both the modes into each other
For linux IOCTL NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE, we need to convert
linux specific modes into common modes first before passing them to common code
And to pass gpu characteristics to user space we need to first convert common
modes into linux specific modes and then pass them to user space
Jira NVGPU-392
Change-Id: I8c62c6859bdc1baa5b44eb31c7020e42d2462c8c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596930
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- Add update_patch_count parameter to ctx_patch_write_begin/end functions
If True, the main_image_patch_count register will be updated. Previously,
the patch count would be updated if the cpu_va for the graphics context
was non-NULL, but this only works for sysmem (cpu_va is always 0 for vidmem)
- Remove unused patch parameter for the commit_global_timeslice functions
JIRA ESRM-74
Bug 2012077
Change-Id: I35d0a9eb48669a227833bba1d2e63e9fe8fd8aa9
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594790
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max_css_buffer_size was accessed directly from GPU characteristics,
which added a dependency to Linux. Move the field to gr_gk20a and
copy it to GPU characteristics at query time.
JIRA NVGPU-259
Change-Id: Ied19e33bf1a79a9ce45e33df57fe5bbe3a3c4f9d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593689
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com>
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All the event ids NVGPU_IOCTL_CHANNEL_EVENT_ID_* are defined in linux
specific user header uapi/linux/nvgpu.h and can't be used in common
code
Hence add new definitions of type NVGPU_EVENT_ID_* for all the events
in common code and use them wherever required in common code
For future additions to event ids, we need to update both
NVGPU_IOCTL_CHANNEL_EVENT_ID_* and NVGPU_EVENT_ID_* fields
Also add new API nvgpu_event_id_to_ioctl_channel_event_id() to convert
common event_id of the form NVGPU_EVENT_ID_* to Linux specific event_id
of the form NVGPU_IOCTL_CHANNEL_EVENT_ID_*
Use this API in gk20a_channel/tsg_event_id_post_event() to get correct
event_id
Jira NVGPU-259
Change-Id: I15a7f41181fdbb8f1876f88bbcd044447d88325f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1591434
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Use nvgpu_alloc_obj_ctx_args structure specific to Linux code only.
Pass the fields of the structure as separate arguments to all common
functions.
gr_ops_gp10b.h referred to the struct, but it's not used anywhere,
so delete the file.
JIRA NVGPU-259
Change-Id: Idba78d48de1c30f205a42da2fe47a9f8c03735f1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1586563
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Allow per chip calculation of gr patch buffer size
and set default to match hw default of 512 data-address pair entries (4K)
bug 200350539
Change-Id: I6010c9e0304332825cb02612d3f10523ef27d128
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1584033
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Add a sysfs node to allow root user to set PRI_FE_GFXP_WFI_TIMEOUT, for gp10b
only, in units of sysclk cycles. Store the set value in a variable, and write
the set value to register after GPU is un-railgated.
NV_PGRAPH_PRI_FE_GFXP_WFI_TIMEOUT is engine_reset after Bug 1623341.
Change default value to be specified in cycles, rather than time. This value
is almost the current value in cycles calculated each boot.
Bug 1932782
Change-Id: I0a4207e637cd1413a1be95abe2bcce3adccf76fa
Reviewed-on: https://git-master.nvidia.com/r/1540939
Signed-off-by: Jonathan McCaffrey <jmccaffrey@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1580999
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Create an nvgpu internal nvgpu_gr_sm_error_state to store and
propagate SM error state within driver. Use
nvgpu_dbg_gpu_sm_error_state_record only in Linux code.
JIRA NVGPU-259
Change-Id: I7365cdf5a1a42cbcdb418dfcef3e0020e02a960f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1585645
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move functions to query preemption type names to the user of the
function: ioctl_channel.c. This removes a dependency to
<uapi/linux/nvgpu.h> from gr_gk20a.h.
JIRA NVGPU-259
Change-Id: I6cafda986eb4659fcfc1b19eac77e43aaaeaec76
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577248
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Patch buffer can hold 128 u32 entries. Each patch write
takes total of 2 u32 entries, 1 u32 for addr and 1 u32
for data. Ideally 64 entries could be written before buffer
overflows. Driver patch some things when creating the channel,
and later when context switch type is changed after channel is loaded.
Reset patch_ctx.data_count before beginning patch
write otherwise system might not be in a state to accept all
patch writes even if patch buffer has valid entries.
If the patch buffer has non-zero entries, then the patch buffer
would be read and all pri writes would be sent out. Once done,
ucode updates the main header patch buffer count to 0.
Without this fix, below priv errors seen on t186 platforms
SYS Write error for ADR 0, INFO 0d000200 and CODE badf1100
Error info decodes as:
NV_PPRIV_SYS_PRIV_ERROR_INFO R[0x00122128]
SUBID [29:24] 13 (?)
LOCAL_ORDERING [22:22] 0 (I)
PRIV_LEVEL [21:20] 0 (I)
SENDING_RS [17:12] 0 (I)
PENDING [ 9: 9] 1 (?)
ORPHAN [ 8: 8] 0 (I)
PRIV_MASTER [ 5: 0] 0 (I)
Ctxsw ucode(subid 13 i.e. 0xd) makes only few pri transactions
at priv level 0. Patch buffer pri writes are one of those.
Bug 200350539
Change-Id: If9e71b5fef4d85600d72a8a633a082d9261c3e1b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1581591
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move most of the dma_buf usage present in the mm_gk20a.c code
out to Linux specific code and some commom/mm code. There's
two primary groups of code:
1. dma_buf priv field code (for holding comptag data)
2. Comptag usage that relies on dma_buf pointers
For (1) the dma_buf code was simply moved to common/linux/dmabuf.c
since most of this code is clearly Linux specific.
The comptag code was a bit more complicated since there is two
parts to the comptag code. Firstly there's the code that manages
the comptag memory. This is essentially a simple allocator. This
was moved to common/mm/comptags.c since it can be shared across
all chips. The second set of code is moved to
common/linux/comptags.c since it is the interface between dma_bufs
and the comptag memory.
Two other fixes were done as well:
- Add struct gk20a to the comptag allocator init so that
the proper nvgpu_vzalloc() function could be used.
- Add necessary includes to common/linux/vm_priv.h.
JIRA NVGPU-30
JIRA NVGPU-138
Change-Id: I96c57f2763e5ebe18a2f2ee4b33e0e1a2597848c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566628
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Replace use of ioctl structure warpstate with internal
nvgpu_warptate.
JIRA NVGPU-259
Change-Id: I5170364d0443235cee471b87fa332fc09588f5d3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1578684
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Change license of OS independent source code files to MIT.
JIRA NVGPU-218
Change-Id: I1474065f4b552112786974a16cdf076c5179540e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1565880
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Initialize following counters in context header
for all legacy chips:
ctxsw_prog_main_image_num_save_ops
ctxsw_prog_main_image_num_restore_ops
This was already present in the code but move to a function
gk20a_gr_init_ctxsw_hdr_data, so that it can be re-used across
chips.
Additionally initialize following preemption related counters
for gp10b onwards in context header:
ctxsw_prog_main_image_num_wfi_save_ops
ctxsw_prog_main_image_num_cta_save_ops
ctxsw_prog_main_image_num_gfxp_save_ops
ctxsw_prog_main_image_num_cilp_save_ops
Bug 1958308
Change-Id: I0e45ec718a8f9ddb951b52c92137051b4f6a8c60
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1562654
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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We right now remove a channel from TSG list and disable all the channels in
TSG while removing a channel from TSG
With this sequence if any one channel in TSG is closed, rest of the channels
are set as timed out and cannot be used anymore
We need to fix this sequence as below to allow removing a channel from active
TSG so that rest of the channels can still be used
- disable all channels of TSG
- preempt TSG
- check if CTX_RELOAD is set if support is available
if CTX_RELOAD is set on channel, it should be moved to some other channel
- check if FAULTED is set if support is available
- if NEXT is set on channel then it means channel is still active
print out an error in this case for the time being until properly handled
- remove the channel from runlist
- remove channel from TSG list
- re-enable rest of the channels in TSG
- clean up the channel (same as regular channels)
Add below fifo operations to support checking channel status
g->ops.fifo.tsg_verify_status_ctx_reload
g->ops.fifo.tsg_verify_status_faulted
Define ops.fifo.tsg_verify_status_ctx_reload operation for gm20b/gp10b/gp106
as gm20b_fifo_tsg_verify_status_ctx_reload()
This API will check if channel to be released has CTX_RELOAD set, if yes
CTX_RELOAD needs to be moved to some other channel in TSG
Remove static from channel_gk20a_update_runlist() and export it
Bug 200327095
Change-Id: I0dd4be7c7e0b9b759389ec12c5a148a4b919d3e2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560637
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add a new sysfs node pd_max_batches for setting max batches value in
NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES register which controls
max number of batches per alpha-beta transition stored in PD.
Bug 1927124
Change-Id: I2817f2d70dab348d8b0b8ba19bf1e9b9d23ca907
Signed-off-by: Sandeep Shinde <sashinde@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1544104
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
(cherry picked from commit aa4daddda23aa44a84464200f497eac802a8e6ce)
Reviewed-on: https://git-master.nvidia.com/r/1543355
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Add init_ovr_sm_dsm_perf & get_ovr_perf_regs gr ops
JIRA GPUT19X-49
Bug 200311674
Change-Id: If02dd9dc0e2e0eb1f68fdbaa86a37c6768eddcef
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1497403
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add etpc ctxsw regs for t19x
Bug 200311674
Change-Id: I2d5076cb4df8040613c20d28518325ad7c6a9145
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1520140
GVS: Gerrit_Virtual_Submit
Tested-by: Tushar Kashalikar <tkashalikar@nvidia.com>
Reviewed-by: Tushar Kashalikar <tkashalikar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Required for multiple SM support and t19x SM
register address changes
JIRA GPUT19X-75
Change-Id: Iad39f8566e2f5f000b019837304df24d9e2a37e3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514043
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add lock_down_sm and wait_for_sm_lock_down gr ops
Required to support multiple SM and t19x SM register
address changes
JIRA GPUT19X-75
Change-Id: I529babde51d9b2143fe3740a4f67c582b7eb404b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514042
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This is required to take care of t19x changes to support
multiple SM
JIRA GPUT19X-75
Change-Id: Ifd2cb28ae442462fef1d2c4439baa817f00c2c9e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514041
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Required for multiple SM support and t19x sm register
address changes
JIRA GPUT19X-75
Change-Id: I437095cb8f8d2ba31b85594a7609532991441a37
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514040
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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mask_hww_warp_esr gr ops is removed and replaced with
get_sm_hww_warp_esr gr ops
JIRA GPUT19X-75
Change-Id: I8c7194ca1b0e4fe740a6f8998a02fba846234e9e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512218
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: I844b5cf02a75ba397891a1100d917875e5a3e181
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512217
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: If8805bcc042c75ea70c1689306feb3c8bf011655
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512216
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: Icdae3b6ed67a3d3deeb17f29528184b2d7a70af5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512215
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: Id104f611736535874cdaa5a2f768f692d799c2c5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512214
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Remove gk20a support. Leave only gk20a code which is reused by other
GPUs.
JIRA NVGPU-38
Change-Id: I3d5f2bc9f71cd9f161e64436561a5eadd5786a3b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master/r/1507927
GVS: Gerrit_Virtual_Submit
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hw_chid is a relative id for vgpu. For native it's same as hw id.
Renaming it to chid to avoid confusing.
Jira VFND-3796
Change-Id: I1c7924da1757330ace715a7c52ac61ec9dc7065c
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master/r/1509530
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-Add sm input param for handle_sm_exception and
pre_process_sm_exception for gr ops/functions.
-Add functions to calculate gpc and tpc reg offsets.
-Add function to find SMs which raised SM exception.
JIRA GPUT19X-75
Change-Id: I257e7342ddabadb1556c9551c50a54d34b0f9d1e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1476108
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
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- moved pg related code to pmu_pg.c under common/pmu folder
PG state machine support methods
PG ACK handlers
AELPG methods
PG enable/disable methods
-prepended with nvgpu_ for elpg/aelpg global methods
by replacing gk20a_
JIRA NVGPU-97
Change-Id: I2148a69ff86b5c5d43c521ff6e241db84afafd82
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1498363
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Since all debugfs code is Linux specific, remove
it from common code and move it to Linux module
Debugfs code is now divided into below
module specific files :
common/linux/debug.c
common/linux/debug_cde.c
common/linux/debug_ce.c
common/linux/debug_fifo.c
common/linux/debug_gr.c
common/linux/debug_mm.c
common/linux/debug_allocator.c
common/linux/debug_kmem.c
common/linux/debug_pmu.c
common/linux/debug_sched.c
Add corresponding header files for above modules too
And compile all of above files only if CONFIG_DEBUG_FS is set
Some more details of the changes made
- Move and rename gk20a/debug_gk20a.c to common/linux/debug.c
- Move and rename gk20a/debug_gk20a.h to include/nvgpu/debug.h
- Remove gm20b/debug_gm20b.c and gm20b/debug_gm20b.h and call
gk20a_init_debug_ops() directly from gm20b_init_hal()
- Update all debug APIs to receive struct gk20a as parameter
instead of receiving struct device pointer
- Update API gk20a_dmabuf_get_state() to receive struct gk20a
pointer instead of struct device
- Include <nvgpu/debug.h> explicitly in all files where debug
operations are used
- Remove "gk20a/platform_gk20a.h" include from HAL files
which no longer need this include
- Add new API gk20a_debug_deinit() to deinitialize debugfs
and call it from gk20a_remove()
- Move API gk20a_debug_dump_all_channel_status_ramfc() to
gk20a/fifo_gk20a.c
Jira NVGPU-62
Change-Id: I076975d3d7f669bdbe9212fa33d98529377feeb6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1488902
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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This is needed to enable chip specific gr exceptions
JIRA GPUT19X-75
Change-Id: I5ca8d0e51d00947c3ab1675bb6331207def433a4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1474851
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Change graphics initialization wait queue to use nvgpu_cond instead
of Linux wait queue.
JIRA NVGPU-14
Change-Id: I55ed64c29856947798e927ffaa5f1dbb1683b977
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1469851
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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(1) Re-arrange the structure for parity counters reporting so multiple
units can be managed
JIRA: GPUT19X-84
Change-Id: If59a883dfe22d5a1d91a6d0ed2f5a6254434ffcb
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1485276
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This CL covers the following modification,
1) Added gr_t19x support for gv11b ECC
2) Modified the gp10b platform config for
gv11b sysfs support
JIRA GPUT19X-85
JIRA GPUT19X-104
JIRA GPUT19X-100
JIRA GPUT19X-103
Bug 1825948
Bug 1825962
Bug 1775457
Change-Id: I0bf13f80a73cc2184147230d098e89a517554c01
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1478952
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This change adds a new sysfs node to allow configuring CZF_BYPASS, to
enable platforms with low context-switching latency requirements.
/sys/devices/17000000.gp10b/czf_bypass
Values:
0 - always
1 - lateZ (default)
2 - single pass
3 - never
The specified value will apply only to newly allocated contexts.
Bug 1914014
Change-Id: Ibb9a8e86089acaadaa7260b00eedec5c80762d6f
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1478567
(cherry picked from commit 3bc022cb385b53f698b04f218db535e8162e8c94)
Reviewed-on: http://git-master/r/1473820
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add new flag support_pmu to struct gk20a at probe time, and access it
from gk20a instead of support_gk20a_pmu() which depends on struct
device *.
JIRA NVGPU-16
Change-Id: I721f1a532e949c98346086abdc2630a8df6eba7b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1463546
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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set gr_idle_timeout_default to 100000 ms instead of MAX_SCHEDULE_TIMEOUT,
and enable timeouts_enabled
Change-Id: I0b4d014dc6f3fc3c365214f7ffad7af054f771b9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1458178
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Renaming was done with the following command:
$ find -type f | \
xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g'
Also rename mem_desc.[ch] to nvgpu_mem.[ch].
JIRA NVGPU-12
Change-Id: I69395758c22a56aa01e3dffbcded70a729bf559a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1325547
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Remove all usage of vmalloc.h and slab.h outside of the Linux specific
kmem API implementation code.
Bug 1799159
Bug 1823380
Change-Id: I5b2a91bd1057b272efeaddc24902f6133b35024f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1331703
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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ctrl_gk20a.c had some direct accesses to hardware. These violate the
HAL rules, because we don't have per-GPU ctrl, and thus the code
cannot be made GPU independent.
Move all GR accesses to new GR HALs and use existing bus HAL for
accessing timer. Remove #includes of all hardware headers.
JIRA NVGPU-28
Change-Id: I57e67519f62e9bd6c3e725e1bef6e366190f5834
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1327001
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Instead of using Linux APIs for mutex and spinlocks
directly, use new APIs defined in <nvgpu/lock.h>
Replace Linux specific mutex/spinlock declaration,
init, lock, unlock APIs with new APIs
e.g
struct mutex is replaced by struct nvgpu_mutex and
mutex_lock() is replaced by nvgpu_mutex_acquire()
And also include <nvgpu/lock.h> instead of including
<linux/mutex.h> and <linux/spinlock.h>
Add explicit nvgpu/lock.h includes to below
files to fix complilation failures.
gk20a/platform_gk20a.h
include/nvgpu/allocator.h
Jira NVGPU-13
Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1293187
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This ioctl can be used on gp10b to set a flag in the context header
indicating this context should be run at elevated clock
frequency. FECS ctxsw ucode will read this flag as part of the context
switch and will request higher GPU clock frequencies from BPMP for the
duration of the context execution.
Bug 1819874
Change-Id: I84bf580923d95585095716d49cea24e58c9440ed
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1292746
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Update zcull and perfmon buffer pointers in context
header through function pointers.
JIRA GV11B-48
Change-Id: Iaa6dd065128cb0c39e308cecf17b9d68a826d865
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1291850
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Remove including gk20a.h from pmu_gk20a.h. This causes a fallout
as some #includes were missing.
gr_gp10b.h uses mem_desc, but did not include mm_gk20a.h. Add the
include.
Including mm_gk20a.h in gr_gp10b.h causes recursive include, as
mm_gk20a.h has some gr defines. Move the defines to gr_gk20a.h to
remove the dependency.
gr_ctx_gk20a.h used struct gk20a pointers, but did not forward
declare it. Add a forward declaration.
gr_gk20a.h uses dbg_session_gk20a, but was missing forward
declaration.
gr_gk20a.h did not include nvgpu.h but it uses preemption types from
that header. Add include.
Change-Id: I2168e2303b55e0d187b816bcb26f37c8af1649ba
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1283717
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Use the timers API in the gk20a code instead of Linux specific
API calls.
This also changes the behavior of several functions to wait for
the full timeout for each operation that can timeout. Previously
the timeout was shared across each operation.
Bug 1799159
Change-Id: I2bbed54630667b2b879b56a63a853266afc1e5d8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1273826
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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