| Commit message (Collapse) | Author | Age |
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Compute a signature checksum for ctxsw ucode boot section and determine
the format of boot initialization data by it. This unifies gk20a and
gk20b ucode segment loading a lot by separating the bootloader loading
logic to separate functions.
Note: Whenever the boot segment binary changes, its updated signature
must be added here. Management of different bootloaders must be
supported for repo-crossing staging issues.
Bug 1519397
Change-Id: I96f9b905d3631dfdebf71ea3a652a0968615fd0a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/556679
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We do not need to wait for FE GO_IDLE counter to go to zero between
SW bundles.
Bug 1560770
Change-Id: I4cf53ea4e64b7244c589409d66c67ce8afb4a8d5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/558305
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Userspace access to gr_pri_bes_crop_hww_esr removed
on Tegra platform.
Remove gr_pri_bes_crop_hww_esr register from gk20a whitelist.
bug 1456562
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: Id9c3f85e39c970182283a0cdbb87ac5b6b83a534
Reviewed-on: http://git-master/r/553636
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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-Moved bind fecs from work queue to init_gr_support.
-It makes all CPU->FECS communication to happen before
booting PMU, and after we boot PMU, only PMU talks to
FECS. So it removes possibility to race between CPU
and PMU talking to FECS.
Bug 200032923
Change-Id: I01d6d7f61f5e3c0e788d9d77fcabe5a91fe86c84
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/559733
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GK20A PMU is not supported in GPU client for virtualization. However,
to make native case and virtualization case can share same defconfig and
kernel image, we need to enable CONFIG_GK20A_PMU and
CONFIG_GK20A_DEVFREQ in defconfig. This commit changes to detect if we
should disable GK20A PMU support in run time.
Bug 200041597
Change-Id: I292c647303ed57af6faa1c5671037ca27b48e31e
Signed-off-by: Haley Teng <hteng@nvidia.com>
Reviewed-on: http://git-master/r/553653
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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old value is for 1 SMs so on gm20b with 2 SMs it resulted in half zcull coverage
bug 1553171
Change-Id: I269f9a333a059b2ef533672df63ccaa90b2d00c7
Signed-off-by: David Li <davli@nvidia.com>
Reviewed-on: http://git-master/r/500517
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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At this stage, ctxsw is always in reset state, because we're powering GPU
up, or we have reset the whole GR partition. Remove the code to invoke a
second reset.
Fix waiting for FE idle. We should wait after each bundle, and break if any
iteration fails.
Change-Id: I0846f67c6d860a485dea62ff870deafe55a47365
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/552799
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Move nvgpu ioctls from the many user space interface headers to a new
single nvgpu.h header under include/uapi. No new code or replaced names
are introduced; this change only moves the definitions and changes
include directives accordingly.
Bug 1434573
Change-Id: I4d02415148e437a4e3edad221e08785fac377e91
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/542651
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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To help remove the nvhost dependency from nvgpu, rename ioctl defines
and structures used by nvgpu such that nvhost is replaced by nvgpu.
Duplicate some structures as needed.
Update header guards and such accordingly.
Change-Id: Ifc3a867713072bae70256502735583ab38381877
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/542620
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fix calculation of the debug buffer address.
Bug 1551221
Change-Id: I8d7921070549a1689dba0675d83bfdbf76ba5193
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/500705
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Riku Salminen <rsalminen@nvidia.com>
Tested-by: Riku Salminen <rsalminen@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Restrict reading of FE object table to the number of entries
available.
Change-Id: I11275ecd14e53f0b763d00d65042adb4b1e8ae6f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/449306
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Add poll interface and control ioctls for waiting for GPU job completion
via semaphores.
Poll on a gk20a channel file waits for events from pending semaphore
interrupts (stalling) of that channel. New ioctls enable and disable the
events, and clear a single interrupt event so that next poll doesn't
wake up for it again.
Bug 1528781
Change-Id: I5c6238966b5d0900c8ab263c6a7f8f2611901f33
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/497750
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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When determining the chid for the current context, first check
the ctx valid bit.
Bug 1485555
Change-Id: I6c3096d800a6cef38b656d525437a2c4f8b45774
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Reviewed-on: http://git-master/r/496140
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Geoffrey Gerfin <ggerfin@nvidia.com>
Tested-by: Geoffrey Gerfin <ggerfin@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We store a reference to common address space of channels
in struct tsg_gk20a without increasing the refcount
This could result in freeing the address space even when
some channel in TSG needs it or when we need to free
common gr_ctx
Fix this by getting ref using gk20a_vm_get() when we store
the VM reference. We drop this reference with
gk20a_vm_put() when closing the TSG
Bug 1470692
Change-Id: Ifc1f29d32cd721810bfbb5a4db96095770318c17
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/495668
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gr_gk20a.c : railgating path the crash was seen
with multiple frees happening
acr_gm20b.c : failure path, kernel panic was seen,
with multiple frees
Change-Id: Ifc5e78c0ee74799c7f78e6030c02d1a27d545a1e
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/494161
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Regenerate clock gating lists. Add new blocks, and takes them into
use. Also moves some clock gating settings to be applied at the
earliest possible moment right after reset.
Change-Id: I21888186c200f7a477c63bd3332e8ed578f63741
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/457698
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Bug 1500195
Change-Id: I5545d1a95a58e7daa5a74cc20f3fc6828774fc42
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/488507
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change-Id: Ia9ab5ef8fbe3244b44c911d8808123e0aaf860cf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/488611
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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The nvgpu driver now supports using the Tegra graphics virtualization
interfaces to support gk20a in a virtualized environment.
Bug 1509608
Change-Id: I6ede15ee7bf0b0ad8a13e8eb5f557c3516ead676
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/440122
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add support for multiple GPCs/TPCs to the GPC/TPC
exception handling code.
Change-Id: Ifb4b53a016e90cb54c4d985a9e17760f87c6046f
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/411660
Reviewed-by: Automatic_Commit_Validation_User
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Bug 1534793
Change-Id: I8a4c35914b58dd13a7c10c668de9d4662d947d8c
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/441377
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Retrieve which TPC is floorswept.
Bug 1450798
Change-Id: I3ea60703695448c68cd3435f443b280d5b2f0995
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/403876
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Disable cyclestats register whitelist check if allow_all is
enabled through sysfs.
bug 1523403
bug 1490388
Change-Id: Iaa1cf9a8fed18f1a379cac28128793fb33567f35
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/454932
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Through this sysfs entry, the register space becomes accessible.
This is be accessible root-only.
Bug 1523403
Change-Id: Ia46f130a0cfd8324c5b675d19e7cbfba9dcb17ca
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/454198
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We have hardcoded compbit backing store to cover 1MB of memory in
ASIM. Remove that hard coding and use the total memory size instead.
Change-Id: Ibb5c6ae88015960fa360ddd5f7bba05949d4da7b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/450313
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Newer netlist does not require image size queries to boot. Save 2ms
from GPU boot time by skipping it if we know the sizes.
Bug 1435870
Change-Id: Ie1b13c8a6e420adf06e635bde8b469385e1d5c60
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/419873
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Add retrieving error code for FECS errors.
Change-Id: I7d9dfc4723376272edb2e5b2ef06f71de1a06889
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/450351
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chris Dragan <kdragan@nvidia.com>
Tested-by: Chris Dragan <kdragan@nvidia.com>
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In cases where a kernel channel dies, we can reload the context by
just reloading the golden context buffer. This patch makes necessary
infrastructural changes to support this behaviour.
Bug 1409151
Change-Id: Ibe6a88bf7acea2d3aced2b86a7a687279075c386
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/440262
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com>
GVS: Gerrit_Virtual_Submit
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gr_ctx is nowadays kalloc()'d separately. Adding kfree() to prevent
memory leak.
Bug 1528275
Change-Id: I942812a483adad47e82bc75a7bda5942c30c527a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/428890
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Boot FECS to secure mode if ACR is enabled.
Bug 200006956
Change-Id: Ifc107704a6456af837b7f6c513c04d152b2f4d3a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/424251
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All channels in a TSG need to share same engine context
i.e. pointer in RAMFC of all channels in a TSG must point
to same NV_RAMIN_GR_WFI_TARGET
To get this, add a pointer to gr_ctx inside TSG struct so
that TSG can maintain its own unique gr_ctx
Also, change the type of gr_ctx in a channel to pointer
variable so that if channel is part of TSG it can point
to TSG's gr_ctx otherwise it will point to its own gr_ctx
In gk20a_alloc_obj_ctx(), allocate gr_ctx as below :
1) If channel is not part of any TSG
- allocate its own gr_ctx buffer if it is already not allocated
2) If channel is part of TSG
- Check if TSG has already allocated gr_ctx (as part of TSG)
- If yes, channel's gr_ctx will point to that of TSG's
- If not, then it means channels is first to be bounded to
this TSG
- And in this case we will allocate new gr_ctx on TSG first
and then make channel's gr_ctx to point to this gr_ctx
Also, gr_ctx will be released as below ;
1) If channels is not part of TSG, then it will be released
when channels is closed
2) Otherwise, it will be released when TSG itself is closed
Bug 1470692
Change-Id: Id347217d5b462e0e972cd3d79d17795b37034a50
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/417065
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Allocate dummy secure buffer of size PAGE_SIZE during gk20a_probe().
This will also help to initiate first secure memory (VPR)
resize call while GPU is rail gated and in reset.
This dummy buffer is released after we allocate some more
secure memory buffers in alloc_global_ctx_buffers()
Bug 1487804
Change-Id: I61604d9e5ffb585801ee893435c98a0d3e69d666
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/421701
(cherry picked from commit 4236ab3323ee3c02fac562740d8b80d763589dea)
Reviewed-on: http://git-master/r/419610
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Print interrupt code and channel id for unhandled gr class error.
Bug 200010403
Change-Id: Iedceaf4b8b6363b26f1836256875fb9b5c43eded
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/419566
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Rewrite PMU boot sequence as a state machine. At PMU power-up send
initial messages, and reset state machine. At each reply from PMU,
do the next stage of PMU boot and set state.
As now PMU and FECS boot are independent, we need to ensure engine
idle before saving ZBC.
Change-Id: I1ea747ab794ef08f1784eeabfdae7655d585ff21
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/410205
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When exiting rail gate, we reloaded default ZBC values. The correct
behavior is to reload the values.
Bug 1447255
Change-Id: I7aad3586dda91a91a3629062a27001af281b955e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/418346
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On FECS arbiter timeout, dump ARB status.
Change-Id: I4f8c4d38c99e35ce751172a8695e950f0ce594c8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/417753
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gk20a_mm_fb_flush() invoked G_ELPG_FLUSH and FB_FLUSH. Remove the
invokation of G_ELPG_FLUSH. Replace calls to gk20a_mm_fb_flush() with
gk20a_mm_l2_flush() when appropriate.
Bug 1421824
Change-Id: I02af4bdc3b7bd26d0f6a8d610f70349269775a36
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/408210
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Implement support for partial buffer mappings.
Whitelist gr_pri_bes_crop_hww_esr accessed by
fec during sparse texture initialization.
bug 1456562
bug 1369014
bug 1361532
Change-Id: Ib0d1ec6438257ac14b40c8466b37856b67e7e34d
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/375012
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Instead of calling second phase of PMU boot sequence, initialize FECS
directly.
Change-Id: I7f9de0c5ec42049033839d244979f3f3daabf317
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/410204
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Add support for booting FECS and GPCCS via faster bootloader method.
We leave this disabled until the bootloader binaries are checked in.
Change-Id: I39df5d116f7a33486407518c743638b01923970d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/413005
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Boot FECS/GPCCS with old method on gm20b. We don't yet have
bootloader for it.
Change-Id: I09046960cd86b0402d3ea2cd8e4c92597766fa10
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/412604
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Remove redundant cache maintenance operations. Instance blocks and
graphics context buffers are uncached, so they do not need any cache
maintenance.
Bug 1421824
Change-Id: Ie0be67bf0be493d9ec9e6f8226f2f9359cba9f54
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/406948
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PMU, FECS and GPCCS use the same address space. We used to initialize
the address space only if PMU is enabled. Create the system address
space always.
FECS and GPCCS used to have slower bit bang and faster DMA method
for loading ucode. Slower method is needed when FECS and GPCCS do not
have an address space. Remove the slower method as not anymore
needed.
Change-Id: I155619741ecc36aa6bf13a9c1ccb03c7c1330f0a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/406771
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fixes one use of unitialized var
renames a register to make it match dev_* file.
Change-Id: Iafba659bbf2df509e0b494b2c5dab3819bf650ef
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/394792
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Waiting for FE idle hangs on simulation, so skip it.
Change-Id: I4f49eab725fcf2eb0b8340040a79731e16a1a0a0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/394053
Reviewed-on: http://git-master/r/396374
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
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Implement gm20b specific gr ops.
Bug 1387211
Change-Id: I4523311f1c155ba2d3403dcf222769f6817b2450
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/362415
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
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Add a place to edit context-switched perf settings based upon
class. Disable tex-lock as the first of such for compute.
Bug 1409041
Change-Id: I5317a2a2e5f855661a1400b42f69211d16ae0c1d
Signed-off-by: Randy Spurlock <rspurlock@nvidia.com>
Reviewed-on: http://git-master/r/405908
(cherry picked from commit 250e149be35ecb8893dcef053ec44ffea86c302a)
Reviewed-on: http://git-master/r/407094
(cherry picked from commit 54337c08cbf6c2c6b5c929c1be24e87165d9d946)
Reviewed-on: http://git-master/r/408837
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
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Add handler gk20a_gr_handle_fecs_error() in case we have
pending fecs error interrupt
And clear this interrupt after handling.
Also, in gk20a_gr_handle_fecs_error(), for now just print
the contents of NV_PGRAPH_FECS_INTR and clear it
Bug 1495957
Change-Id: Ie7f70c84ec76ab698141646cd683584c4501e3e0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/402874
(cherry picked from commit a29f219c57d65a06f6dae8086f19fa1af94d95bd)
Reviewed-on: http://git-master/r/403587
(cherry picked from commit e65ebebd0d4d5c3dbb6fa454dd51c383ea13d715)
Reviewed-on: http://git-master/r/411160
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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This change disables gr engine before calling into pmu
for saving zbc and re-enables once it is finished.
Looks like NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_TIMEOUT
error during access of NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE
happens because of active concurrent memory traffic.
Bug 1489850
Change-Id: I60eacd718480a296f5a46438e18a519c7457f58a
Signed-off-by: Santosh Katvate <skatvate@nvidia.com>
Reviewed-on: http://git-master/r/398398
GVS: Gerrit_Virtual_Submit
(cherry picked from commit 42931088a3a1944359be61ebe39c646b41f73ee6)
Reviewed-on: http://git-master/r/402779
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>
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Add abstraction for triggering fake MMU fault, and a gk20a
implementation. Also adds recovery to FE hardware warning
exception to make testing easier.
Bug 1495967
Change-Id: I6703cff37900a4c4592023423f9c0b31a8928db2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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