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* gpu: nvgpu: Use HAL for waiting for GR quietTerje Bergstrom2015-06-01
| | | | | | | | | | | | | | | Create a HAL for waiting for GR to become quiet. Use it forall cases where we require GR to be quiet, but where it does not need to be idle. Bug 1640378 Change-Id: Ic0222d595a2d049e0fa8864b069ab94a97fac143 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/745640 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: Dynamic betacb sizeTerje Bergstrom2015-05-18
| | | | | | | | | | | Allow querying and setting default betacb size via debugfs. For global buffers the value takes effect upon first boot of GPU, and has no effect after that. Bug 1628352 Change-Id: Ib63f4299249c41eab1b36cc501b525cc54211195 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/733328
* gpu: nvgpu: fix setting gr_pd_ab_dist_cfg1_r()David Li2015-05-18
| | | | | | | | | | | | | gr_*__set_alpha_circular_buffer_size() left max_batches field of gr_pd_ab_dist_cfg1_r as 0 which results in too many alpha beta transitions and poor performance when tessellation or geometry shaders are used Change-Id: If18feb1119e9672005455155dc56337cd444a1f1 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: http://git-master/r/735476 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: dbg level for per-write ctx patch msgKonsta Holtta2015-05-18
| | | | | | | | | | | | | The message "per-write ctx patch begin?" is a legacy message for warning about probably inefficient code, but it's written at error loglevel. Silence it out a bit by using gk20a_dbg_info(). The inefficient paths can be fixed later. Bug 200075565 Change-Id: Idae821aef3001ea5016de22a1a87fec747c42d31 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/734248
* gpu: nvgpu: zbc: disable activity only from ioctlTerje Bergstrom2015-05-18
| | | | | | | | | | | | | Move the fifo engine activity disabling and wait-for-idle from the lowest-level functions higher, into the ioctl path of zbc operations, so that the sw initialization path wouldn't call them. During the init path, the disable isn't necessary, and the code path could result in a deadlock in the fifo runlist mutex. Change-Id: Icf5c270ba29bc1c7f88874fba2d176d68e11278a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/733668
* gpu: nvgpu: Use common allocator for patchTerje Bergstrom2015-05-05
| | | | | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by using common helpers, and common data structure for storing results of allocations. Bug 1605769 Change-Id: Idf51831e8be9cabe1ab9122b18317137fde6339f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/721030 Reviewed-on: http://git-master/r/737530 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
* Revert "gpu: nvgpu: zbc: disable activity only ...Sam Payne2015-04-04
| | | | | | | | | | | | This reverts commit 83bc90620f863977101a164780de360bcd0aa088. bug 1628118 Change-Id: I478f9dd3685b55b4fce18354d475ee0b817a7775 Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/727152 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use common allocator for contextTerje Bergstrom2015-04-04
| | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by using common helpers, and common data structure for storing results of allocations. Bug 1605769 Change-Id: I10c226e2377aa867a5cf11be61d08a9d67206b1d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/720507
* gpu: nvgpu: fix sparse tool warningsSandarbh Jain2015-04-04
| | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warning: -drivers/gpu/nvgpu/gk20a/gr_gk20a.c:6028:6: warning: symbol 'gr_gk20a_init_sm_dsm_reg_info' was not declared. Should it be static? -gr_gk20a.c:6174:6: warning: symbol 'gr_gk20a_get_sm_dsm_perf_regs' was not declared. Should it be static? -gr_gk20a.c:6184:6: warning: symbol 'gr_gk20a_get_sm_dsm_perf_ctrl_regs' was not declared. Should it be static? -gr_gm20b.c:465:6: warning: symbol 'gr_gm20b_init_sm_dsm_reg_info' was not declared. Should it be static? -gr_gm20b.c:476:6: warning: symbol 'gr_gm20b_get_sm_dsm_perf_regs' was not declared. Should it be static? -gr_gm20b.c:486:6: warning: symbol 'gr_gm20b_get_sm_dsm_perf_ctrl_regs' was not declared. Should it be static? Bug 200067946 Change-Id: Ic14080e94e343386f4fef379152a623c402984fd Signed-off-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-on: http://git-master/r/723518 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: add platform specific get_iova_addr()Deepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | Add platform specific API pointer (*get_iova_addr)() which can be used to get iova/physical address from given scatterlist and flags Use this API with g->ops.mm.get_iova_addr() instead of calling API gk20a_mm_iova_addr() which makes it platform specific Bug 1605653 Change-Id: I798763db1501bd0b16e84daab68f6093a83caac2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/713089 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use common allocator for compbit storeTerje Bergstrom2015-04-04
| | | | | | | | | | | | Reduce amount of duplicate code around memory allocation by using common helpers, and common data structure for storing results of allocations. Bug 1605769 Change-Id: I7c1662b669ed8c86465254f6001e536141051ee5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/720435
* gpu: nvgpu: Catch DS exceptionTerje Bergstrom2015-04-04
| | | | | | | | Catch DS exception and write an error to UART. Change-Id: Iaad9813c48191f0d3d734d4af264b976a3818672 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/679142
* gpu: nvgpu: GM20B extended buffer definitionSandarbh Jain2015-04-04
| | | | | | | | | | | | | | | | Update extended buffer definition for Maxwell. On GM20B only PERF_CONTROL0 and PERF_CONTROL5 registers are restored in extended buffer. They are needed for stopping the counters as late as possible during ctx save and start them as early as possible during context restore. On Maxwell, these registers contain the enable/disable bit. Bug 200086767 Change-Id: I59125a2f04bd0975be8a1ccecf993c9370f20337 Signed-off-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-on: http://git-master/r/717421 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not touch gr status maskTerje Bergstrom2015-04-04
| | | | | | | | | GR status disable mask was never set, so driver always disabled all engines from status rollup. Change-Id: I500a127be9253294f73d1f42ce89b886471a9117 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/719141
* gpu: nvgpu: zbc: disable activity only from ioctlKonsta Holtta2015-04-04
| | | | | | | | | | | | | | Move the fifo engine activity disabling and wait-for-idle from the lowest-level functions higher, into the ioctl path of zbc operations, so that the sw initialization path wouldn't call them. During the init path, the disable isn't necessary, and the code path could result in a deadlock in the fifo runlist mutex. Change-Id: Ia3d768b7ad2d829416a1144486e6788d3177eb04 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/715195 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: make the local function staticAmit Sharma (SW-TEGRA)2015-04-04
| | | | | | | | | | | | | | | | | | | Fixed the following sparse warnings by making below APIs static: - gk20a.c: warning: symbol 'gk20a_pm_restore_debug_setting' was not declared. Should it be static? - gr_gk20a.c: warning: symbol 'gr_gk20a_rop_l2_en_mask' was not declared. Should it be static? - gr_gm20b.c: warning: symbol 'gr_gm20b_rop_l2_en_mask' was not declared. Should it be static? Bug 200067946 Change-Id: I334893bb6614171bff835d270716a7dd262c9ba7 Signed-off-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-on: http://git-master/r/718756 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Implement common allocator and mem_descTerje Bergstrom2015-04-04
| | | | | | | | | | Introduce mem_desc, which holds all information needed for a buffer. Implement helper functions for allocation and freeing that use this data type. Change-Id: I82c88595d058d4fb8c5c5fbf19d13269e48e422f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/712699
* gpu: nvgpu: Gpu characterstics enhancementsujeet baranwal2015-04-04
| | | | | | | | | | | New members are added in nvgpu_gpu_characterstics to export more information required specially from CUDA tools. Change-Id: I907f3bcbd272405a13f47ef6236bc2cff01c6c80 Signed-off-by: Sujeet Baranwal <sbaranwal@nvidia.com> Reviewed-on: http://git-master/r/679202 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Removal of regops from CUDA driversujeet baranwal2015-04-04
| | | | | | | | | | | | | | | | The current CUDA drivers have been using the regops to directly accessing the GPU registers from user space through the dbg node. This is a security hole and needs to be avoided. The patch alternatively implements the similar functionality in the kernel and provide an ioctl for it. Bug 200083334 Change-Id: Ic5ff5a215cbabe7a46837bc4e15efcceb0df0367 Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com> Reviewed-on: http://git-master/r/711758 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: do not enable unhandled exceptionsDeepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | | | | | We currently have below exceptions enabled but we do not have any handler for them. So if any of these exception is raised, we do not clear it. NV_PGRAPH_EXCEPTION_PD NV_PGRAPH_EXCEPTION_SCC NV_PGRAPH_EXCEPTION_DS NV_PGRAPH_EXCEPTION_MME NV_PGRAPH_EXCEPTION_SKED Hence do not enable above exceptions. Bug 200078514 Change-Id: I0dd3a2299f80f3fe06994818f64151e7cc83a84e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/714166 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: handle memfmt exceptionDeepak Nibade2015-04-04
| | | | | | | | | | | | | | | | In gk20a_gr_isr(), handle memfmt exception as below : - read NV_PGRAPH_PRI_MEMFMT_HWW_ESR - debug print for contents of above register - write same value back to NV_PGRAPH_PRI_MEMFMT_HWW_ESR and clear the exception Bug 200078514 Change-Id: I5b9afacd7f99b5a37de953041582b3a53b863642 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/713713 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add exception registers to dumpDeepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | Add below exception registers to GR dump : NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN Bug 200078514 Change-Id: Ib0ec34f7bf5a136928c53cf8398b4929fb4639c5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/712480 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix some GPU boot error pathsTerje Bergstrom2015-04-04
| | | | | | | | Fix panics in error path when FECS cannot be booted. Change-Id: I354e37579386e27f46b80cd4172fe12897a3b92f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/712698
* gpu: nvgpu: gk20a: Sparse warning fixSupriya2015-04-04
| | | | | | | | | | | | Bug 200067946 Change-Id: Ifec926b406c1daf0295d9ee07f1962b56c1b603a Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/711479 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ioctl for flushing GPU L2sujeet baranwal2015-04-04
| | | | | | | | | | | | | | CUDA devtools need to be able to flush the GPU's cache in a sideband fashion and so cannot use methods. This change implements an nvgpu_gpu_ioctl to flush and optionally invalidate the GPU's L2 cache and flush fb. Change-Id: Ib06a0bc8d8880ffbfe4b056518cc3c3df0cc4988 Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com> Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com> Reviewed-on: http://git-master/r/671809 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Disable GO_IDLE timeout and skip waitingTerje Bergstrom2015-04-04
| | | | | | | | | Disable GO_IDLE timeout when pushing SW methods. This stops FE_GI bit from getting enabled, so remove polling for that, too. Change-Id: I695aa9fbc68d4fe722ae46a28d7f4cc05db75b3b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/709878
* gpu: nvgpu: Fix if/else conds if PMU flag is OFF.Deepak Goyal2015-04-04
| | | | | | | | | | | | | | | | | | bug 200069748 Invalidating FECS code instblk is required only if FECS uses bootloader to load. Added check for same instead of using PMU support to invalidate. Handle elpg enable/disable call in case PMU is OFF. Change-Id: I28abbbbe1f22edd9e0417df9d0e831bbd770502c Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/670664 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: APIs to dump GR statusDeepak Nibade2015-04-04
| | | | | | | | | | | | | | | | | | Add below APIs to dump various GR status registers 1. debugfs : /d/gpu.0/gr_status Read this debugfs at runtime to get status registers 2. API gk20a_gr_debug_dump() Add this API in code to dump registers at any point Bug 200062436 Change-Id: Ic1115b5a2fc16362954b5ed8a9e70afb872a8d91 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/486465 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: optimize fecs status pollingVijayakumar2015-04-04
| | | | | | | | | | | | | | | | bug 200078367 using udelay for fecs status polling during GR init phase brings down fecs transaction time to < 20usec from few hundred usec. Change-Id: I61a27daaf1187ac086a42779b46aa3fbee3b37f2 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/691918 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gk20a: FECS HALT methodSupriya2015-04-04
| | | | | | | | | | | | FECS halt method is used to do graceful FECS shutdown. Bug 1551865 Change-Id: Iec8590e86cb09f9b54c36f85859208fc8650f6a6 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/682459 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use busy looping on memory opsTerje Bergstrom2015-04-04
| | | | | | | | | | | | Use busy looping on L2 and TLB maintenance operations. This speeds them up by an order of magnitude. Add also trace points to measure performance for memory ops and interrupt processing. Change-Id: Ic4a8525d3d946b2b8f57b4b8ddcfc61605619399 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/681640
* gpu: nvgpu: unify instance block initializationKonsta Holtta2015-04-04
| | | | | | | | | | | Create gk20a_init_inst_block() to reduce reg write clutter when initializing instance blocks, which is done in several places. Change-Id: Idcb8b604851a849e0bb6abce5743c9f4cbf98033 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/672434 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gk20a: Set lockboost size for computeTerje Bergstrom2015-04-04
| | | | | | | | | | | For compute channel on gk20a, set lockboost size to zero. Bug 1573856 Change-Id: I369cebf72241e4017e7d380c82caff6014e42984 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/594843 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gm20b: Enable CTA preemptionTerje Bergstrom2015-04-04
| | | | | | | | | | | | CTA preemption needs to be enabled by setting a value in context. Set it for gm20b. Bug 200063473 Bug 1517461 Change-Id: I080cd71b348d08f834fd23ebbe7443dba79224db Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/661299
* gpu: nvgpu: unify instance block creationKonsta Holtta2015-04-04
| | | | | | | | | | | Reduce copypaste code in instance block allocation and deletion with functions purposed for that. Change-Id: I2c8ae6a317ac89e2c857dde4296cb4316b8aaafe Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/668698 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Pre-Population of zbc entriessujeet baranwal2015-04-04
| | | | | | | | | | | | | | | | | | | | The default zbc entries were never populated in zbc HW table because the conditional flag "gr->sw_ready" was always set thus avoided the zbc default loading function call. Now zbc default loading would happen only during boot time in sw structure.Hw zbc regs would be loaded from that structure every time a railgate exit happens. Bug 1580210 Change-Id: Ie3e40738cbc84cf724c3f3871f15b17a5c84025a Signed-off-by: Sujeet Baranwal <sbaranwal@nvidia.com> Reviewed-on: http://git-master/r/662306 Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Tested-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix/HACK for v3.18Dan Willemsen2015-03-18
| | | | Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
* gpu: nvgpu: Per-chip context creationTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Add HAL for context creation, and expose functions that T18x context creation needs. Bug 1517461 Bug 1521790 Bug 200063473 Change-Id: I63d1c52594e851570b677184a4585d402125a86d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/660237
* gpu: nvgpu: Generic mem_desc & allocationTerje Bergstrom2015-03-18
| | | | | | | | | | | | Make mem_desc a generic container for buffers. Add functions for allocating and mapping buffers to an address space which store their data in mem_desc. Change-Id: I031643442c6fd41f5e7222fe9b7bfcaf9b784db5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/660908 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: Simplify pagepool size queryTerje Bergstrom2015-03-18
| | | | | | | | | | | Make pagepool size query into a function instead of storing the value during boot time in a structure. This simplifies the structure and users of pagepool size do not need to worry about whether it has already been set. Change-Id: Iba16e840cdf9b6c39449730237aa7d8fdff47848 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/660907
* gpu: nvgpu: Implement per-chip pagepool sizeTerje Bergstrom2015-03-18
| | | | | | | | | | Bug 1567274 Change-Id: Ib366f56c109f60be98435124e9e73697d161c4d0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/606935 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Physical page bits to be per chipTerje Bergstrom2015-03-18
| | | | | | | | | | Retrieve number of physical page bits based on chip. Bug 1567274 Change-Id: I5a0f6a66be37f2cf720d66b5bdb2b704cd992234 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601700
* gpu: nvgpu: Add HAL for add ZBC color & depthTerje Bergstrom2015-03-18
| | | | | | | | | | | Turn add ZBC functions into HALs that can be filled per chip. Bug 1567274 Change-Id: Ic6ef29d3353d4a0079ea0c80f513ffd579fe554f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601109 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: support config of TPC FUSE dynamicallyDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Follow steps below to config active TPC number: echo 1 > /sys/devices/platform/host1x/gpu.0/force_idle echo 0x1/0x2/0x3 > /sys/devices/platform/host1x/gpu.0/tpc_fs_mask echo 0 > /sys/devices/platform/host1x/gpu.0/force_idle where, 0x1 : disable TPC1 0x2 : disable TPC0 0x3 : both TPCs active Also, add API set_gpc_tpc_mask to update the TPCs and call this API after update to sysfs "tpc_fs_mask" Once fuses are updated for new TPC settings, we need to reconfigure GR and golden_image. Hence disable gr->sw_ready and golden_image_initialized flags. Also, initialize gr->tpc_count = 0 each time in gr_gk20a_init_gr_config(), otherwise it goes on adding tpc count Bug 1513685 Change-Id: Ib50bafef08664262f8426ac0d6cbad74b32c5909 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/552606 Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: GPU characteristics additionsSami Kiminki2015-03-18
| | | | | | | | | | | | | | | | | Add the following info into GPU characteristics: available big page sizes, support indicators for sync fence fds and cycle stats, gpc mask, SM version, SM SPA version and warp count, and IOCTL interface levels. Also, add new IOCTL to fetch TPC masks. Bug 1551769 Bug 1558186 Change-Id: I8a47d882645f29c7bf0c8f74334ebf47240e41de Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/562904 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: explicitly disable elcg during initVijayakumar2015-03-18
| | | | | | | | | | bug 200048467 Change-Id: I39f85a638b6bc97442ebf8e4a78e07c8575e4b20 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/592751 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix sparse warningsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | Fix below sparse warnings : warning: Using plain integer as NULL pointer warning: symbol <variable/funcion> was not declared. Should it be static? warning: Initializer entry defined twice Also, remove dead functions Bug 1573254 Change-Id: I29d71ecc01c841233cf6b26c9088ca8874773469 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/593363 Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Regenerate HW headersTerje Bergstrom2015-03-18
| | | | | | | Regenerate HW headers after adding SM debugger registers. Change-Id: Icc47c11f8e9ff52c0cf1f3a54233fb781c2c2b67 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: warn on nested ctx patch beginKonsta Holtta2015-03-18
| | | | | | | | | Add WARN_ON to a critical error condition to get a backtrace dump. Bug 200046882 Change-Id: I76c4186024547c6e89f1465612fe17f44e27eefe Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: disable cg in mmu error handlerVijayakumar2015-03-18
| | | | | | | | | | | | | | With CG enabled sometimes fifo could not be idled during firmware load. Bug 200042729 Change-Id: I43d7551c0c7c19314c52ac5f678afed8c6df6415 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/559077 Reviewed-by: Automatic_Commit_Validation_User
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-27 15:13:13 -0400