summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
Commit message (Collapse)AuthorAge
* gpu: nvgpu: allocate secure buffer in probeDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | Allocate dummy secure buffer of size PAGE_SIZE during gk20a_probe(). This will also help to initiate first secure memory (VPR) resize call while GPU is rail gated and in reset. This dummy buffer is released after we allocate some more secure memory buffers in alloc_global_ctx_buffers() Bug 1487804 Change-Id: I61604d9e5ffb585801ee893435c98a0d3e69d666 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/421701 (cherry picked from commit 4236ab3323ee3c02fac562740d8b80d763589dea) Reviewed-on: http://git-master/r/419610 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: print intr code for class errorDeepak Nibade2015-03-18
| | | | | | | | | | | | Print interrupt code and channel id for unhandled gr class error. Bug 200010403 Change-Id: Iedceaf4b8b6363b26f1836256875fb9b5c43eded Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/419566 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Rewrite PMU boot-up sequenceTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Rewrite PMU boot sequence as a state machine. At PMU power-up send initial messages, and reset state machine. At each reply from PMU, do the next stage of PMU boot and set state. As now PMU and FECS boot are independent, we need to ensure engine idle before saving ZBC. Change-Id: I1ea747ab794ef08f1784eeabfdae7655d585ff21 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/410205
* gpu: nvgpu: Reload ZBC values on rail gate exitTerje Bergstrom2015-03-18
| | | | | | | | | | | When exiting rail gate, we reloaded default ZBC values. The correct behavior is to reload the values. Bug 1447255 Change-Id: I7aad3586dda91a91a3629062a27001af281b955e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/418346
* gpu: nvgpu: On FECS error, dump ARB statusTerje Bergstrom2015-03-18
| | | | | | | | On FECS arbiter timeout, dump ARB status. Change-Id: I4f8c4d38c99e35ce751172a8695e950f0ce594c8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/417753
* gpu: nvgpu: Remove extraneous FB flush callsTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | gk20a_mm_fb_flush() invoked G_ELPG_FLUSH and FB_FLUSH. Remove the invokation of G_ELPG_FLUSH. Replace calls to gk20a_mm_fb_flush() with gk20a_mm_l2_flush() when appropriate. Bug 1421824 Change-Id: I02af4bdc3b7bd26d0f6a8d610f70349269775a36 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/408210 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: implement mapping for sparse allocationKirill Artamonov2015-03-18
| | | | | | | | | | | | | | | | Implement support for partial buffer mappings. Whitelist gr_pri_bes_crop_hww_esr accessed by fec during sparse texture initialization. bug 1456562 bug 1369014 bug 1361532 Change-Id: Ib0d1ec6438257ac14b40c8466b37856b67e7e34d Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-on: http://git-master/r/375012 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Initialize FECS explicitly on recoveryTerje Bergstrom2015-03-18
| | | | | | | | | Instead of calling second phase of PMU boot sequence, initialize FECS directly. Change-Id: I7f9de0c5ec42049033839d244979f3f3daabf317 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/410204
* gpu: nvgpu: Add gm20b fecs/gpccs bootloader supportTerje Bergstrom2015-03-18
| | | | | | | | | Add support for booting FECS and GPCCS via faster bootloader method. We leave this disabled until the bootloader binaries are checked in. Change-Id: I39df5d116f7a33486407518c743638b01923970d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/413005
* gpu: nvgpu: Use old ctxsw boot method on gm20bTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Boot FECS/GPCCS with old method on gm20b. We don't yet have bootloader for it. Change-Id: I09046960cd86b0402d3ea2cd8e4c92597766fa10 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/412604 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: Prune redundant cache maintenanceTerje Bergstrom2015-03-18
| | | | | | | | | | | | Remove redundant cache maintenance operations. Instance blocks and graphics context buffers are uncached, so they do not need any cache maintenance. Bug 1421824 Change-Id: Ie0be67bf0be493d9ec9e6f8226f2f9359cba9f54 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/406948
* gpu: nvgpu: Always initialize system vmTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | PMU, FECS and GPCCS use the same address space. We used to initialize the address space only if PMU is enabled. Create the system address space always. FECS and GPCCS used to have slower bit bang and faster DMA method for loading ucode. Slower method is needed when FECS and GPCCS do not have an address space. Remove the slower method as not anymore needed. Change-Id: I155619741ecc36aa6bf13a9c1ccb03c7c1330f0a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/406771
* gpu: nvgpu: gk20a: minor fixesKen Adams2015-03-18
| | | | | | | | | fixes one use of unitialized var renames a register to make it match dev_* file. Change-Id: Iafba659bbf2df509e0b494b2c5dab3819bf650ef Signed-off-by: Ken Adams <kadams@nvidia.com> Reviewed-on: http://git-master/r/394792
* gpu: nvgpu: Do not wait for FE idle on linsimTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Waiting for FE idle hangs on simulation, so skip it. Change-Id: I4f49eab725fcf2eb0b8340040a79731e16a1a0a0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/394053 Reviewed-on: http://git-master/r/396374 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
* video: tegra: host: gm20b: Implement gr opsTerje Bergstrom2015-03-18
| | | | | | | | | | | Implement gm20b specific gr ops. Bug 1387211 Change-Id: I4523311f1c155ba2d3403dcf222769f6817b2450 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/362415 Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
* video: tegra: host: gk20a: add class perf settingsRandy Spurlock2015-03-18
| | | | | | | | | | | | | | | | | Add a place to edit context-switched perf settings based upon class. Disable tex-lock as the first of such for compute. Bug 1409041 Change-Id: I5317a2a2e5f855661a1400b42f69211d16ae0c1d Signed-off-by: Randy Spurlock <rspurlock@nvidia.com> Reviewed-on: http://git-master/r/405908 (cherry picked from commit 250e149be35ecb8893dcef053ec44ffea86c302a) Reviewed-on: http://git-master/r/407094 (cherry picked from commit 54337c08cbf6c2c6b5c929c1be24e87165d9d946) Reviewed-on: http://git-master/r/408837 Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com> Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
* gpu: nvgpu: gk20a: add fecs error intr handlerDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | Add handler gk20a_gr_handle_fecs_error() in case we have pending fecs error interrupt And clear this interrupt after handling. Also, in gk20a_gr_handle_fecs_error(), for now just print the contents of NV_PGRAPH_FECS_INTR and clear it Bug 1495957 Change-Id: Ie7f70c84ec76ab698141646cd683584c4501e3e0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/402874 (cherry picked from commit a29f219c57d65a06f6dae8086f19fa1af94d95bd) Reviewed-on: http://git-master/r/403587 (cherry picked from commit e65ebebd0d4d5c3dbb6fa454dd51c383ea13d715) Reviewed-on: http://git-master/r/411160 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* video: tegra: gk20a: Disable gfx before save zbcSantosh Katvate2015-03-18
| | | | | | | | | | | | | | | | | | | This change disables gr engine before calling into pmu for saving zbc and re-enables once it is finished. Looks like NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_TIMEOUT error during access of NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE happens because of active concurrent memory traffic. Bug 1489850 Change-Id: I60eacd718480a296f5a46438e18a519c7457f58a Signed-off-by: Santosh Katvate <skatvate@nvidia.com> Reviewed-on: http://git-master/r/398398 GVS: Gerrit_Virtual_Submit (cherry picked from commit 42931088a3a1944359be61ebe39c646b41f73ee6) Reviewed-on: http://git-master/r/402779 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: Make trigger mmu fault GPU specificTerje Bergstrom2015-03-18
| | | | | | | | | | | Add abstraction for triggering fake MMU fault, and a gk20a implementation. Also adds recovery to FE hardware warning exception to make testing easier. Bug 1495967 Change-Id: I6703cff37900a4c4592023423f9c0b31a8928db2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* video: tegra: host: fix the bundle corruptionKevin Huang2015-03-18
| | | | | | | | | | | | | | Wait for FE idle between SW bundles. Bug 1477234 Bug 1486347 Bug 1485069 Change-Id: I5181b1240fff73cfecd07aa3e54076cde800ea00 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/391591 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add NVIDIA GPU DriverArto Merilainen2015-03-18
This patch moves the NVIDIA GPU driver to a new location. Bug 1482562 Change-Id: I24293810b9d0f1504fd9be00135e21dad656ccb6 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/383722 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 13:15:48 -0400