| Commit message (Collapse) | Author | Age |
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It'll allow the function to use fixed mapping.
Jira VQRM-2982
Change-Id: I98159c5b199ce1854b1b40704392237cadb71ef2
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1660225
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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fault_ch is needed by rm-server to send the notification to guest VM.
rm-server is going to use gr sources from linux
Jira VQRM-2982
Change-Id: Ifb6e8a9630a471d07b89ffaa7f2ceb309220fd21
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1661665
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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ctxsw disable could be called recursively for RM server. Suspend
contexts disables ctxsw at the beginning, then call tsg disable and
preempt. If preempt timeout happens, it goes to recovery path, which
will try to disable ctxsw again. More details on Bug 200331110.
Jira VQRM-2982
Change-Id: I4659c842ae73ed59be51ae65b25366f24abcaf22
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1671716
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This reverts commit 848af2ce6de6140323a6ffe3075bf8021e119434.
This is a revert of a revert, etc, etc. It re-enables IO coherence again.
JIRA EVLR-2333
Change-Id: Ibf97dce2f892e48a1200a06cd38a1c5d9603be04
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1669722
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The vserver variant for gr handle semaphore pending needs different
functionality to send interrupt to VM. Add HAL operation to allow
overriding vserver usecase.
Jira VQRM-2982
Change-Id: I5fee5a491c6e54344f9da477eaf5881c50335bbc
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1658298
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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RM Server will need to set specific HAL op and notify vgpu client.
Jira VQRM-2982
Change-Id: I679565831635ff3fadf0bdc1af5fd7a8679b6fdd
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1660226
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fixed vsrv link errors for gr unification.
Jira VQRM-2982
Change-Id: Icd46792191f1a9aaefbf86d2f3c0b4d5bce2384e
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1664706
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The vserver variant for gr post event id needs different
functionality to send interrupt to VM. Add HAL operation
to allow overriding vserver usecase.
Jira VQRM-2982
Change-Id: I915d089ef751023968c1e8ab181c21afeec997a5
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1658382
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The vserver variant for gr handle notify pending needs different
functionality to send interrupt to VM. Add HAL operation to allow
overriding vserver usecase.
Jira VQRM-2982
Change-Id: I4cb88d4d769a5d5cb98a4ee6ac3fbb74245cb5f2
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1658255
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The vserver variant for gr set error notifier needs different
functionality to send interrupt to VM. Add HAL operation to
allow overriding vserver usecase.
Jira VQRM-2982
Change-Id: Ia445a27112bb6c5587dbb81100a9dafe5875b338
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1657830
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Check these conditions for fecs arbiter idle:
1. Wait for gr_fecs_arb_ctx_cmd to idle
2. Wait for gr_fecs_ctxsw_status_1:arb_busy to idle
Just waiting for condition 1, only guarantees dispatching
of command but not completion of work.
Bug 2056266
Change-Id: I3fcbdb9cda91fee0ff345a24bf23ba7dabf268d0
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1667550
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This is to resolve memory leak after modifying
tpc_fs_mask sysfs which sets gr.sw_ready to false and
forces gr to re-initialize.
echo 1 > /sys/devices/gpu.0/force_idle
echo 5 > /sys/devices/gpu.0/tpc_fs_mask
echo 0 > /sys/devices/gpu.0/force_idle
Bug 200393029
Change-Id: I76299f53fc87823071c672ec682c3eb51f72f513
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1666018
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This reverts commit 89fbf39a05483917c0a9f3453fd94c724bc37375.
Bug 2075315
Change-Id: Id34a0376be5160b164931926ec600f77edf69667
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1668487
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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This reverts commit 5a35a95654d561fce09a3b9abf6b82bb7a29d74b.
JIRA EVLR-2333
Change-Id: I923c32496c343d39d34f6d406c38a9f6ce7dc6e0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1667167
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Bug 200393029
Change-Id: Ic2946958e34bcb9247179fcf2e8735c822155cce
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665338
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
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Also revert other changes related to IO coherence. This may be the
culprit in a recent dev-kernel lockdown.
Bug 2070609
Change-Id: Ida178aef161fadbc6db9512521ea51c702c1564b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665914
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srikar Srimath Tirumala <srikars@nvidia.com>
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When using a coherent DMA API wee must make sure to program
any aperture fields with the coherent aperture setting. To
do this the nvgpu_aperture_mask() function was modified to
take a third aperture mask argument, a coherent setting, so
that code can use this function to generate coherent aperture
settings.
The aperture choice is some what tricky: the default version
of this function uses the state of the DMA API to determine
what aperture to use for SYSMEM: either coherent or
non-coherent internally. Thus a kernel user need only specify
the normal nvgpu_mem struct and the correct mask should be
chosen. Due to many uses of nvgpu_mem structs not created
directly from the DMA API wrapper it's easier to translate
SYSMEM to SYSMEM_COH after creation.
However, the GMMU mapping code, will encounter buffers from
userspace with difference coerency attributes than the DMA
API. Thus the __nvgpu_aperture_mask() really respects the
aperture setting passed in regardless of the DMA API state.
This aperture setting is pulled from NVGPU_VM_MAP_IO_COHERENT
since this is either passed in from userspace or set by the
kernel when using coherent DMA. The aperture field in attrs
is upgraded to coh if this flag is set.
This change also adds a coherent sysmem mask everywhere that
it can. There's a couple places that do not have a coherent
register field defined yet. These need to eventually be
defined and added.
Lastly the aperture mask code has been mvoed from the Linux
vm.c code to the general vm.c code since this function has
no Linux dependencies.
Note: depends on https://git-master.nvidia.com/r/1664536 for
new register fields.
JIRA EVLR-2333
Change-Id: I4b347911ecb7c511738563fe6c34d0e6aa380d71
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1655220
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Miscellaneous fixes for the sched code:
1. Make sure get_addr() on an SGL respects the use phys flag since
the runlist needs physical addresses when NVLINK is in use.
2. Ensure the runlist is contiguous. Since the runlist memory is
not virtually addressed the buffer must be physically contiguous.
3. Use all 64 bits of the runlist address in the runlist base addr
register (and related fields).
JIRA EVLR-2333
Change-Id: Id4fd5ba4665d3e35ff1d6ca78dea6b58894a9a9a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1654667
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Tested-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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There are numerous places where variables are assigned to but then
never used. This patch cleans up all these unused variables and
in some cases simplifies surrounding logic.
Also delete unused header includes and add necessary header includes.
JIRA NVGPU-525
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Change-Id: Ice9ec2a0e97f262d0dcfebe22f83208dbea569d9
Reviewed-on: https://git-master.nvidia.com/r/1662548
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We don't have compression enabled on GV100 so it does not make sense
to allocate a huge CBC for this device.
Change-Id: I0ff908571f28c2ba6f439b0989398bf68dce16f9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1655279
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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To prevent deadlock while allocating VPR in nvgpu, allocate all the
needed VPR memory at probe time and use an internal allocator to
hand out space for VPR buffers.
Change-Id: I584b9a0f746d5d1dec021cdfbd6f26b4b92e4412
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1655324
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-pd, scc, ds, ssync, mme and sked exceptions are
enabled. This will be useful for debugging
-Handle enabled interrupts
-Add gr ops to handle ssync hww. For legacy
chips, ssync hww_esr register is gpcs_ppcs_ssync_hww_esr.
Since ssync hww is not enabled on legacy chips, added
ssync hww exception handling for volta only.
Change-Id: I63ba2eb51fa82e74832df26ee4cf3546458e5669
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644751
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This will be used to enable fecs interrupts per
chip.
Change-Id: Id99412ca1a9c4caad999c3458b0e9701515db4b9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1642554
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Data can be speculatively loaded from memory and stay in cache even
when bound check fails. This can lead to unintended information
disclosure via side-channel analysis.
To mitigate this problem insert a speculation barrier.
bug 2039126
CVE-2017-5753
Change-Id: Ib6c4b2f99b85af3119cce3882fe35ab47509c76f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640500
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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When we detect a timeout waiting for ctxsw ucode method to complete,
we print an error. The error does not detail the event we are waiting
which makes debugging difficult. Add the missing mailbox id and value
to the error.
Bug 2049965
Change-Id: I45204a2d6f1f39919a0133b1e0867213e1a5b671
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1643709
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move graphics context ownership to TSG instead of channel. Combine
channel_ctx_gk20a and gr_ctx_desc to one structure, because the split
between them was arbitrary. Move context header to be property of
channel.
Bug 1842197
Change-Id: I410e3262f80b318d8528bcbec270b63a2d8d2ff9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639532
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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gp10b version of free_gr_ctx was created to keep gp10b source code
changes out from the mainline. gp10b was merged back to mainline a
while ago, so this separation is no longer needed. Merge the two
variants.
Change-Id: I954b3b677e98e4248f95641ea22e0def4e583c66
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1635127
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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On gv11b we can have multiple SMs per TPC. Add sm_per_tpc in
vgpu constants to properly dimension the virtual SM to TPC/GPC
mapping in virtualization case.
Use TEGRA_VGPU_CMD_GET_SMS_MAPPING to query current mapping.
Bug 2039676
Change-Id: I817be18f9a28cfb9bd8af207d7d6341a2ec3994b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631203
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Committing buffer addresses only writes to the memory. There's no
need to disable ELPG for the duration, so drop the ELPG protection.
Change-Id: I8d8d08506387197e4737e0311df4a20085496056
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631149
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Remove compute optimization specific to gk20a. We do not support
gk20a anymore.
Change-Id: Ibd548eee8d891a667f28a451d586fcfaac7f026a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631144
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Remove support for events for bare channels. All users have already
moved to TSGs and TSG events.
Bug 1842197
Change-Id: Ib3ff68134ad9515ee761d0f0e19a3150a0b744ab
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1618906
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Check the availability of ecc units by checking
relevant ecc fuse and fuse overrides.
During gpu boot, initialize ecc units by scrubbing
individual ecc units available. ECC initialization
should be done before gr initialization.
Following ecc units are scrubbed:
SM LRF
SM L1 DATA
SM L1 TAG
SM CBU
SM ICACHE
Bug 200339497
Change-Id: I54bf8cc1fce639a9993bf80984dafc28dca0dba3
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612734
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In __gr_gk20a_exec_ctx_ops(), we directly access linux specific pages to check
if memory is allocated or not
Since we need to remove this linux specific dependency from common code,
use common API nvgpu_mem_is_valid() to check if memory is allocated or not
Jira NVGPU-448
Change-Id: Iad62482ad1c0dfad3b96c6c125c2641bbe6ea596
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612445
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In gr_gk20a_init_access_map(), we declare num_entries as "unsigned int"
But this variable is implicitly type casted into "int" while calling subsequent
functions
Hence explicitly declare it as type "int"
Also declare variable "w" as "int" too since we use it to compare against
num_entries
Jira NVGPU-446
Change-Id: I289da6951db0a9ed6b8d6bcb3ee4f6071a4ddaf0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612444
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Use nvgpu specific list APIs nvgpu_list_for_each_entry() instead of calling
Linux specific list APIs list_for_each_entry()
Jira NVGPU-444
Change-Id: I3c1fd495ed9e8bebab1f23b6769944373b46059b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612442
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Remove linux specific #include "common/linux/os_linux.h" from common source
files gr_gk20a.c/gr_gm20b.c/gr_gp10b.c
Remove use of ZERO_OR_NULL_PTR() and simply check if pointer is NULL or not
Jira NVGPU-405
Change-Id: I663fe298cc720f0b0e22beaa05697b18b375a204
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1607233
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For gv11b, configured gfx preemption wfi timeout in usec.
Set timeout unit as usec in gr_gv11b_init_preemption_state.
Used default timeout as 1msec and this timeout value can
be modified through sysfs node:
/sys/devices/gpu.0/gfxp_wfi_timeout_count
For gp10b:
gfxp_wfi_timeout_count is in syclk cycles
For gv11b:
gfxp_wfi_timeout_count is in usec
Bug 2003668
Change-Id: I68d52ce996a83df90b8b3a8164debb07e5cb370f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599658
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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With recent rework in nvgpu most of the <uapi/linux/nvgpu.h> includes
are not needed so remove them
Remove use of NVGPU_DBG_GPU_REG_OP_* in gk20a/gr_gk20a.c and use common
definition instead
Remove use of NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE in
gp10b/fifo_gp10b.c by defining new common flag
NVGPU_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE and then parsing it in API
nvgpu_gpfifo_user_flags_to_common_flags()
Jira NVGPU-363
Change-Id: I8e653275ea3f443f24be7284d54f2115636aba3f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606108
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We initialize gr->max_comptag_mem in common code and with a global variable
declared in <linux/mm.h>
Move this linux specific dependency to linux specific files i.e.
initialize gr->max_comptag_mem during linux specific probe functions
Jira NVGPU-414
Change-Id: I9415938bf1288b24950ba7ecc71abee3162dae64
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606195
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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All the linux specific error_notifier codes are defined in linux specific
header file <uapi/linux/nvgpu.h> and used in all the common driver
But since they are defined in linux specific file, we need to move all the
uses of those error_notifiers in linux specific code only
Hence define new error_notifiers in include/nvgpu/error_notifier.h and
use them in the common code
Add new API nvgpu_error_notifier_to_channel_notifier() to convert common
error_notifier of the form NVGPU_ERR_NOTIFIER_* to linux specific error
notifier of the form NVGPU_CHANNEL_*
Any future additions to error notifiers requires update to both the form
of error notifiers
Move all error notifier related metadata from channel_gk20a (common code)
to linux specific structure nvgpu_channel_linux
Update all accesses to this data from new structure instead of channel_gk20a
Move and rename below APIs to linux specific file and declare them
in error_notifier.h
nvgpu_set_error_notifier_locked()
nvgpu_set_error_notifier()
nvgpu_is_error_notifier_set()
Add below new API and use it in fifo_vgpu.c
nvgpu_set_error_notifier_if_empty()
Include <nvgpu/error_notifier.h> wherever new error_notifier codes are used
NVGPU-426
Change-Id: Iaa5bfc150e6e9ec17d797d445c2d6407afe9f4bd
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593361
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Use API nvgpu_mem_is_valid() to check if buffers are allocated or not
instead of directly accessing linux specific sg_table
Jira NVGPU-416
Change-Id: I83da79f4a57ec5a765f32c69bf76e708753e11fb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1604587
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This patch removes the dependency on the header file "uapi/linux/nvgpu.h"
for regops_gk20a.c. The original structure and definitions in the
uapi/linux/nvgpu.h is maintained for userspace libnvrm_gpu.h. The
following changes are made in this patch.
1) Defined common versions of the NVGPU_DBG_GPU_REG_OP* definitions inside
regops_gk20a.h.
2) Defined common version of struct nvgpu_dbg_gpu_reg_op inside
regops_gk20a.h naming it struct nvgpu_dbg_reg_op.
3) Constructed APIs to convert the NVGPU_DBG_GPU_REG_OP* definitions from
linux versions to common and vice versa.
4) Constructed APIs to convert from struct nvgpu_dbg_gpu_reg_op to
struct nvgpu_dbg_reg_op and vice versa.
5) The ioctl handler nvgpu_ioctl_channel_reg_ops first copies from
userspace into a local storage based on struct nvgpu_dbg_gpu_reg_op which
is copied into the struct nvgpu_dbg_reg_op using the APIs above and
after executing the regops handler passes the data back into userspace
by copying back data from struct nvgpu_dbg_reg_op to struct
nvgpu_dbg_gpu_reg_opi.
JIRA NVGPU-417
Change-Id: I23bad48d2967a629a6308c7484f3741a89db6537
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596972
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Add a translation layer to convert from the NVGPU_AS_* flags to
to new set of NVGPU_VM_MAP_* and NVGPU_VM_AREA_ALLOC_* flags.
This allows the common MM code to not depend on the UAPI header
defined for Linux.
In addition to this change a couple of other small changes were
made:
1. Deprecate, print a warning, and ignore usage of the
NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS flag.
2. Move the t19x IO coherence flag from the t19x UAPI header
to the regular UAPI header.
JIRA NVGPU-293
Change-Id: I146402b0e8617294374e63e78f8826c57cd3b291
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599802
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Add explicit #includes for <uapi/linux/nvgpu.h> for source code files
that depend on it.
JIRA NVGPU-259
Change-Id: I717d5f1493423fd3a7a34b6dd3380d33a9307a09
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596254
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Add update_patch_count parameter to ctx_patch_write_begin/end functions
If True, the main_image_patch_count register will be updated. Previously,
the patch count would be updated if the cpu_va for the graphics context
was non-NULL, but this only works for sysmem (cpu_va is always 0 for vidmem)
- Remove unused patch parameter for the commit_global_timeslice functions
JIRA ESRM-74
Bug 2012077
Change-Id: I35d0a9eb48669a227833bba1d2e63e9fe8fd8aa9
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594790
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In gr_gp10b_alloc_gr_ctx(), we use linux specific flags NVGPU_ALLOC_OBJ_FLAGS_*
Since common code should be independent of linux specific code, define new flags
NVGPU_OBJ_CTX_FLAGS_SUPPORT_* in common code and use them wherever needed
Linux code will parse the user flags and send appropriate flags to
g->ops.gr.alloc_obj_ctx()
Also remove use of NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO since this seems to be
deadcode anyways
Jira NVGPU-382
Change-Id: Id82efe0d46ddc3e2c063610025ea57f283bc3510
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594452
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Since NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL was made mandatory,
kernel does not need to know the details about the PTE kinds
anymore. Thus, we can remove the kind_gk20a.h header and the code
related to kind table setup, as well as simplify buffer mapping code
a bit.
Bug 1902982
Change-Id: Iaf798023c219a64fb0a84da09431c5ce4bc046eb
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560933
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This CL is as part of phased changes to support NO LSPMU
Changes done is to add missing can_elpg check
JIRA NVGPU-296
Change-Id: Ic4e5ebf208e08a0a9fce6b449f15a2e768281bb1
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1592629
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Move fuse override DT handling to Linux code. All the chip specific
fuse override functions did the same thing, so delete the HAL and
call the same function to read the DT overrides on all chips.
Also remove the fuse override functionality from dGPU. There are no
DT entries for PCIe devices, so it would've failed anyway.
JIRA NVGPU-259
Change-Id: Iba64a5d53bf4eb94198c0408a462620efc2ddde4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593687
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Make NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL mandatory for all map
IOCTLs. We'll clean up the legacy kernel code in subsequent patches.
Remove support for NVGPU_AS_IOCTL_MAP_BUFFER. It has been superseded
by NVGPU_AS_IOCTL_MAP_BUFFER_EX.
Remove legacy definitions to nvgpu_map_buffer_args and the related
flags, and update the in-kernel map calls accordingly by switching to
the newer definitions.
Bug 1902982
Change-Id: Ie9a7f02b8d5d0ec7c3722c4481afab6d39b4fbd0
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560932
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