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path: root/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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* gpu: nvgpu: add safe channel id lookupKonsta Holtta2019-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add gk20a_channel_from_id() to retrieve a channel, given a raw channel ID, with a reference taken (or NULL if the channel was dead). This makes it harder to mistakenly use a channel that's dead and thus uncovers bugs sooner. Convert code to use the new lookup when applicable; work remains to convert complex uses where a ref should have been taken but hasn't. The channel ID is also validated against FIFO_INVAL_CHANNEL_ID; NULL is returned for such IDs. This is often useful and does not hurt when unnecessary. However, this does not prevent the case where a channel would be closed and reopened again when someone would hold a stale channel number. In all such conditions the caller should hold a reference already. The only conditions where a channel can be safely looked up by an id and used without taking a ref are when initializing or deinitializing the list of channels. Jira NVGPU-1460 Change-Id: I0a30968d17c1e0784d315a676bbe69c03a73481c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1955400 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 7df3d587502c2de997dfbe8ea8ddc114d0a0481e in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2008515 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: channel: make chid u32Philip Elcan2019-02-05
| | | | | | | | | | | | | | | | | | The chid member of the channel_gk20a struct was being used as a unsigned value. By being declared as an int, it was causing MISRA 10.3 violations for implicit assignment of different types. JIRA NVGPU-647 Change-Id: I7477fad6f0c837cf7ede1dba803158b1dda717af Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1918470 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 1c7bb9b538200a11aa3ef31d72038d8ba820dfca in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2008514 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: make tsgid a consistent typePhilip Elcan2019-02-05
| | | | | | | | | | | | | | | | | | Different units were declaring tsgid as int or u32. This makes everyone use u32. This change resolves MISRA 10.3 violations for implicit assingment to different types. JIRA NVGPU-647 Change-Id: I78660e737acb0dad76dd538e5dd37f4527cf5acd Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1918469 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit f5cac144a04a3ef83762ecb2e3f405196beffd68 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2008513 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle timestamp buffer full ctxsw_intr0Seema Khowala2018-12-29
| | | | | | | | | | | | | | | | | | | | | | | | If enabled, fecs trace updating happens from ucode side even when there is no fecs trace dumper application to consume it. Due to this, trace buffer will get eventually full and ucode will trigger ctxsw_intr0. Reset fecs_trace buffer to handle timestamp buffer full ctxsw_intr0. Bug 2361571 Bug 200472922 Change-Id: Ia26a17635fc6bd6e8663b8af983acc91839ecfcd Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1965370 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> (cherry picked from commit 790ba095543b33f4cc3a145559ad31a1e9f99d98) Reviewed-on: https://git-master.nvidia.com/r/1979746 GVS: Gerrit_Virtual_Submit Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
* gpu: nvgpu: add handling for ctxsw_intr0Seema Khowala2018-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | ctxsw_intr0 is triggered by ucode even if it is not enabled by driver. Add handling for processing ctxsw_intr0. fecs mailbox(6) is used to report fecs/gpccs misc error codes. Also dump falcon stats for unhandled fecs intr. Bug 2361571 Bug 200472922 Change-Id: Iefb3c0d46ad1d08db07fd3c08cff91a77835908c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1966984 (cherry picked from commit 2c379cad0f6a01d07102898b362735a574f3aea8 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/1979745 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: update all ctx headers in the tsg when update hwpm modeRichard Zhao2018-10-11
| | | | | | | | | | | | | | | | | | | | FECS could use any ctx headers for context switch, so needs to update all ctx headers in the same tsg with hwpm buffer address. Bug 2404093 Bug 200454109 Change-Id: I99e74cd8c768c06c3d215779db899a1318522db0 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1917756 (cherry picked from commit f447a8d279b0d0abc8e2d3eb6f0596ea5cd87cbf) Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1920608 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: fix update hwpm ctxsw mode"Richard Zhao2018-10-11
| | | | | | | | | | | | | | | | | | | | | The fix is incorrect. hwpm ctxsw mode should always in gr ctx. This reverts commit 8f30251c67811834f9d93b50ce3e97fe3aa18051. Bug 2404093 Bug 200454109 Change-Id: I8fae2c379b051a3f48fe9e886e3b2348bb94b935 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1917755 (cherry picked from commit 70248d531479fac7946ae296f926518fcc5677a0) Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1920607 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add MC APIs for reset masksTerje Bergstrom2018-09-27
| | | | | | | | | | | | | | Add API for querying reset mask corresponding to a unit. The reset masks need to be read from MC HW header, and we do not want all units to access Mc HW headers themselves. JIRA NVGPU-954 Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1823384 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix update hwpm ctxsw modeVaibhav Kachore2018-09-27
| | | | | | | | | | | | | | | | | | - Depending on main context or subcontext, ctxheader and gr_mem should be updated with pm mode and buffer addresss accordingly Bug 2404093 Change-Id: Iba16c762c09b2a420570d4f528205e258ff27e8f Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1849396 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Do not disable GRFIFO access when resetting GRTerje Bergstrom2018-09-21
| | | | | | | | | | | | | | | | | | gk20a_init_gr_prepare() is called only when initializing GR from reset. In those cases there is no need to disable GRFIFO access. Remove the corresponding code. It also gets rid of one extra dependency to MC registers. JIRA NVGPU-954 Change-Id: I935e65f236e0f29ab224787d20e017d8c67e69e2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822309 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gk20a: gr: MISRA 10.1 & 14.4 boolean fixesAmulya2018-09-19
| | | | | | | | | | | | | | | | | | | | Fix violations where a variable of type non-boolean is used as a boolean in nvgpu/gk20a/gr_gk20a.c Changed instances of BIT() to BIT32() in nvgpu/gk20a/gr_pri_gk20a.h JIRA NVGPU-646 JIRA NVGPU-1019 Change-Id: I1784f8509cc87d65ac1c8c95796a4c8876626b48 Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1811925 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: dump falcon stats for fecs watchdogSeema Khowala2018-09-14
| | | | | | | | | | | | | | | After fecs watchdog gets triggered, system will not do anything useful as it cannot context switch. Dumping falcon stats will help debug the issue since s/w is not triggering recovery. Bug 2113657 Change-Id: I03ccd5ad7c03daac0581775dc615174cc0e77328 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812720 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Wait for empty always has GR enabledTerje Bergstrom2018-09-13
| | | | | | | | | | | | | | | | | | Whenever wait for empty HAL is called, GR is out of reset. Check for GR being out of reset was adding an extra dependency to MC, so just remove that code. JIRA NVGPU-964 Change-Id: Ic6d607fd2e29359a67896973517d8de6542029e9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813522 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move programming of debug page to FBTerje Bergstrom2018-09-10
| | | | | | | | | | | | | | | Debug page was allocated and programmed to HUB MMU in GR code. This introduces a dependency from GR to FB and is anyway the wrong place. Move the code to allocate memory to generic MM code, and the code to program the addresses to FB. Change-Id: Ib6d3c96efde6794cf5e8cd4c908525c85b57c233 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801423 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Return gr_ctx_resident from NVGPU_DBG_GPU_IOCTL_REG_OPSAnup Mahindre2018-09-09
| | | | | | | | | | | | | | | | | | NVGPU_DBG_GPU_IOCTL_REG_OPS currently doesn't return if the ctx was resident in engine or not. Regops are broken down into batches of 128 and each batch is executed together. Since there only 32 bits were available in IOCTL args, returning is ctx was resident isn't possible for all batches. Hence return if the ctx was resident for the first batch. Bug 200445575 Change-Id: Iff950be25893de0afadd523d4ea04842a8ddf2af Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812975 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix nvgpu_readl MISRA 17.7 violationsNicolas Benech2018-09-07
| | | | | | | | | | | | | | | | | MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fix for calls to nvgpu_readl. JIRA NVGPU-677 Change-Id: I432197cca67a10281dfe407aa9ce2dd8120030f0 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807528 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gk20a: gr: Fix MISRA 15.6 violationsSrirangan2018-09-06
| | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces by introducing the braces. JIRA NVGPU-671 Change-Id: Ie4bd8bffdafe6321e35394558dc9559f9c2d05c2 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797689 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move channel header to commonKonsta Holtta2018-09-05
| | | | | | | | | | | | | channel_gk20a is clear from chip specifics and from most dependencies, so move it under the common directory. Jira NVGPU-967 Change-Id: I41f2160b96d4ec84064288ecc22bb360e82352df Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810578 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix mutex MISRA 17.7 violationsNicolas Benech2018-09-05
| | | | | | | | | | | | | | | | | | MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fix for calls to nvgpu_mutex_init and improves related error handling. JIRA NVGPU-677 Change-Id: I609fa138520cc7ccfdd5aa0e7fd28c8ca0b3a21c Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805598 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix various MISRA 10.1 bool violationsScott Long2018-09-04
| | | | | | | | | | | | | | | | | | | | | | This patch corrects a handful of MISRA 10.1 violations involving illegal arithmetic operations (e.g. bitwise OR) on boolean values: * fix to status handling in regops validation code * fix to debugger event handling in gr code * fix to entries_left tracking in runlist construct code * fix to verbose channel dumping and reset tracking in fifo code JIRA NVGPU-650 Change-Id: I3c3d9123b5a0e08fc936d0e63d51de99fc310ade Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810957 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove ctx header desc typeKonsta Holtta2018-08-31
| | | | | | | | | | | | | | The graphics subctx header object is nothing but memory. Drop the dependency to gr header file in the channel header file and substitute struct nvgpu_mem for struct ctx_header_desc. Jira NVGPU-967 Change-Id: Ic3976391016c42d2ada4aac3e0851a1222244ce9 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807370 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix zbc MISRA 10.1 violationsScott Long2018-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The gr_gk20a_add_zbc() routine returns a signed error (errno) status value. Current callers of this function use a bitwise OR to collect the returned error status values to generate a single value to return. Bitwise OR on signed status values is flagged as a violation of MISRA Rule 10.1 (not to mention that in this case it potentially results in a garbage return value). To eliminate such violations this change modifies the following routines to fail immediately on the first error from a call to gr_gk20a_add_zbc(): * gr_gk20a_load_zbc_default_table() * gr_gv11b_load_stencil_default_tbl() JIRA NVGPU-650 Change-Id: If733c1bb0e05943ff5d0355de729133c89233583 Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805501 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: invoke calls to methods in pmu_gk20a.h via HALDebarshi Dutta2018-08-29
| | | | | | | | | | | | | | | | | | | | In nvgpu repository, we have multiple accesses to methods in pmu_gk20a.h which have register accesses. Instead of directly invoking these methods, these are now called via HALs. Some common methods such as pmu_wait_message_cond which donot have any register accesses are moved to pmu_ipc.c and the method declarations are moved to pmu.h. Also, changed gm20b_pmu_dbg to nvgpu_dbg_pmu all across the code base. This would remove all indirect dependencies via gk20a.h into pmu_gk20a.h. As a result pmu_gk20a.h is now removed from gk20a.h JIRA-597 Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1804283 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Read sm error ioctl support for tsgVinod G2018-08-25
| | | | | | | | | | | | | | | | | | | | | | | | | Add READ_SM_ERROR IOCTL support to TSG level. Moved the struct to save the sm_error details from gr to tsg as the sm_error support is context based, not global. Also corrected MISRA 21.1 error in header file. nvgpu_dbg_gpu_ioctl_write_single_sm_error_state and nvgpu_dbg_gpu_ioctl_read_single_sm_error_state functions are modified to use the tsg struct nvgpu_tsg_sm_error_state. Bug 200412642 Change-Id: I9e334b059078a4bb0e360b945444cc4bf1cc56ec Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1794856 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: switch gk20a nonstall ops to #definesScott Long2018-08-22
| | | | | | | | | | | | | | | | | | | | Fix MISRA rule 10.1 violations involving gk20a_nonstall_ops enums by replacing them with with corresponding #defines. Because these values can be used in expressions that require unsigned values (e.g. bitwise OR) we cannot use enums. The g->ce2.isr_nonstall() function was previously returning an int that was a combination of gk20a_nonstall_ops enum bits which led to the violations. JIRA NVGPU-650 Change-Id: I6210aacec8829b3c8d339c5fe3db2f3069c67406 Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1796242 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Deprecate NVGPU_GPU_IOCTL_INVAL_ICACHEAnup Mahindre2018-08-17
| | | | | | | | | | | | | | | | | Deprecate NVGPU_GPU_IOCTL_INVAL_ICACHE as it is unused and has a broken implementation. Bug 200439908 Change-Id: Iab6f08cf3dd4853ba6c95cbc8443331bf505e514 Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1800797 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move ltc HAL to commonTerje Bergstrom2018-08-16
| | | | | | | | | | | | Move implementation of ltc HAL to common/ltc. JIRA NVGPU-956 Change-Id: Id78d74e8612d7dacfb8d322d491abecd798e42b5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1798461 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move therm HAL to commonTerje Bergstrom2018-08-14
| | | | | | | | | | | | | | | Move implementation of therm HAL to common/therm. ELCG and BLCG code was embedded in gr HAL, so moved that code to therm. Bump gk20a code to gm20b. JIRA NVGPU-955 Change-Id: I9b03e52f2832d3a1d89071a577e8ce106aaf603b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: MISRA 10.4 enum fixesAmulya2018-08-14
| | | | | | | | | | | | | | | | MISRA rule-10.4 only allows arithmetic conversions on operands of the same essential type category. Fix violations where an arithmetic conversion is performed on enum and non-enum types. JIRA NVGPU-993 Change-Id: I5391bb670d68982e0b5af6600995f70fe0cb2ad3 Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1792852 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove utils.h from gk20a.hVinod G2018-08-10
| | | | | | | | | | | | | | | | Removed the utils.h include from gk20a.h utils.h is included in those files which make use of the macros in utils.h JIRA NVGPU-1005 Change-Id: Ifb41da58db6ff8682fa6b5dfdd8eda11a751fcac Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1785952 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix MISRA Rule 10.1 issues in gr reset codeScott Long2018-08-08
| | | | | | | | | | | | | | | | Fix MISRA rule 10.1 violations involving need_reset var in gk20a_gr_isr(). Changed type to bool and set it to true any time one of the pending condition checks returns non-zero. JIRA NVGPU-650 Change-Id: I2f87b68d455345080f7b4c68cacf515e074c671a Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1793633 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gk20a: Fix MISRA 15.6 violationsSrirangan2018-08-06
| | | | | | | | | | | | | | This fixes errors due to single statement loop bodies without braces, which is part of Rule 15.6 of MISRA. This patch covers in gpu/nvgpu/gk20a/ JIRA NVGPU-989 Change-Id: I2f422e9bc2b03229f4d2c3198613169ce5e7f3ee Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1791019 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix gpc_tpc_mask to use max_gpc_countRichard Zhao2018-08-06
| | | | | | | | | | | | | | | | | | gpc_tpc_mask uses gpc/tpc IDs directly read from fuse, so it needs to use max_gpc_count for any possible cases rather not gpc_count. Bug 2302005 Change-Id: I903ee3e0c10c4b329dd0d76c40d3516dc36ed303 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1790464 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gk20a: nvgpu: Remove io.h dependency from gk20a.hDebarshi Dutta2018-07-30
| | | | | | | | | | | | | | | | In the current code, gk20a.h includes io.h which gets directly included in a lot of other files. io.h contains methods which uses a struct gk20a as a parameter leading to a circular dependency between io.h and gk20a.h. This can be mitigated by removing io.h from gk20a.h as part of larger effort to moving gk20a.h to nvgpu/gk20a.h JIRA NVGPU-597 Change-Id: I93e504fa9371b88152737b342a75580c65e8f712 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1787316 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Rearrange the static inline codeVinod G2018-07-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to avoid the circular dependencies, rearrange the static inline functions from gk20a.h file. Moved gk20a_gr_flush_channel_tlb function to gr_gk20a.c and removed the #include gr_gk20a.h from gk20a.h Added a helper function utils.h to move all generic static inline functions which have no reference to gpu related structures. ptimer related functions are moved to ptimer.h Implementations for as and pmu are moved to corresponding files. JIRA NVGPU-624 Change-Id: I4e956326e773ba037bf3a1696cc4c462085dbbe5 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1781941 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rework ecc structure and sysfsRichard Zhao2018-07-19
| | | | | | | | | | | | | | | | | | | | | - create common file common/ecc.c which include common functions for add ecc counters and remove counters. - common code will create a list of all counter which make it easier to iterate all counters. - Add chip specific file for adding ecc counters. - add linux specific file os/linux/ecc_sysfs.c to export counters to sysfs. - remove obsolete code - MISRA violation for using snprintf is not solved, tracking with jira NVGPU-859 Jira NVGPUT-115 Change-Id: I1905c43c5c9b2b131199807533dee8e63ddc12f4 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1763536 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Initialize hwpm perfmons (engine_sel)Vaibhav Kachore2018-07-10
| | | | | | | | | | | | | | - For Mode-E ctxsw it is required that engine_sel is set to 0xFFFFFFFF. - Default 0 is a valid signal and causes problems. Bug 2106999 Change-Id: I5cdb4441a8e6d7e8133c31a9e361b54611dd2995 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770755 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable HWPM Mode-E context switchVaibhav Kachore2018-07-10
| | | | | | | | | | | | | | | | | | - Write new pm mode to context buffer header. Ucode use this mode to enable mode-e context switch. This is Mode-B context switch of PMs with Mode-E streamout on one context. If this mode is set, Ucode makes sure that Mode-E pipe (perfmons, routers, pma) is idle before it context switches PMs. - This allows us to collect counters in a secure way (i.e. on context basis) with stream out. Bug 2106999 Change-Id: I5a7435f09d1bf053ca428e538b0a57f3a175ac37 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1760366 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix ppc broadcast address splitDeepak Nibade2018-07-05
| | | | | | | | | | | | | | | | | | | | | | In gr_gk20a_split_ppc_broadcast_addr() we convert a PPC broadcast address to its corresponding unicast address list But we consider gr.pe_count_per_gpc instead of actual number of PPCs and that leads to generating incorrect list of addresses Fix this by using gr.gpc_ppc_count[gpc_num] which gives correct number of PPC count Jira NVGPUT-117 Change-Id: If7e7c19244b90cb3c405dcba4ae7a86c782972f7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1767838 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to get offset in gpccs segmentDeepak Nibade2018-07-05
| | | | | | | | | | | | | | | | | | | | | | In gr_gk20a_find_priv_offset_in_buffer() we right now calculate offset of a register in gpccs segment based on register address type Separate out sequence to find offset in gpccs segment and move it to new API gr_gk20a_get_offset_in_gpccs_segment() Introduce new HAL gops.gr.get_offset_in_gpccs_segment() and set above API to this HAL Call HAL from gr_gk20a_find_priv_offset_in_buffer() instead of calling direct API Jira NVGPUT-118 Change-Id: I0df798456cf63e3c3a43131f3c4ca7990b89ede0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761669 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove unnecessary nvgpu_memset callsKonsta Holtta2018-06-28
| | | | | | | | | | | | | | | | Some graphics context buffers are explicitly cleared to zero after allocation. That's not necessary because the allocator gives zero-initialized memory already, so remove the clears. Change-Id: I8f9913605801e35082762e7743762d97f88e1d12 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761578 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: don't mem_{begin,end}() for grKonsta Holtta2018-06-28
| | | | | | | | | | | | | | | | | | | | | Now that GR buffers always have a kernel mapping, remove the unnecessary calls to nvgpu_mem_begin() and nvgpu_mem_end() on these buffers: - global ctx buffer mem in gr - gr ctx mem in a tsg - patch ctx mem in a gr ctx - pm ctx mem in a gr ctx - ctx_header mem in a channel (subctx header) Change-Id: Id2a8ad108aef8db8b16dce5bae8003bbcd3b23e4 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1760599 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Do not use NO_KERNEL_MAPPING for GRTerje Bergstrom2018-06-20
| | | | | | | | | | | | | | | | With arm64 mapping buffers to CPU is free. Remove the use of NO_KERNEL_MAPPING. Change-Id: Ic99ca6b7f8c698e2d3cb1d61a821939798bb237b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1753709 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Lakshmanan M <lm@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add support for FECS VAVaibhav Kachore2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | - On t186, ucode expects physical address to be programmed for FECS trace buffer. - On t194, ucode expects GPU VA to be programmed for FECS trace buffer. This patch adds extra support to handle this change for linux native. - Increase the size of FECS trace buffer (as few entries were getting dropped due to overflow of FECS trace buffer.) - This moves FECS trace buffer handling in global context buffer. - This adds extra check for updation of mailbox1 register. (Bug 200417403) EVLR-2077 Change-Id: I7c3324ce9341976a1375e0afe6c53c424a053723 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1536028 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: correct calculation of sm_id for .record_sm_error_stateRichard Zhao2018-06-14
| | | | | | | | | | | | | | | | | | Starting with Volta, one TPC could have more than 1 SMs. So .record_sm_error_state needs to have sm number as parameter. Logic tpc id should be read from gr_gpc0_gpm_pd_sm_id_r. Let the function return logical sm_id. RM server will need it to nofify client. Jira EVLR-2643 Bug 200405202 Change-Id: Iffaff05b89b1c5058616b8a6bf50dd73bd4e52f6 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1742165 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: export APIs to allocate/destroy context buffersDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | Export below APIs in gr_gk20a.h header gk20a_gr_alloc_ctx_buffer() gk20a_gr_destroy_ctx_buffer() Jira NVGPUT-27 Change-Id: Ia181a3f464ffbc9abe12963dd709cebee9e7dbc9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1743364 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs to allocate/map/commit global context buffersDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | | | Add below new HALs to allocate/map/commit global context buffers gops.gr.alloc_global_ctx_buffers() gops.gr.map_global_ctx_buffers() gops.gr.commit_global_ctx_buffers() Set these HALs for all the supported GPUs We right now re-use below APIs to set these HALs gr_gk20a_alloc_global_ctx_buffers() gr_gk20a_map_global_ctx_buffers() gr_gk20a_commit_global_ctx_buffers() Jira NVGPUT-27 Change-Id: I975a54e8d1716af057f982d543787748d35a256e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1743362 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move setting priv interrupt to priv_ringTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Registers to set priv interrupts are in priv_ring, but the code was in bus HAL. Move the code and related HALs to priv_ring instead. JIRA NVGPU-588 Change-Id: I708d11f77405dbba86586a0d1da42f65bcc1de9d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730889 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: initialze bundle64 stateDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | We receive bundle with address and 64 bit values from ucode on some platforms This patch adds the support to handle 64 bit values Add struct av64_gk20a to store an address and corresponding 64 bit value Add struct av64_list_gk20a to store count and list of av64_gk20a Add API alloc_av64_list_gk20a() to allocate the list that supports 64bit values In gr_gk20a_init_ctx_vars_fw(), if we see NETLIST_REGIONID_SW_BUNDLE64_INIT, load the bundle64 state into above local structures Add new HAL gops.gr.init_sw_bundle64() and call it from gk20a_init_sw_bundle() if defined Also load the bundle for simulation cases in gr_gk20a_init_ctx_vars_sim() Jira NVGPUT-96 Change-Id: I1ab7fb37ff91c5fbd968c93d714725b01fd4f59b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1736450 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix crash due to accessing incorrect TSG pointerDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_gr_isr(), we handle various errors including GPC/TPC errors. And then if BPT errors are pending we call gk20a_gr_post_bpt_events() at the end and pass channel pointer to it gk20a_gr_post_bpt_events() extracts TSG pointer based on ch->tsgid But in some race conditions it is possible that we clear the error and trigger recovery and as a result channel is unbounded from TSG and closed by user space before calling gk20a_gr_post_bpt_events() And in that case the code above results in getting incorrect TSG pointer and hence crashes as below Unable to handle kernel paging request at virtual address ffffff8012000c08 ... [<ffffff8008081f84>] el1_da+0x24/0xb4 [<ffffff80086e72e0>] gk20a_tsg_get_event_data_from_id+0x30/0xb0 [<ffffff80086e7560>] gk20a_tsg_event_id_post_event+0x50/0xc8 [<ffffff800872922c>] gk20a_gr_isr+0x27c/0x12e0 To fix this extract the TSG pointer before handling all the errors and pass this pointer to gk20a_gr_post_bpt_events() will post the events if they are enabled and if TSG is still open Bug 200404720 Change-Id: I4861c72e338a2cec96f31cb9488af665c5f2be39 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735415 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 14:40:04 -0400