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path: root/drivers/gpu/nvgpu/gk20a/gk20a.h
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* gpu: nvgpu: Disable rd_coalesce for all chipsAlex Waterman2017-08-16
| | | | | | | | | | | | Disable read coalescing for all chips. Bug 200314091 Change-Id: Iaa3f58f94369ae1edae0620083eca4594be730fd Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1518308 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Reorg mm HAL initializationSunny He2017-08-14
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ieb87a62f047510e51c52e6563d8e3fd5a65b5f28 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537753 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "gpu: nvgpu: Reorg mm HAL initialization"Sunny He2017-08-11
| | | | | | | | | | | | Conflicts with gv100 changes This reverts commit 8d63cd3995d4a650b478ad69d7e29ed2b1b2d927. Change-Id: Ie2f88d281b2b87a9a794d79164a61c4d883626b7 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537668 Reviewed-by: Shu Zhong <shuz@nvidia.com> Tested-by: Shu Zhong <shuz@nvidia.com>
* gpu: nvgpu: Reorg mm HAL initializationSunny He2017-08-11
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I289284e6e528fc7951c959c8765ccf9349eec33b Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1533351 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove mm.get_iova_addrAlex Waterman2017-08-04
| | | | | | | | | | | | | | | | | | | | | | Remove the mm.get_iova_addr() HAL and replace it with a new HAL called mm.gpu_phys_addr(). This new HAL provides the real phys address that should be passed to the GPU from a physical address obtained from a scatter list. It also provides a mechanism by which the HAL code can add extra bits to a GPU physical address based on the attributes passed in. This is necessary during GMMU page table programming. Also remove the flags argument from the various address functions. This flag was used for adding an IO coherence bit to the GPU physical address which is not supported. JIRA NVGPU-30 Change-Id: I69af5b1c6bd905c4077c26c098fac101c6b41a33 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530864 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Pass struct gk20a to gk20a_wait_for_idle()Terje Bergstrom2017-08-04
| | | | | | | | | | | | Pass struct gk20a pointer instead of struct device to gk20a_wait_for_idle(). The code is not Linux specific and does not need pointer to struct device. Change-Id: I2cafd6c7db019c9de76b6e68a1ae73f0b4cea37d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1533173 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: Pass gk20a to XVE initTerje Bergstrom2017-08-04
| | | | | | | | | | | Pass gk20a pointer instead of struct device pointer to XVE init. Change-Id: I5f5efc1d09430a45a49321830b1d7f17c7a57e2f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1528264 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Move debugfs fields to os_linuxTerje Bergstrom2017-08-04
| | | | | | | | | | | | | Move all Linux specific debugfs dentry fields to struct nvgpu_os_linux. JIRA NVGPU-62 Change-Id: I615620005f5d042943dd2e478c1629bcc912c550 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1528263 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Make LTC disabling common codeTerje Bergstrom2017-08-04
| | | | | | | | | | | | | | | | | | Refactor the sync_debugfs LTC HAL op so that the logic to enable or disable LTC goes to common code nvgpu_ltc_sync_enabled() and the LTC HAL set_enabled only performs the hardware register access. Create a new common function nvgpu_init_ltc_support() to initialize the LTC software variable, and move hardware initialization of LTC to be called from it. JIRA NVGPU-62 Change-Id: Ib1cf4f5b83ca3dac08407464ed56a732e0a33923 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1528262 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move isr related fields from gk20aTerje Bergstrom2017-08-03
| | | | | | | | | | | | | | | | | Move fields in struct gk20a related to interrupt handling into Linux specific nvgpu_os_linux. At the same time move the counter logic from function in HAL into Linux specific code, and two Linux specific power management functions from generic gk20a.c to Linux specific module.c. JIRA NVGPU-123 Change-Id: I0a08fd2e81297c8dff7a85c263ded928496c4de0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1528177 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sourab Gupta <sourabg@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Reorg gr_ctx HAL initializationSunny He2017-07-27
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr_ctx sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I783d8e8919d8694ad2aa0d285e4c5a2b62580f48 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1527417 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove privsecurity flag from gpu_opsSunny He2017-07-26
| | | | | | | | | | | | | | | | | Replace privsecurity boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_PRIVSECURITY Jira NVGPU-74 Change-Id: I4b258f5ffbe30a6344ffba0ece51c6f5d47ebec1 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1525713 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Remove securegpccs flag from gpu_opsSunny He2017-07-26
| | | | | | | | | | | | | | | | | Replace securegpccs boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_SECUREGPCCS Jira NVGPU-74 Change-Id: I46430f95063f617531cf0e5aba472051b41f4a9d Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514060 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Remove pmupstate flag from gpu_opsSunny He2017-07-26
| | | | | | | | | | | | | | | | | Replace pmupstate boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_PMU_PSTATE Jira NVGPU-74 Change-Id: I4e1ba922a48145b1cf3488b6f14fde78107adb5b Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514059 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: support context regoptype for egpc/etpcSeema Khowala2017-07-19
| | | | | | | | | | | | | | | | - add is_egpc_addr, is_etpc_addr and get_egpc_etpc_num gr ops - add gr ops for decode and create egpc/etpc priv addr - add etpc as part of ctxsw_regs JIRA GPUT19X-49 Bug 200311674 Bug 1960226 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Change-Id: I9a8be1804a9354238de2441093b3b136321b7e53 Reviewed-on: https://git-master.nvidia.com/r/1522442 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add perf gr ops to support t19xSeema Khowala2017-07-19
| | | | | | | | | | | | | Add init_ovr_sm_dsm_perf & get_ovr_perf_regs gr ops JIRA GPUT19X-49 Bug 200311674 Change-Id: If02dd9dc0e2e0eb1f68fdbaa86a37c6768eddcef Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1497403 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu : nvgpu: secure boot code unification.Deepak Goyal2017-07-18
| | | | | | | | | | | | | | This exposes all secure boot functions that can be re-used by other chips. This is the first patch in this series. Other pacthes will also follow. JIRA NVGPU-60 Change-Id: I523637bbf601166f8a01ddf29a913e193d3fdc7a Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514567 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgu: Support SET_BES_CROP_DEBUG3 sw methodLauri Peltonen2017-07-14
| | | | | | | | | | | | | | | The new SET_BES_CROP_DEBUG3 sw method is used to flip two fields in the NV_PGRAPH_PRI_BES_CROP_DEBUG3 register. The sw method is used by the user space driver to disable enough ROP optimizations to maintain ZBC state of target tiles. Bug 1942454 Change-Id: Id4e4d9d06c6c66080d06b6d4694546fe5cba8436 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1516202 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move gops.mc's non-fp membersSunny He2017-07-13
| | | | | | | | | | | | | | | | | | Move non-function pointer members out of the mc substruct of gpu_ops. Ideally gpu_ops will have only function ponters, better matching its intended purpose and improving readability. gops.mc.intr_mask_restore is now mc_intr_mask_restore Jira NVGPU-74 Change-Id: Iddf5e761012086e993c375d59e1bbdfb1e64db0c Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1509602 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add gr ops for mpc exception handlingSeema Khowala2017-07-10
| | | | | | | | | | | | | Required for t19x JIRA GPUT19X-69 Change-Id: I96d1ee2ae1bf310ce572cb4dc7773818a42a25a0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1515913 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add ops and var for t19x mmu faultSeema Khowala2017-07-08
| | | | | | | | | | | | | Add new ops and fields required for t19x mmu fault JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I29694c15ff9a4150bb1737adac6b58ccba76bea4 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1492640 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move dev field from gk20a to nvgpu_os_linuxTerje Bergstrom2017-07-07
| | | | | | | | | | | | | Move field "struct device *dev" from struct gk20a to struct nvgpu_os_linux. The field is valid only for Linux. JIRA NVGPU-38 Change-Id: I09286aa3a9c5a2406e5a27c1fbf21b2c515b4dd4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1514162 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use u32 for timeout API durationKonsta Holtta2017-07-07
| | | | | | | | | | | | | | | | A negative value in the timeout duration does not have any special uses, so change the duration type to u32 (from just int). Delete some unnecessary typecasts to int. Also change MAX_SCHEDULE_TIMEOUT to ULONG_MAX in default gr idle timeout because the value is in milliseconds instead of scheduling units and to drop unnecessary Linux dependency. Change-Id: I5cf6febd4f1cb00c46fe159603436a9ac3b003ac Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master/r/1512565 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support platform specific physical address translationDeepak Nibade2017-07-07
| | | | | | | | | | | | | | | On some GPUs certain physical address bits have special meaning. This patch adds support for setting those bits based on the GMMU attributes struct. Jira GPUT19X-10 Bug 200279508 Change-Id: I32b8a028be7fd62af06a60c393a8c9251de0ef3c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master/r/1512600 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add handle_tpc_sm_ecc_exception gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | | Needed to handle t19x sm ecc errors per tpc JIRA GPUT19X-75 JIRA GPUT19X-109 Change-Id: I921615dd5f551f34cdf55c1b085b16f562f16eb0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514044 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add clear_sm_hww gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | | Required for multiple SM support and t19x SM register address changes JIRA GPUT19X-75 Change-Id: Iad39f8566e2f5f000b019837304df24d9e2a37e3 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514043 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add sm lock_down gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | | Add lock_down_sm and wait_for_sm_lock_down gr ops Required to support multiple SM and t19x SM register address changes JIRA GPUT19X-75 Change-Id: I529babde51d9b2143fe3740a4f67c582b7eb404b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514042 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add get_sm_no_lock_down_hww_global_esr_mask gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | This is required to take care of t19x changes to support multiple SM JIRA GPUT19X-75 Change-Id: Ifd2cb28ae442462fef1d2c4439baa817f00c2c9e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514041 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add gr ops get_sm_hww_global_esrSeema Khowala2017-07-06
| | | | | | | | | | | | | | Required for multiple SM support and t19x sm register address changes JIRA GPUT19X-75 Change-Id: I437095cb8f8d2ba31b85594a7609532991441a37 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514040 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix race condition during poweronskadamati2017-07-05
| | | | | | | | | | | | | | | | | | When two or more apps ran simultaneously First app context sets power_on flag & starts init Other app context check the power_on flag and try to use GPU without init completed Which makes aother apps to assert Added mutex to synchronize poweron access Bug 200297265 Change-Id: Ie138f7f43bb0dd3304ed91ae3649a6a4947bee91 Signed-off-by: skadamati <skadamati@nvidia.com> Reviewed-on: https://git-master/r/1511436 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add get_sm_hww_warp_esr gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | | mask_hww_warp_esr gr ops is removed and replaced with get_sm_hww_warp_esr gr ops JIRA GPUT19X-75 Change-Id: I8c7194ca1b0e4fe740a6f8998a02fba846234e9e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512218 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add resume_all_sms gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: I844b5cf02a75ba397891a1100d917875e5a3e181 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512217 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add resume_single_sm gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: If8805bcc042c75ea70c1689306feb3c8bf011655 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512216 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add suspend_all_sms gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: Icdae3b6ed67a3d3deeb17f29528184b2d7a70af5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512215 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add suspend_single_sm gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: Id104f611736535874cdaa5a2f768f692d799c2c5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512214 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add sm_debugger_attached gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | This is required to support t19x sm register address changes JIRA GPUT19X-75 Change-Id: I7f961147e0e6464a71e240487f7bc964b0544e5d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512213 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add ops to support t19x ce changesSeema Khowala2017-07-02
| | | | | | | | | | JIRA GPUT19X-46 Change-Id: Idd17f2f644da1bbb8d31a55ac91561b25ff68aac Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1509749 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Per chip default big page sizeTerje Bergstrom2017-06-30
| | | | | | | | | | | | | | Make default big page size query a HAL op instead of per-platform constant. This allows querying for default big page size without accessing Linux specific gk20a_platform structure. JIRA NVGPU-38 Change-Id: Ibfbd1319764fdae5fdb06700fb64d23f6f3dd01a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1507928 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: move mclk related functions to clkThomas Fleury2017-06-30
| | | | | | | | | | | | | | Move mclk related functions be moved to clk structure instead of pmu. We want to keep pmu only for basic pmu interaction and split clk, lpwr etc. Bug 1921094 Change-Id: I32394bc0e6d3657dfbd34dbcf19c9af56c12e194 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master/r/1506586 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename hw_chid to chidRichard Zhao2017-06-30
| | | | | | | | | | | | | hw_chid is a relative id for vgpu. For native it's same as hw id. Renaming it to chid to avoid confusing. Jira VFND-3796 Change-Id: I1c7924da1757330ace715a7c52ac61ec9dc7065c Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master/r/1509530 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gr: rename write_preemption_ptrseshendra Gadagottu2017-06-29
| | | | | | | | | | | Change function name write_preemption_ptr to set_preemption_buffer_va to match with what exactly getting done in that function. Change-Id: Ia20c1df865dde01ab2878d3cf10281676ff5000e Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master/r/1510972 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PMU reset reorgMahantesh Kumbar2017-06-29
| | | | | | | | | | | | | | | | | | | | | | | | - nvgpu_pmu_reset() as pmu reset for all chips & removed gk20a_pmu_reset() & gp106_pmu_reset() along with dependent code. - Created ops to do PMU engine reset & to know the engine reset status - Removed pmu.reset ops & replaced with nvgpu_flcn_reset(pmu->flcn) - Moved sec2 reset to sec2_gp106 from pmu_gp106 & cleaned PMU code part of sec2. JIRA NVGPU-99 Change-Id: I7575e4ca2b34922d73d171f6a41bfcdc2f40dc96 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1507881 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add GPU_LIT_SM_PRI_STRIDE litter defineSeema Khowala2017-06-29
| | | | | | | | | | | | | Required to support multiple SM JIRA GPUT19X-75 Change-Id: If4397f29bfc4f31da13187182f0ae3c7423d0432 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1490096 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
* gpu: nvgpu: Support multiple SM for t19xSeema Khowala2017-06-29
| | | | | | | | | | | | | | | | | -Add sm input param for handle_sm_exception and pre_process_sm_exception for gr ops/functions. -Add functions to calculate gpc and tpc reg offsets. -Add function to find SMs which raised SM exception. JIRA GPUT19X-75 Change-Id: I257e7342ddabadb1556c9551c50a54d34b0f9d1e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1476108 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
* gpu: nvgpu: vgpu: perfbuffer supportPeter Daifuku2017-06-27
| | | | | | | | | | | | | | | | | Add vgpu support for ModeE perfbuffers - VM allocation is handled by the kernel, with final mapping handled by the RM server - Enabling/disabling the perfbuffer is handled by the RM server Bug 1880196 JIRA EVLR-1074 Change-Id: Ifbeb5ede6b07e2e112b930c602c22b66a58ac920 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master/r/1506747 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move sysfs dependencies from HAL to LinuxTerje Bergstrom2017-06-27
| | | | | | | | | | | | | Move sysfs dependencies from gk20a/ and gp10b/ to common/linux. At the same time the gk20a and gp10b variants are merged into one. JIRA NVGPU-48 Change-Id: I212be8f1beb8d20a57de04a57513e8fa0e2e83b4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1466055 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvpgu: Remove FECS override sysfs APITerje Bergstrom2017-06-27
| | | | | | | | | | | FECS override PMU support was removed with http://git-master/1297370. Remove the sysfs API that is wired to that. Change-Id: I5802e5a8dd78b80c3d255dd93587b24df9203fca Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1507934 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add fifo ops for handling pbdma_intr_1Seema Khowala2017-06-27
| | | | | | | | | | | | This is needed to handle new pbmda intr_1 in t19x JIRA GPUT19X-47 Change-Id: If75de0b57f3f18420aff07ee99feaad67ac63752 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1329373 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvpgu: Use correct chipidSamuel Payne2017-06-23
| | | | | | | | | | | | | | | Add gm20b "B" revision chipip. Bug 1870669 Change-Id: Ife31e6d739aabb8ef4a4f401091c3202b415a70e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1490650 Reviewed-by: Samuel Payne <spayne@nvidia.com> Signed-off-by: Samuel Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/1490648 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Reorder members of gpu_opsSunny He2017-06-22
| | | | | | | | | | | | | | Reorder non-function pointer members of gpu_ops to be at the very end of their respective sub-structs. This allows for easier debug interpretation and slightly improves readability. Jira NVGPU-107 Change-Id: Ife3279180306de70f7fad6760f616c6d69769b36 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: http://git-master/r/1506591 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>