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path: root/drivers/gpu/nvgpu/gk20a/gk20a.h
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* gpu: nvgpu: add init_pbdma_intr_desc fifo opsSeema Khowala2017-03-23
| | | | | | | | | | | | | | | | | | | | | | Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w variables for pbdma_intr_0 interrupt masks for each GPU version separately pbdma_intr_0 field differences for each GPU version:- -gk20a : bit 28 does not exists in hw -gm20b : bit 8(lbreq), 20(xbarconnect) and 28 do not exist in hw -gp10b : bit 8(lbreq), 20(xbarconnect) do not exist in hw. bit 28, (syncpoint_illegal) added in hw but is not being handled. -gk20a/gm20b/gp10b bit 24 eng_reset and bit 25 semaphore always existed in hw but never handled JIRA GPUT19X-47 Change-Id: I209191f57c5ea5b15081b7dc2411801d3537017c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1325402 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add bus HALTerje Bergstrom2017-03-23
| | | | | | | | | | | Add bus HAL and move all bus related hardware sequencing to that file: BAR1 binding, timer access, and interrupt handling. Change-Id: Ibc5f5797dc338de10749b446a7bdbcae600fecb4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323353 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: profiler create/free, hwpm reservePeter Daifuku2017-03-22
| | | | | | | | | | | | | | Add support for creating/freeing profiler objects, hwpm reservations Bug 1775465 JIRA EVLR-680 JIRA EVLR-682 Change-Id: I4db83d00e4b0b552b05b9aae96dc553dd1257d88 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1294401 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add mm ops for mmu_fault_pendingSeema Khowala2017-03-22
| | | | | | | | | | This change is needed for t19x mmu fault handling. Change-Id: I7f9190ab305f699401f6b0033b6a93dd8b4fc3cd Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1315201 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add is_preempt_pending fifo opsSeema Khowala2017-03-21
| | | | | | | | | | | | | is_preempt_pending fifo ops is added as t19x preempt done sequence is differnt than legacy chips. Change-Id: I6b46be1f5b911ae11bbe806968cb8fabb21848e0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1309678 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move sim support to its own fileTerje Bergstrom2017-03-21
| | | | | | | | | | | Simulator support is intermixed with the rest of code in gk20a.c. Move that code away from gk20a.c to an own file. Change-Id: Idd3c8795cec5eadc6e49811b5b8ff0592c49a7d2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323230 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Remove ELPG_FLUSHTerje Bergstrom2017-03-20
| | | | | | | | | | | | ELPG_FLUSH is not accessible in later GPUs, so we stopped using it and instead do explicit CBC and L2 flushes. Delete the unused function op and backing code. Change-Id: Ic3eb97f2d32ea8fdbe5ec57bd9254268caaf9935 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323236 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add refcounting to driver fdsDavid Nieto2017-03-20
| | | | | | | | | | | | | | | | | The main driver structure is not refcounted properly, so when the driver unload, file desciptors associated to the driver are kept open with dangling references to the main object. This change adds referencing to the gk20a structure. bug 200277762 JIRA: EVLR-1023 Change-Id: Id892e9e1677a344789e99bf649088c076f0bf8de Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1317420 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add fifo ops for intr_0_error_maskSeema Khowala2017-03-20
| | | | | | | | | | This change is required to support t19x mmu fault Change-Id: I3953dcf02c71ace606ba81896e56ea98683eb2ca Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313482 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move all FB programming to FB HALTerje Bergstrom2017-03-17
| | | | | | | | | | | | | | | | | | | | | Move all programming of FB to fb_*.c files, and remove the inclusion of FB hardware headers from other files. TLB invalidate function took previously a pointer to VM, but the new API takes only a PDB mem_desc, because FB does not need to know about higher level VM. GPC MMU is programmed from the same function as FB MMU, so added dependency to GR hardware header to FB. GP106 ACR was also triggering a VPR fetch, but that's not applicable to dGPU, so removed that call. Change-Id: I4eb69377ac3745da205907626cf60948b7c5392a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1321516 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement get_rate/set_rate as GPU opTerje Bergstrom2017-03-16
| | | | | | | | | | | | | | | | | | | Move clock APIs from gk20a_platform to gpu_ops. At the same time allow use of internal get_rate/set_rate for querying both GPCCLK and PWRCLK on iGPU. At the same time we can replace calls to clk framework with the new HAL and drop direct dependency to clk framework. gp10b ops were replaced as a whole at HAL initialization. That replaces anything set in platform probe stage, so reduce that to touch only clock gating regs. Change-Id: Iaf219b1f000d362dbf397d45832f52d25463b31c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1300113 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Rename clk->get_rate to measure_freqTerje Bergstrom2017-03-16
| | | | | | | | | | | | | | get_rate is already used for call-back that queries the last set clock rate. This instance of get_rate actually measures the frequency so renaming it to measure_freq. At the same time modify to use hertz instead of megahertz. We use fractional megahertz already in GPU. Change-Id: I387473d6a6cbf3bb9b9e5a909677a1a725403c32 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1300111 Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: refactor interrupt handlingDavid Nieto2017-03-14
| | | | | | | | | | | | | | | | | | | | | JIRA: EVLR-1004 (*) Refactor the non-stalling interrupt path to execute clear on the top half, so on dGPU case processing of stalling interrupts does not block non-stalling one. (*) Use a worker thread to do semaphore wakeups and allow batching of the non-stalling operations. (*) Fix a bug where some gpus will not properly track the completion of interrupts, preventing safe driver unloads Change-Id: Icc90a3acba544c97ec6a9285ab235d337ab9eefa Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1312796 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Lakshmanan M <lm@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: debug dump enablement for t19xSeema Khowala2017-03-09
| | | | | | | | | | | | Fifo ops added for dumping channel & ramfc status and pbdma & engine status. Change-Id: Icc739f4f05f0864721954489517fefdfa2fa608a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1302369 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: suspend/resume contextsThomas Fleury2017-03-09
| | | | | | | | | | | | | | | | | | | | | | | | | Add ability to suspend/resume contexts for a debug session (NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_CONTEXTS), in virtualized case: - added hal function to resume contexts. - added vgpu support for suspend contexts, i.e. build a list of channel ids, and send TEGRA_VGPU_CMD_SUSPEND_CONTEXTS - added vgpu support for resume contexts, i.e. build a list of channel ids, and send TEGRA_VGPU_CMD_RESUME_CONTEXTS Bug 1791111 Change-Id: Icc1c00d94a94dab6384ac263fb811c00fa4b07bf Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1294761 (cherry picked from commit d17a38eda312ffa92ce92e5bafc30727a8b76c4e) Reviewed-on: http://git-master/r/1299059 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Cory Perry <cperry@nvidia.com> Tested-by: Cory Perry <cperry@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add fifo ops for *client_type_gpc_vSeema Khowala2017-03-07
| | | | | | | | | | *client_type_gpc_v is different for t19x Change-Id: Ic8f8eff2d98138a877ef95c6f7f40226f0d61a61 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313436 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Disable trace_printk use by defaultTerje Bergstrom2017-03-07
| | | | | | | | | | | | | | | trace_printk() does an extra stringify operation before calling do_trace_printk(). The string ends up unused. This has an impact to kernel even if we never end up using trace_printk(). Disable use of trace_printk() and introduce a Kconfig option for re-enabling it. Change-Id: I2e1014f5231f2089d7dc3cb2539e3eb5f4d58361 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1295298 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: kmem abstraction and trackingAlex Waterman2017-03-03
| | | | | | | | | | | | | | | | Implement kmem abstraction and tracking in nvgpu. The abstraction helps move nvgpu's core code away from being Linux dependent and allows kmem allocation tracking to be done for Linux and any other OS supported by nvgpu. Bug 1799159 Bug 1823380 Change-Id: Ieaae4ca1bbd1d4db4a1546616ab8b9fc53a4079d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1283828 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove nvgpu_gpuid_t18x.hAlex Waterman2017-03-02
| | | | | | | | | | | | | | | Remove nvgpu_gpuid_t18x.h since this file is now visible. Migrate the relevant definitions and defines into their expected places and make the code use the real defines. No longer is hiding t18x specific stuff necessary. Bug 1799159 Change-Id: I47fa2392e46fdb7aacc70aeb0cc8c3f5ca0dc22f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1300976 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add worker for watchdog and job cleanupKonsta Holtta2017-03-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a worker thread to replace the delayed works in channel watchdog and job cleanups. Watchdog runs by polling the channel states periodically, and job cleanup is performed on channels that are appended on a work queue consumed by the worker thread. Handling both of these two in the same thread makes it impossible for them to cause a deadlock, as has previously happened. The watchdog takes references to channels during checking and possibly recovering channels. Jobs in the cleanup queue have an additional reference taken which is released after the channel is processed. The worker is woken up from periodic sleep when channels are added to the queue. Currently, the queue is only used for job cleanups, but it is extendable for other per-channel works too. The worker can also process other periodic actions dependent on channels. Neither the semantics of timeout handling or of job cleanups are yet significantly changed - this patch only serializes them into one background thread. Each job that needs cleanup is tracked and holds a reference to its channel and a power reference, and timeouts can only be processed on channels that are tracked, so the thread will always be idle if the system is going to be suspended, so there is currently no need to explicitly suspend or stop it. Bug 1848834 Bug 1851689 Bug 1814773 Bug 200270332 Jira NVGPU-21 Change-Id: I355101802f50841ea9bd8042a017f91c931d2dc7 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1297183 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add fifo ops for *data_fault_id_enum_vSeema Khowala2017-03-02
| | | | | | | | | | | | | generated hw header for top_device_info_data_fault_id_enum_v is different between legacy chips and t19x JIRA GV11B-7 Change-Id: I877e88a5b1b1f3f41bc72b895536f4a01b4fbd4e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313384 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gm20b: add gr ops for load tpc maskSeema Khowala2017-03-02
| | | | | | | | | | | | | gr_fe_tpc_fs_r addr is different for t19x Change-Id: I9868fcaf94d063753c4ecf1970b53374cb67b380 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1310326 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ACR interface headers reorganizationMahantesh Kumbar2017-02-23
| | | | | | | | | | | | | | | | | | | | | | -Moved ACR interface headers from acr_gm20b.h/acr_gp106.h to Its specific header files under “drivers/gpu/nvgpu/include/nvgpu/acr/” Folder. - nvgpu_acr.h - Top-level header-file which include ACR interfaces headers & defines required to communicate with ACR, including this header file is good to get access into ACR interface & made changes accordingly, -Deleted acr.h & acr_t18x.h as not required anymore & removed its include from dependent files. Jira NVGPU-19 Change-Id: Ie404043cfe1ab32404eb63a43831f470d8436324 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1304748 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use common nvgpu mutex/spinlock APIsDeepak Nibade2017-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using Linux APIs for mutex and spinlocks directly, use new APIs defined in <nvgpu/lock.h> Replace Linux specific mutex/spinlock declaration, init, lock, unlock APIs with new APIs e.g struct mutex is replaced by struct nvgpu_mutex and mutex_lock() is replaced by nvgpu_mutex_acquire() And also include <nvgpu/lock.h> instead of including <linux/mutex.h> and <linux/spinlock.h> Add explicit nvgpu/lock.h includes to below files to fix complilation failures. gk20a/platform_gk20a.h include/nvgpu/allocator.h Jira NVGPU-13 Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1293187 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Disable IRQs only if enabledAlex Waterman2017-02-21
| | | | | | | | | | | | | | | | | In the PCI init/de-init code only disable IRQs if they were enabled. The enable happens in the common power_on code. The PCI routines could both be called without the common power_on code being called which causes an extra disable to happen. Bug 200275531 Change-Id: I43a8a9881f1e9ae254bf36230f29849df074657f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1301701 (cherry picked from commit cca70e9adccee1ef65a0a6d95a4494fc87500c17) Reviewed-on: http://git-master/r/1298954 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove almost all gm204/gm206 supportTerje Bergstrom2017-02-17
| | | | | | | | | | | | Remove gm204/gm206 support. It was used only in the interim until Pascal cards were available, and we don't maintain that code anymore. This patch leaves only BIOS code. Change-Id: I215988603d4588ef710bdda6e47449e9235e78ac Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1302224 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Generalize BIOS codeTerje Bergstrom2017-02-17
| | | | | | | | | | | | | | | | | | Most of BIOS parsing code is not specific to any particular GPU. Move most of the code to generic files, and leave only chip specific parts dealing with microcontroller boot into chip specific files. As most of the parsing is generic, they do not need to be called via HALs so remove the HALs and change the calls into direct function calls. All definitions meant to be used outside BIOS code itself are now in <nvgpu/bios.h> Change-Id: Id48e94c74511d6e95645e90e5bba5c12ef8da45d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1302222 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add NVGPU_IOCTL_CHANNEL_SET_BOOSTED_CTXPeter Boonstoppel2017-02-14
| | | | | | | | | | | | | | | | This ioctl can be used on gp10b to set a flag in the context header indicating this context should be run at elevated clock frequency. FECS ctxsw ucode will read this flag as part of the context switch and will request higher GPU clock frequencies from BPMP for the duration of the context execution. Bug 1819874 Change-Id: I84bf580923d95585095716d49cea24e58c9440ed Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1292746 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move from gk20a_ to nvgpu_ in semaphore codeAlex Waterman2017-02-13
| | | | | | | | | | | | | Change the prefix in the semaphore code to 'nvgpu_' since this code is global to all chips. Bug 1799159 Change-Id: Ic1f3e13428882019e5d1f547acfe95271cc10da5 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1284628 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
* gpu: nvgpu: Add enable/disable shadow ROM HALTerje Bergstrom2017-02-13
| | | | | | | | | Add HAL for enabling and disabling shadow ROM. This removes XVE dependency from bios code. Change-Id: Icafec72dae71669376bbfb97077661b7165badb8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1302223
* gpu: nvgpu: enable PCI MSI interruptsDavid Nieto2017-02-08
| | | | | | | | | | | | | | Use MSI interrupts instead of legacy on PCIe dGPUs to reduce latency and contention with other PCIe devices JIRA EVLR-986 Change-Id: I6cecc7e62e5797860d42a5bee21e8f4f664e1b18 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1291758 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: implement chip specific init_elcg_modeseshendra Gadagottu2017-02-07
| | | | | | | | | | | | | Added function pointer to implement chip specific init_elcg mode and updated this pointer for legacy chips. JIRA GV11B-58 Change-Id: I3fff4f771eaa5dad98a3d8166c9127ecd6b745e4 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1300120 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove separate fixed address VMAAlex Waterman2017-01-31
| | | | | | | | | | | | | | Remove the special VMA that could be used for allocating fixed addresses. This feature was never used and is not worth maintaining. Bug 1396644 Bug 1729947 Change-Id: I06f92caa01623535516935acc03ce38dbdb0e318 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1265302 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: update zcull and pm context pointersseshendra Gadagottu2017-01-27
| | | | | | | | | | | | | Update zcull and perfmon buffer pointers in context header through function pointers. JIRA GV11B-48 Change-Id: Iaa6dd065128cb0c39e308cecf17b9d68a826d865 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1291850 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Make driver rebind workAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the GPU bind and rebind operations work when the driver is idle. This required two changes. 1. Reset the GPU before doing SW init for PCI GPUs. This clears the SW state which may be stale in the case of a rebind attempt. 2. Cleanup the interrupt enable/disables. Firstly there was one place where nvgpu would accidentally disable the stalling interrupt twice when the stalling interrupt and non-stalling interrupt are the same. Secondly make sure when exiting nvgpu that the interrupt enable/disables are balanced. Leaving the interrupt in the -1 disable state means that next time the driver runs interrupts never quite get enabled. Bug 1816516 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1287643 Reviewed-on: http://git-master/r/1287649 (cherry picked from commit aa15af0aae5d0a95a8e765469be4354ab7ddd9f8) Change-Id: I945e21c1fbb3f096834acf850616b71b2aab9ee3 Reviewed-on: http://git-master/r/1292700 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add GPU reset to XVEAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | | | | | Add a full GPU reset function to the XVE block. This allows the driver to reset the GPU (except the XVE and XP interfaces) to clear the GPU's state. This is necessary for the GPU rebind to work. The state of the GPU needs to be cleared before the new driver instance can work. Bug 1816516 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1287642 Reviewed-on: http://git-master/r/1287648 (cherry picked from commit 7e751c0eb2c0f7d9d0b2020600c33fc8b4381878) Change-Id: Ie2b721bf1b40acbab34de2436dea4e70d33b5611 Reviewed-on: http://git-master/r/1292698 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: restore golden context without bindseshendra Gadagottu2017-01-20
| | | | | | | | | | | | | | | | | Copy and restore golden context correctly with context header. Removed parallel fecs bind method, which can cause issues for context in execution. Also added function pointer to freeing context header during channel context free. Bug 1834201 Change-Id: I7962d68338d5144f624375ab81436e86cb31051e Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1275201 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use soc/tegra/chip-id.h for soc headerShardar Shariff Md2017-01-20
| | | | | | | | | | | | The soc tegra headers are unified and moved all the content of linux/tegra-soc.h to the soc/tegra/chip-id.h to have the single soc header for Tegra. Change-Id: I281e19dd3eb1538b8dfbea4eb0779fb64d1fcffa Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1288365 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: pmu: Use ops to get PMU queue HEAD/TAIL.Deepak Goyal2017-01-18
| | | | | | | | | | | | | | pmu_queue_head() & pmu_queue_tail() are updated to use gops to include chip specific PMU queue head/tail registers. JIRA GV11B-30 Change-Id: I9c3d6a4601ba2767f9ada95642052044e2b79747 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1283266 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use timer API in gk20a codeAlex Waterman2017-01-18
| | | | | | | | | | | | | | | | | Use the timers API in the gk20a code instead of Linux specific API calls. This also changes the behavior of several functions to wait for the full timeout for each operation that can timeout. Previously the timeout was shared across each operation. Bug 1799159 Change-Id: I2bbed54630667b2b879b56a63a853266afc1e5d8 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1273826 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support t19x zbcSeema Khowala2017-01-18
| | | | | | | | | | | | | Added infrastructure for supporting new zbc features JIRA GV11B-9 Change-Id: Id8408348759488e8b0393dd89dd0faacfb111f01 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1235525 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: HAL to get current pstateMahantesh Kumbar2017-01-17
| | | | | | | | | | | | | | | | | | - Added HAL support to get current pstate from clk_arb Note - This function is inherently unsafe to call while arbiter is running arbiter must be blocked before calling this function JIRA DNVGPU-165 Change-Id: I4e9f5eba7739280bddd9ee661fd314288c129516 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1286378 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix pmu->mscg_stat optimization issueMahantesh Kumbar2017-01-17
| | | | | | | | | | | | | | | | | | | | | | | - with help of WRITE_ONCE() & ACCESS_ONCE() make sure variable pmu->mscg_stat read/write goes through without optimization - Added WRITE_ONCE() define for kernel-3.18 version & below to support backward compatibility issue: inconsistencies on getting MSCG to trigger consistently in P5 due to a lack of memory barrier around and volatile accesses to the variable pmu->mscg_stat JIRA DNVGPU-71 Change-Id: I04d30493d42c52710304dbdfb9cb4a1e9a76f2c0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1252524 (cherry picked from commit 8af7fc68e7ab06a856ba4ef4e44de7336682361b) Reviewed-on: http://git-master/r/1271614 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: HAL to query LPWR feature supportMahantesh Kumbar2017-01-16
| | | | | | | | | | | | | | | HAL to query LPWR feautre's RPPG/MSCG support based on current pstate configured. JIRA DNVGPU-71 Change-Id: I58a34c6dca68e3eb76e222bd781578bf682eac34 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1283916 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add sysfs nodes for timeslice min/maxPeter Boonstoppel2017-01-12
| | | | | | | | | | | | | | | | | | The timeslice values that can be selected for a particular channel/tsg are bounded by a static min/max. This change introduces two sysfs nodes that allow these bounds to be configured from userspace. min_timeslice_us max_timeslice_us Bug 200251974 Bug 1854791 Change-Id: I5d5a14225eee4090e418c7e43629324114f60768 Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1280372 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pg stat read updateMahantesh Kumbar2017-01-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added struct pmu_pg_stats_data to extract data from multiple version of pmu pg statistics - Added pmu_pg_stats_v2 interface to fetch PG statistics data from PMU - Added MSCG debugfs node to read mscg statistics from PMU. - Added pmu_elpg_statistics HAL support for gp106 PG statistics read. - Made changes to gp104/gp106 pmu_elpg_statistics HAL to support for struct pmu_pg_stats_data JIRA DNVGPU-165 Change-Id: I2b9e89c0fae90deb45006c4478170b9a97b56603 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1252798 (cherry picked from commit 3c073b15fd991db8d65b3171b02c161294be40cd) Reviewed-on: http://git-master/r/1271615 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add thermal alert event handlingLakshmanan M2017-01-10
| | | | | | | | | | | | | | | | * Added the thermal alert event handling * Added the thermal alert event PMU RPC JIRA DNVGPU-130 Bug 200231080 Change-Id: If5ff2704e5aa6ad2f25123f72c3049a311dae5dc Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1248964 (cherry picked from commit 1850e5a9b9dfa2f9df634e2f284ab282ad9f7fc8) Reviewed-on: http://git-master/r/1253452 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add platform flag to disable ASPMAlex Waterman2017-01-04
| | | | | | | | | | | | | | | Add a platform flag and logic to disable ASPM on boot if a platform does not want ASPM enabled. Bug 200256272 Change-Id: I378997290377ef8ffa21bf8e7f3f59fa134b3d4d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1263271 (cherry picked from commit 01e4700b74f4b4c6f0b9ffb40747653f2b63ea3c) Reviewed-on: http://git-master/r/1274477 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Handle driver shutdown more gracefullyAlex Waterman2017-01-04
| | | | | | | | | | | | | | | | | | | | | | | | Handle possible asynchronous GPU driver shutdown more gracefully. This occurs when the GPU disappears from the PCI bus, for example, if it overheats or detects an over current event. Also add a preprocessor check to make sure that the gk20a_channel_cancel_pending_sema_waits() is always defined. In some builds CONFIG_SYNC is disabled but the gk20a_remove_support() code does not check for this. Bug 1816516 Bug 1807277 Change-Id: I932e312291c5c6a6ac5e13525ce8ca56a1be3652 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1250028 (cherry picked from commit 337810f8c478238a38d8553c1492622d5fa9aafa) Reviewed-on: http://git-master/r/1274476 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move deferred interrupt wait codeAlex Waterman2017-01-04
| | | | | | | | | | | | | | | | | Move the code that waits for deferred interrupts to nvgpu_common.c and make it global. Also rename that function to use nvgpu_ as the function prefix. Bug 1816516 Bug 1807277 Change-Id: I42c4982ea853af5489051534219bfe8b253c2784 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1250027 (cherry picked from commit cb6fb03e20b08e5c3606ae8a5a9c237bfdf9e7da) Reviewed-on: http://git-master/r/1274475 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-17 07:46:36 -0400