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path: root/drivers/gpu/nvgpu/gk20a/gk20a.h
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* gpu: nvgpu: gm20b: Regenerate clock gating listsTerje Bergstrom2015-03-18
| | | | | | | | | | Regenerate clock gating lists. Add new blocks, and takes them into use. Also moves some clock gating settings to be applied at the earliest possible moment right after reset. Change-Id: I21888186c200f7a477c63bd3332e8ed578f63741 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/457698
* gpu: nvgpu: add HAL for regopsKevin Huang2015-03-18
| | | | | | | | | | | Bug 1500195 Change-Id: I5545d1a95a58e7daa5a74cc20f3fc6828774fc42 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/488507 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: dynamically detect priv security for secure boot of falconVijayakumar2015-03-18
| | | | | | | | | | | based on the config setting and fuse secure no non secure boot is done Change-Id: I5937ba945c5a3a86f72e0f2a9078fcde01977137 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/487684 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: support gk20a virtualizationAingara Paramakuru2015-03-18
| | | | | | | | | | | | | The nvgpu driver now supports using the Tegra graphics virtualization interfaces to support gk20a in a virtualized environment. Bug 1509608 Change-Id: I6ede15ee7bf0b0ad8a13e8eb5f557c3516ead676 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/440122 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Set PB timeout only in gk20aTerje Bergstrom2015-03-18
| | | | | | | | | | | | | PB timeout has been removed in gm20b, so write it only in gk20a. Change-Id: I2aab92fe7d1d5de151dad768f8b3f6901ec0bbb0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/486358 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
* gpu: nvgpu: 3d.emc bandwidth ratio policySamuel Russell2015-03-18
| | | | | | | | | | | | | Modify the 3d.emc policy to use a formula based on bandwidth and utilization instead of the current sku-dependent policy. Bug 1364894 Change-Id: Id97f765a48f0aa9f5ebeb0c82bccb22db474a1ae Signed-off-by: Samuel Russell <samuelr@nvidia.com> Reviewed-on: http://git-master/r/453586 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: use gpc_mmu to check debug modeKevin Huang2015-03-18
| | | | | | | | | | Bug 1534793 Change-Id: I8a4c35914b58dd13a7c10c668de9d4662d947d8c Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/441377 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: clear sparse in space freeKevin Huang2015-03-18
| | | | | | | | | | | | | | Gk20a unmaps the addresses binding to dummy page to clear sparse. On Gm20b, we need to free the allocated page table entry for sparse memory. Bug 1538384 Change-Id: Ie2409ab016c29f42c5f7d97dd7287b093b47f9df Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/448645 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvpug: add hal func get_gpc_tpc_maskKevin Huang2015-03-18
| | | | | | | | | | | | | Retrieve which TPC is floorswept. Bug 1450798 Change-Id: I3ea60703695448c68cd3435f443b280d5b2f0995 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/403876 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: sysfs mode for allowing access to registerssujeet baranwal2015-03-18
| | | | | | | | | | | | | Through this sysfs entry, the register space becomes accessible. This is be accessible root-only. Bug 1523403 Change-Id: Ia46f130a0cfd8324c5b675d19e7cbfba9dcb17ca Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com> Reviewed-on: http://git-master/r/454198 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add boost once GPU is initializedTerje Bergstrom2015-03-18
| | | | | | | | | | | Workaround for GPU hang if boost turns GPU on before it is initialized. Bug 1435870 Change-Id: I07d0617049612344ca7c494da8cb8d75789984e5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/453375
* nvgpu:Added PROD settings for ELPG sequencingMahantesh Kumbar2015-03-18
| | | | | | | | | Added PROD settings for ELPG sequencing registers Bug 200023161 Change-Id: Id313f9bc800d3a57f45aff0f0f609887565971be Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
* gpu: nvgpu: CDE supportArto Merilainen2015-03-18
| | | | | | | | | | | | | | This patch adds support for executing a precompiled GPU program to allow exporting GPU buffers to other graphics units that have color decompression engine (CDE) support. Bug 1409151 Change-Id: Id0c930923f2449b85a6555de71d7ec93eed238ae Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/360418 Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: new gpmu ucode compatibilitySupriya2015-03-18
| | | | | | | | | | | | | | For LS PMU new ucode needs to be used. Ucode has interface header file changes too. This patch also has fixes for pmu dmem copy failure Bug 1509680 Change-Id: I8c7018f889a82104dea590751e650e53e5524a54 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/441734 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fork GM20B clock from GK20A clockHoang Pham2015-03-18
| | | | | | | | | Bug 1450787 Change-Id: Id7fb699d9129a272286d6bc93e0e95844440a628 Signed-off-by: Hoang Pham <hopham@nvidia.com> Reviewed-on: http://git-master/r/440536 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Init clock debugfs after clock supportAlex Frid2015-03-18
| | | | | | | | | | | | Initialized GK20A clock debugfs after clock support hardware and software are ready. Bug 1450787 Change-Id: I8ec2ef303a84b9151b7ce209a1864f1729382a44 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/440973 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: Split clk_ops for GK20A and GM20BHoang Pham2015-03-18
| | | | | | | | | | | Split clk_ops for GK20A and GM20B into different files Bug 1450787 Change-Id: I34d16c54ac40c70854e80588475434c9e50b51a5 Signed-off-by: Hoang Pham <hopham@nvidia.com> Reviewed-on: http://git-master/r/437771 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: force idle if railgate not supportedDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | Add a way to force idle and reset the GPU in case where GPU rail gating is not supported (i.e. platform->can_railgate = false) In this case, we follow below sequence : - once GPU is idle, get runtime reference which enables the clocks - call prepare_poweroff() to save the state explicitly - perform explicit reset assert/deassert - call finalize_poweron() to restore the state - drop the runtime reference taken earlier Bug 1525284 Change-Id: Id5f3ec152093acd585631dfbf785d8e0561f9048 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/435620 GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Tested-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu:nvgpu: Enable Falcon trace printsVijayakumar2015-03-18
| | | | | | | | | | | Dump Falcon trace on PMU Crash and add debugfs node falc_trace. This needs Debug trace to be enabled in GPmu binary. Change-Id: I093ef196202958e46d8d9636a848bd6733b5e4cc Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/432732 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Remove GPU MMIO access on power/rail gateAlex Waterman2015-03-18
| | | | | | | | | | | | This is to weed out accesses to the GPU while it is gated. Otherwise the accesses are silently dropped or cause a HW hang (on older chips). Bug 1514949 Change-Id: Ice4cdb9f1f736978ebb3db847f39c7439bf98134 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/416339 Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: Boot FECS to secure modeTerje Bergstrom2015-03-18
| | | | | | | | | | Boot FECS to secure mode if ACR is enabled. Bug 200006956 Change-Id: Ifc107704a6456af837b7f6c513c04d152b2f4d3a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424251
* gpu: nvgpu: Separate PMU firmware load from initTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Separate the code to load PMU firmware from the software init. This allows folding ACR and non-ACR PMU software initialization sequences. Bug 200006956 Change-Id: I74b289747852167e8ebf1be63036c790ae634da4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424768 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Remove extra g field in pmu_gk20aTerje Bergstrom2015-03-18
| | | | | | | | | | | pmu_gk20a has a pointer to struct gk20a *. As pmu_gk20a is part of gk20a, there's no need to have the circular dependency. Bug 200006956 Change-Id: I6d5d10a93b2fba4a26a1e28b3c5206506dc6cc04 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424767
* gpu: nvgpu: add kernel APIs for TSG supportDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | Add support to create/destroy TSGs using node "/dev/nvhost-tsg-gpu" Provide below IOCTLs to bind/unbind channels to/from TSGs : NVGPU_TSG_IOCTL_BIND_CHANNEL NVGPU_TSG_IOCTL_UNBIND_CHANNEL Bug 1470692 Change-Id: Iaf9f16a522379eb943906624548f8d28fc6d4486 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/416610
* gpu: nvgpu: add explicit wmb() before reg writeDeepak Nibade2015-03-18
| | | | | | | | | | | | | | Add explict memory barrier wmb() before writing to register values. Also call writel_relaxed() instead of writel() to skip internal wmb() call which is conditional on some configs. Bug 200012037 Change-Id: I9c545138314b6e73fec2a4aff2b1956444fac806 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/421463 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com>
* nvgpu: Host side changes to support HS modeSupriya2015-03-18
| | | | | | | | | | | | | | | | | | | GM20B changes in PMU boot sequence to support booting in HS mode and LS mode Bug 1509680 Change-Id: I2832eda0efe17dd5e3a8f11dd06e7d4da267be70 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/423140 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Implement L2 flush in fifo recoveryAlex Waterman2015-03-18
| | | | | | | | | | | | | Implement a full L2 flush (clean and invalidate) for gm20b in the fifo recovery path. Bug 1512176 Change-Id: Ibf89ede9cca65a6868ebff89825869053302a007 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/416435 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reload ZBC values on rail gate exitTerje Bergstrom2015-03-18
| | | | | | | | | | | When exiting rail gate, we reloaded default ZBC values. The correct behavior is to reload the values. Bug 1447255 Change-Id: I7aad3586dda91a91a3629062a27001af281b955e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/418346
* gpu: nvgpu: gm20b: fix compression sharingKevin Huang2015-03-18
| | | | | | | | | | | | | | | | For GM20B alone, the LTC count is already accounted for the HW logic for the CBC base calculation from the postDivide address. So SW doesn't have to explicity divide it by the LTC count in the postDivide address calculation. Bug 1477079 Change-Id: I558bbe66bbcfb7edfa21210d0dc22c6170149260 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/414264 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add generic api for sparse memoryKevin Huang2015-03-18
| | | | | | | Bug 1442531 Change-Id: I97408b54e27f5ed6411792e73f079a6f86cbe5f6 Signed-off-by: Kevin Huang <kevinh@nvidia.com>
* gpu: nvgpu: sysfs to put gpu into idleDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | - Add a sysfs "force_idle" to forcibly idle the GPU - read on this sysfs will return the current status 0 : not in idle (running) 1 : in forced idle state "echo 1 > force_idle" will force the gpu into idle "echo 0 > force_idle" will cause the gpu to resume Bug 1376916 Bug 1487804 Change-Id: I48dfd52e0d14561220bc4baea0776d1bdfaa7ea5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: Add gm20b fecs/gpccs bootloader supportTerje Bergstrom2015-03-18
| | | | | | | | | Add support for booting FECS and GPCCS via faster bootloader method. We leave this disabled until the bootloader binaries are checked in. Change-Id: I39df5d116f7a33486407518c743638b01923970d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/413005
* gpu: nvgpu: gk20a: add busy lockDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | - add rw_semaphore busy_lock for gpu busy() path - take read lock on busy_lock inside gk20a_busy() so that all usual requests can execute simultaneously - write lock can be taken when we need to block all of the gk20a_busy() calls Bug 1487804 Change-Id: I1b162b38bce9621723d3e45280c6076816cf771a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/412060 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Register as subdomain of host1xTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | Add gk20a as a sub power domain of host1x. This enforces keeping host1x on when using gk20a. Bug 200003112 Change-Id: I08db595bc7b819d86d33fb98af0d8fb4de369463 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/407006 (cherry picked from commit 009812b3e510518740e9c7e89b8b8b80439fe26a) Reviewed-on: http://git-master/r/408013 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: halize ltc isrKevin Huang2015-03-18
| | | | | | | | | | Bug 1507804 Change-Id: I3cca0e83dbf911c94422f8bb0b2df675a170b990 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/403213 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "gpu: nvgpu: Keep host1x on when GPU on"Matt Pedro2015-03-18
| | | | | | | | | | | This reverts commit 20d48a759b032116e3092e1df76518065da59879. Change-Id: I93718a314b70ee9284a83ca69964883e670ad78d Signed-off-by: Matt Pedro <mapedro@nvidia.com> Reviewed-on: http://git-master/r/407969 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Get host1x device from DTSArto Merilainen2015-03-18
| | | | | | | | | | | | | | | Currently the gpu driver assumes that the GPU is a child of host1x. This is an invalid assumption and therefore we need to get the host1x device from device tree based on nvidia,host1x property. Bug 1311528 Bug 1434573 Change-Id: I097e39369aaa15ab6652cd23f353f88f7c2b9c48 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/395664 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* video: tegra: host: gk20a: GM20B characteristicsSami Kiminki2015-03-18
| | | | | | | | | | | | | This patch adds initial support for GM20B for GPU characteristics IOCTL. Bug 1392902 Change-Id: I55bfb7e087244eae1462d44319bd91c7c0901c2e Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/359227 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Register as subdomain of host1xTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Add gk20a as a sub power domain of host1x. This enforces keeping host1x on when using gk20a. Bug 200003112 Change-Id: I08db595bc7b819d86d33fb98af0d8fb4de369463 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/407543 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
* gpu: nvgpu: Request irq at probeTerje Bergstrom2015-03-18
| | | | | | | | | | Request irq at probe instead of at poweron. This allows investigating interrupt numbers across rail gating cycles. Change-Id: I6db4b3f1d865c6fbbd9d6a96c3df89617e169891 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/374859
* gpu: nvgpu: Make trigger mmu fault GPU specificTerje Bergstrom2015-03-18
| | | | | | | | | | | Add abstraction for triggering fake MMU fault, and a gk20a implementation. Also adds recovery to FE hardware warning exception to make testing easier. Bug 1495967 Change-Id: I6703cff37900a4c4592023423f9c0b31a8928db2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add CBC clean and invalidateArto Merilainen2015-03-18
| | | | | | | Bug 1409151 Change-Id: I232af159d402f818cf972498d721c3b57846ce74 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: gk20a: Fix G_ELPG flush pollTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | We poll completion of flush sequence by polling the broadcast register. The polling should be done for a per-slice register instead. Bug 1457723 Change-Id: I10aba939175b6d05b05f5f26eebebcbe09d9b4a7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/382521 Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Tested-by: Juha Tukkinen <jtukkinen@nvidia.com>
* video: tegra: host: flexible to select fw per chipKevin Huang2015-03-18
| | | | | | | | | | | Decouple the firmware selection of different gpu architecture. Change-Id: I62bf6b3bc51a8606c5973e475988cd5987a65a1a Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/389793 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add NVIDIA GPU DriverArto Merilainen2015-03-18
This patch moves the NVIDIA GPU driver to a new location. Bug 1482562 Change-Id: I24293810b9d0f1504fd9be00135e21dad656ccb6 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/383722 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 13:02:45 -0400