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path: root/drivers/gpu/nvgpu/gk20a/gk20a.h
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* gpu: nvgpu: bring back tegra idle registrationKonsta Holtta2017-06-15
| | | | | | | | | | | | | | | | | | | | To make do_idle work when nvgpu is built as a module, reverse the order of call dependencies for do_idle. Don't provide visible gk20a_do_{idle,unidle}() functions for the kernel but instead call the kernel for registering and unregistering pointers to them when the driver loads and unloads. Refactor the internal __gk20a_do_{idle,unidle} functions to take a struct gk20a * instead of struct device *, and use the callback api for providing that g instead of retrieving the plat device from device tree. Bug 200290850 Change-Id: Ibef8b069302e547b298069cbb97734f461a10cc3 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1493774 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: hold power ref for deterministic channelsKonsta Holtta2017-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support deterministic channels even with platforms where railgating is supported, have each deterministic-marked channel hold a power reference during their lifetime, and skip taking power refs for jobs in submit path for those. Previously, railgating blocked deterministic submits in general because of gk20a_busy()/gk20a_idle() calls in submit path possibly taking time and more significantly because the gpu may need turning on which takes a nondeterministic and long amount of time. As an exception, gk20a_do_idle() can still block deterministic submits until gk20a_do_unidle() is called. Add a rwsem to guard this. VPR resize needs do_idle, which conflicts with deterministic channels' requirement to keep the GPU on. This is documented in the ioctl header now. Make NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING always set in the gpu characteristics now that it's supported. The only thing left now blocking NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_FULL is the sync framework. Make the channel debug dump show which channels are deterministic. Bug 200291300 Jira NVGPU-70 Change-Id: I47b6f3a8517cd6e4255f6ca2855e3dd912e4f5f3 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1483038 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: reorganize PMU initMahantesh Kumbar2017-06-12
| | | | | | | | | | | | | | | | | | | | | | | | - Moved PMU init code from pmu_gk20a.c to "drivers/gpu/nvgpu/common/pmu/pmu.c" file - Moved below related methods SW/HW init, init msg handler, deinit/destroy, PMU state machine -Created HAL methods to read message queue tail & supported mutex count. -prepend with nvgpu_ for pmu init global mehtods JIRA NVGPU-56 JIRA NVGPU-92 Change-Id: Iea9efc194fefa74fb5641d2b2f4633577d2c3a47 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1480002 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: reorganize PMU IPCMahantesh Kumbar2017-06-09
| | | | | | | | | | | | | | | | | | | | - Moved PMU IPC related code to drivers/gpu/nvgpu/common/pmu/pmu_ipc.c file, -Below is the list which are moved seq mutex queue cmd/msg post & process event handling NVGPU-56 Change-Id: Ic380faa27de4e5574d5b22500125e86027fd4b5d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1478167 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use nvgpu specific nvhost APIsDeepak Nibade2017-06-08
| | | | | | | | | | | | | | | | | | | | | | | | | | Remove use of linux specifix header files <linux/nvhost.h> and <linux/nvhost_ioctl.h> and use nvgpu specific header file <nvgpu/nvhost.h> instead This is needed to remove all Linux dependencies from nvgpu driver Replace all nvhost_*() calls by nvgpu_nvhost_*() calls from new nvgpu library Remove platform device pointer host1x_dev from struct gk20a and add struct nvgpu_nvhost_dev instead Jira NVGPU-29 Change-Id: Ia7af70602cfc16f9ccc380752538c05a9cbb8a67 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1489726 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: add nvhost abstraction filesDeepak Nibade2017-06-08
| | | | | | | | | | | | | | | | | | | | | Add new abstraction file common/linux/nvhost.c for all nvhost APIs and operations and export them from header <nvgpu/nvhost.h> This file will be compiled only if config CONFIG_TEGRA_GK20A_NVHOST is set Define struct nvgpu_nvhost_dev in a separate private header nvhost_priv.h Jira NVGPU-29 Change-Id: I17e1f7836d4854feadff0c339bc093e78ba7f3eb Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1489725 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Split non-stall interrupt handlingTerje Bergstrom2017-06-07
| | | | | | | | | | | | | | | | | | | | | | Split handling of stalling interrupt to Linux specific chip agnostic and OS independent chip specific parts. Linux specific chip independent part contains handler for ISR and passing the control to a bottom half worker. It uses the new MC HALs intr_nonstall (query interrupt status), intr_nonstall_pause (pause interrupts), intr_nonstall_resume (resume interrupts), and is_intr1_pending (query per-engine interrupt bit). MC HAL isr_nonstall is removed, because its work is now handled in chip independent code. JIRA NVGPU-26 Change-Id: I3e4c9905ef6eef7f1cc9f71b0278518ae663f87e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1497048 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add MC HAL is_intr1_pendingTerje Bergstrom2017-06-07
| | | | | | | | | | | | | | | Add MC HAL is_intr1_pending. At the same time introduce nvgpu_unit that is passed as parameter to is_intr1_pending. The API is passed contents of intr1 register and an engine number, and returns true if there's an interrupt pending for the engine. JIRA NVGPU-26 Change-Id: I8e6363dd78572f8e41dbab2b258036ed168b6f75 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1497870 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: implement chip specific fb cbc_initseshendra Gadagottu2017-06-07
| | | | | | | | | | | | | Add function pointer in fb to add chip specific cbc init. GPUT19X-70 Change-Id: I12f73945d99498de965a671fd8e258b5c95bbabe Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1484524 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Unify vm_init for vGPU and regular GPUAlex Waterman2017-06-06
| | | | | | | | | | | | | | | | | Unify the initialization routines for the vGPU and regular GPU paths. This helps avoid any further code divergence. This also assumes that the code running on the regular GPU essentially works for the vGPU. The only addition is that the regular GPU path calls an API in the vGPU code that sends the necessary RM server message. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: I37af1993fd8b50f666ae27524d382cce49cf28f7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1480226 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move clk_gm20b debugfs to Linux moduleDeepak Nibade2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move debugfs code from clk_gm20b.c to file in Linux module common/linux/debug_clk.c This file will be compiled only if CONFIG_DEBUG_FS is set Define below new HAL APIs for various clock operations which can be accessed from debug file init_debugfs() get_voltage() get_gpcclk_clock_counter() pll_reg_write() get_pll_debug_data() Export nvgpu_pl_to_div() and nvgpu_div_to_pl() so that these can be accessed from debug_clk.c Add new structure nvgpu_clk_pll_debug_data so that all required register values for debugging can be made available in debug_clk.c Add new API gm20b_get_gpc_pll_parms() so that statically defined variable can be accessed in debug_clk.c too Remove global variable dvfs_safe_max_freq and add it to struct clk_gk20a so that it can accessed from both clk_gm20b.c and debug_clk.c Jira NVGPU-62 Change-Id: I3ae70b40235e78141a686686930e1f178ad59453 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1488903 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: moved & renamed "struct pmu_gk20a"Mahantesh Kumbar2017-06-05
| | | | | | | | | | | | | | | | | | | - Renamed "struct pmu_gk20a" to "struct nvgpu_pmu" then moved to file "pmu.h" under folder "drivers/gpu/nvgpu/include/nvgpu/" - Included header file "pmu.h" to dependent file & removed "pmu_gk20a.h" include if its usage is not present. - Replaced "struct pmu_gk20a" with "struct nvgpu_pmu" in dependent source & header files. JIRA NVGPU-56 Change-Id: Ia3c606616831027093d5c216959c6a40d7c2632e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1479209 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu : GPC MMU ECC supportDavid Nieto2017-06-04
| | | | | | | | | | | | | | Adding support for handling of GPC MMU errors JIRA: GPUT19X-112 Change-Id: Iadeef017587e5dce3698026eef4ad94676c3c02b Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1490771 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: move debugfs code to linux moduleDeepak Nibade2017-06-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since all debugfs code is Linux specific, remove it from common code and move it to Linux module Debugfs code is now divided into below module specific files : common/linux/debug.c common/linux/debug_cde.c common/linux/debug_ce.c common/linux/debug_fifo.c common/linux/debug_gr.c common/linux/debug_mm.c common/linux/debug_allocator.c common/linux/debug_kmem.c common/linux/debug_pmu.c common/linux/debug_sched.c Add corresponding header files for above modules too And compile all of above files only if CONFIG_DEBUG_FS is set Some more details of the changes made - Move and rename gk20a/debug_gk20a.c to common/linux/debug.c - Move and rename gk20a/debug_gk20a.h to include/nvgpu/debug.h - Remove gm20b/debug_gm20b.c and gm20b/debug_gm20b.h and call gk20a_init_debug_ops() directly from gm20b_init_hal() - Update all debug APIs to receive struct gk20a as parameter instead of receiving struct device pointer - Update API gk20a_dmabuf_get_state() to receive struct gk20a pointer instead of struct device - Include <nvgpu/debug.h> explicitly in all files where debug operations are used - Remove "gk20a/platform_gk20a.h" include from HAL files which no longer need this include - Add new API gk20a_debug_deinit() to deinitialize debugfs and call it from gk20a_remove() - Move API gk20a_debug_dump_all_channel_status_ramfc() to gk20a/fifo_gk20a.c Jira NVGPU-62 Change-Id: I076975d3d7f669bdbe9212fa33d98529377feeb6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1488902 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Begin removing variables in struct gk20aAlex Waterman2017-05-30
| | | | | | | | | | | | | | | | | | | | | | Begin removing all of the myriad flag variables in struct gk20a and replace that with one API that checks for flags being enabled or disabled. The API is as follows: bool nvgpu_is_enabled(struct gk20a *g, int flag); bool __nvgpu_set_enabled(struct gk20a *g, int flag, bool state); These APIs allow many of the gk20a flags to be replaced by defines. This makes flag usage consistent and saves a small amount of memory in struct gk20a. Also it makes struct gk20a easier to read since there's less clutter scattered through out. JIRA NVGPU-84 Change-Id: I6525cecbe97c4e8379e5f53e29ef0b4dbd1a7fc2 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1488049 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add fifo ops get_mmu_fault_infoSeema Khowala2017-05-30
| | | | | | | | | | | | | | | | | | | | This is needed to take care of gp10b h/w header changes. gp10b changes as compared to legacy gpu chips -fault_info_fault_type field width is changed -fault_info_write field is removed -fault_info_access_type field is added -fault_info_engine_subid is removed -fault_info_client_type is added -fault_info_client field width has changed JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: Iebf28cc6c851830524049b67a71cd72fb4a28948 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1487319 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add enable_exceptions gr opsSeema Khowala2017-05-30
| | | | | | | | | | | | This is needed to enable chip specific gr exceptions JIRA GPUT19X-75 Change-Id: I5ca8d0e51d00947c3ab1675bb6331207def433a4 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1474851 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add chip specific sync point supportseshendra Gadagottu2017-05-26
| | | | | | | | | | | | | | Added support for chip specific sync point implementation. Relevant fifo hal functions are added and updated for legacy chips. JIRA GPUT19X-2 Change-Id: I9a9c36d71e15c384b5e5af460cd52012f94e0b04 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1258232 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Split stalling interrupt handlingTerje Bergstrom2017-05-26
| | | | | | | | | | | | | | | | | | | | | | Split handling of stalling interrupt to Linux specific chip agnostic and OS independent chip specific parts. Linux specific chip independent part contains handler for ISR and passing the control to a bottom half. It uses the new MC HALs intr_stall (query interrupt status), intr_pause (pause interrupts) and intr_resume (resume interrupts). MC HAL isr_stall now returns void and gets called in thread context and thus remove isr_thread_stall and replace the implementation with isr_stall. JIRA NVGPU-26 Change-Id: I206f330f6fc4a1f4def47c5f986585ac4080216d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1480243 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add and use VM init/deinit APIsAlex Waterman2017-05-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the VM init/de-init from the HAL and instead use a single set of routines that init/de-init VMs. This prevents code divergence between vGPUs and regular GPUs. This patch also clears up the naming of the routines a little bit. Since some VMs are used inplace and others are dynamically allocated the APIs for freeing them were confusing. Also some free calls also clean up an instance block (this is API abuse - but this is how it currently exists). The new API looks like this: void __nvgpu_vm_remove(struct vm_gk20a *vm); void nvgpu_vm_remove(struct vm_gk20a *vm); void nvgpu_vm_remove_inst(struct vm_gk20a *vm, struct nvgpu_mem *inst_block); void nvgpu_vm_remove_vgpu(struct vm_gk20a *vm); int nvgpu_init_vm(struct mm_gk20a *mm, struct vm_gk20a *vm, u32 big_page_size, u64 low_hole, u64 kernel_reserved, u64 aperture_size, bool big_pages, bool userspace_managed, char *name); void nvgpu_deinit_vm(struct vm_gk20a *vm); JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: Ia4016384c54746bfbcaa4bdd0d29d03d5d7f7f1b Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1477747 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Track also pushbuf get for watchdogKonsta Holtta2017-05-24
| | | | | | | | | | | | | | | Make the watchdog notice also fine-grained changes within a single pushbuffer - by tracking just the gpfifo get, the watchdog could wake when the channel hasn't really been stuck but processing a relatively large or slow pushbuf. Jira NVGPU-72 Change-Id: I15374eea5d9abc9d3725a79d0b960503237e478c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1485919 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: re-arrange parity countersDavid Nieto2017-05-24
| | | | | | | | | | | | | (1) Re-arrange the structure for parity counters reporting so multiple units can be managed JIRA: GPUT19X-84 Change-Id: If59a883dfe22d5a1d91a6d0ed2f5a6254434ffcb Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1485276 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move linux clk calls to tegra specific fileDeepak Nibade2017-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | clk_gm20b.c has number of calls specific to linux and tegra-soc environment In order to unify the driver, move all of those calls to tegra/linux specific file tegra/linux/clk.c All the clk_*() and tegra_dvfs_*() calls are now abstracted behind GPU's clock operations and shoule be accessed using g->ops.clk.<API> format Remove <linux/clk.h> and <soc/tegra/tegra-dvfs.h> from clk_gm20b.c Remove <linux/version.h> from clk_gm20b.c too since we only support k4.4 and higher version only Jira NVGPU-49 Change-Id: Ib26811e0423bbd3868b9a46e662b80a8ca088dc5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1483092 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove TEGRA_CLK_FRAMEWORK supportDeepak Nibade2017-05-24
| | | | | | | | | | | | | | CONFIG_TEGRA_CLK_FRAMEWORK is no longer supported hence remove this config and all the code that is protected with this config Jira NVGPU-49 Change-Id: Ica28019e0c99e95743216e005ba2fba20357b2d5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1483090 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: per-chip GPCCS exception supportDavid Nieto2017-05-24
| | | | | | | | | | | | Adding support for ISR handling of GPCCS exceptions JIRA: GPUT19X-83 Change-Id: Ia5550aac8f368d8915f6c94aa22478cacbb2bddc Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1480992 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add ioctls to get current timesliceThomas Fleury2017-05-24
| | | | | | | | | | | | | | | | | | Add the following ioctls - NVGPU_CHANNEL_IOCTL_GET_TIMESLICE for channel timeslice in us - NVGPU_TSG_IOCTL_GET_TIMESLICE for TSG timeslice in us If timeslice has not been set explicitly, ioctl returns the default timeslice that will be used when programming the runlist entry. Bug 1883271 Change-Id: Ib18fdd836323b1a2d4efceb1e27d07713bd6fca5 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1469040 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add GCC exception handling supportLakshmanan M2017-05-19
| | | | | | | | | | | | Add support for per-chip handling of GCC exception. JIRA GPUT19X-86 Change-Id: I76ea588dc76b5c821ae5b53529db6dd64b3a856a Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1485836 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Scrub gk20a_platform dependenciesTerje Bergstrom2017-05-18
| | | | | | | | | | | | | | Remove gk20a_platform dependencies from gk20a.h. This makes gk20a_platform a Linux platform specific data structure. Add #include for platform_gk20a.h in the source files that still depend on Linux. JIRA NVGPU-16 Change-Id: Ib098accd34a1f5066eb8680c387f9b178169f3f0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1463547 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add czf_bypass sysfs node for gp10bPeter Boonstoppel2017-05-17
| | | | | | | | | | | | | | | | | | | | | | | | | This change adds a new sysfs node to allow configuring CZF_BYPASS, to enable platforms with low context-switching latency requirements. /sys/devices/17000000.gp10b/czf_bypass Values: 0 - always 1 - lateZ (default) 2 - single pass 3 - never The specified value will apply only to newly allocated contexts. Bug 1914014 Change-Id: Ibb9a8e86089acaadaa7260b00eedec5c80762d6f Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1478567 (cherry picked from commit 3bc022cb385b53f698b04f218db535e8162e8c94) Reviewed-on: http://git-master/r/1473820 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use nvgpu_cond in channel workerTerje Bergstrom2017-05-16
| | | | | | | | | | | | | Change the channel worker to use nvgpu_cond instead of Linux wait queue. JIRA NVGPU-14 Change-Id: Iac856dca2acfa80065f5d2fd542cd2a6278333a4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1469850 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Lakshmanan M <lm@nvidia.com>
* gpu: nvgpu: Move can_railgate & railgate_delay to gk20aTerje Bergstrom2017-05-14
| | | | | | | | | | | | | Copy can_railgate and railgate_delay to struct gk20a at probe time, and access them from gk20a instead of platform_gk20a. JIRA NVGPU-16 Change-Id: I63d4f4aff7eb17a167775fd7982a1b548bbca3a5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1463543 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Introduce priv ring HAL and define ISRTerje Bergstrom2017-05-12
| | | | | | | | | | | | | | | Introduce a priv ring HAL and define ISR as the only function in it. Introduce a gp10b version of the ISR that writes error message to UART for every priv ring error, and leave the old chips with silent error handling. Bug 1846641 Change-Id: I73e38396205ac7bb7b8488b7fbca3ff67a3db3bb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1473696 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move secure_alloc to struct gk20aTerje Bergstrom2017-05-11
| | | | | | | | | | | | | | | | | | Move the function pointer for VPR page allocation to struct gk20a and use it from there. At the same time remove secure_page_alloc pointer and add a direct call to it in probe. Move platform_tegra.h as tegra/linux/platform_gk20a_tegra.h, as it's only declaring functions defined in platform_gk20a_tegra.c to other files in the same directory. JIRA NVGPU-16 Change-Id: I19ac9ee0b2f6734203ae32a1f51d67fd51aced9f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1473706 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: changes related to preemptionseshendra Gadagottu2017-05-10
| | | | | | | | | | | | | | Added function pointers to check chip specific valid gfx class and compute class. Also added function pointer to update ctx header with preemption buffer pointers. Bug 200292090 Change-Id: I8119ee082e2abb67186a8ac07088f8db7f410ba1 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1293502 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add flag gk20a->is_virtualTerje Bergstrom2017-05-04
| | | | | | | | | | | | | Instead of calling gk20a_gpu_is_virtual() which requires struct device pointer fill in flag gk20a->is_virtual and use that. JIRA NVGPU-16 Change-Id: I24382c041ee69940c703ca1ea7f5c667c5731cd1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1473707 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use nvgpu_thread for channel workerTerje Bergstrom2017-05-04
| | | | | | | | | | | | Use nvgpu_thread for channel worker. JIRA NVGPU-14 Change-Id: Idcb93d3096de06a1569dc3ea69890745b5805d67 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1472870 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
* gpu: nvgpu: Move ch_wdt_timeout to gk20aTerje Bergstrom2017-05-03
| | | | | | | | | | | | | Copy watchdog timeout from platform structure to gk20a and use it from gk20a. JIRA NVGPU-16 Change-Id: Iab70253a7f0e1d28f2e3209285b3f4c476ce9279 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1473705 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: interface layer for falconMahantesh Kumbar2017-05-03
| | | | | | | | | | | | | | | | - struct nvgpu_falcon to hold properties of falcon controller - falcon controller interface layer which establish access to required falcon controller HAL based on struct nvgpu_falcon member flcn_id & flcn_base parameter. - each falcon nvgpu_falcon struct initialized during init with id, base-address along with other properties at HAL. - Added defines related to flacon controller. Change-Id: Ia7777c01ecc542150ddd72f8603b7b4475522b58 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1467523 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add new flag support_pmu to gk20aTerje Bergstrom2017-05-02
| | | | | | | | | | | | | | Add new flag support_pmu to struct gk20a at probe time, and access it from gk20a instead of support_gk20a_pmu() which depends on struct device *. JIRA NVGPU-16 Change-Id: I721f1a532e949c98346086abdc2630a8df6eba7b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1463546 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move ptimer_src_freq to gk20aTerje Bergstrom2017-04-28
| | | | | | | | | | | | | Copy ptimer_src_freq to struct gk20a at probe time, and access it from gk20a instead of platform_gk20a. JIRA NVGPU-16 Change-Id: I92c1b83d6e2305a19eb2cd267b7dd8d97c1fdc44 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1463544 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move has_syncpts to gk20aTerje Bergstrom2017-04-26
| | | | | | | | | | | | | Copy has_syncpts to struct gk20a at probe time, and access it from gk20a instead of platform_gk20a. JIRA NVGPU-16 Change-Id: I50329e3a5141a62e6e9828e97ea0747abc1ce1ee Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1463545 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move aggressive_sync_destroy to gk20aTerje Bergstrom2017-04-24
| | | | | | | | | | | | | Copy aggressive_sync_destroy* to struct gk20a at probe time, and access it from gk20a instead of platform_gk20a. JIRA NVGPU-16 Change-Id: I6a1c04d85580cb62ab9a52bae08a0f99fe7cfef9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1463542 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Put debugfs dependencies inside #ifdefTerje Bergstrom2017-04-24
| | | | | | | | | | | | | | | | | | | Put all debugfs dependencies inside #ifdef CONFIG_DEBUG_FS. This includes some functions in allocators that were used only for debugging. Remove include of linux/debugfs.h on files that do not deal with debugfs. linux/debugfs.h implicitly included linux/fs.h, which we relied on. Add explicit include of linux/fs.h for all files where this is the case. Change-Id: I16feffae6b0e3a2edf366075cdc01ade86be06f9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1467897 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Move default_pri_timeout to gk20aTerje Bergstrom2017-04-24
| | | | | | | | | | | | | Copy default_pri_timeout to struct gk20a at probe time, and access it from gk20a instead of platform_gk20a. JIRA NVGPU-16 Change-Id: Ic361e6be59df73d9b627c97fdcff190b00dfe179 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1463541 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: ModeE perfbuffer feature developmentPeter Daifuku2017-04-19
| | | | | | | | | | | | | | | | | | perfbuf mapping fixes: - Allocate VM specifically for perfbuf use: using the PMU's results in mmu faults for larger buffers where 64k pages are used. - Make 4GB boundary check work for large address spaces - remove requirement to have allow_all flag set - track perfbuf ownership and clean up appropriately Bug 1880196 JIRA EVLR-1074 Change-Id: Ieee4eb17b64acf9b6ede37bf8e6a91892cda4a7e Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1460809 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move can_elpg to struct gk20aTerje Bergstrom2017-04-19
| | | | | | | | | | | | | Copy can_elpg to struct gk20a at probe time, and access it from gk20a instead of platform_gk20a. JIRA NVGPU-16 Change-Id: I497f58c17e0be44e3622e49dad2ba44ed78cffbf Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1463539 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move Linux kernel driver code to module.cTerje Bergstrom2017-04-18
| | | | | | | | | | | | | | | | Move Linux driver specific code to common/linux/module.c. This includes module initialization, power management, and interrupt functions. Move pci.c, pci.h and nvgpu_common.c under common/linux as they're Linux only files. JIRA NVGPU-16 Change-Id: If92b4dd78ebc0c2bbfa9fbca258e9552e4979b4b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1456162 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: missing power sensor detectionThomas Fleury2017-04-18
| | | | | | | | | | | | | | | | | Monitoring INA3221 is currently missing on some customer designs. Use PCI vendor/device ids and VBIOS version to identify such device, and set power_sensor_missing flag. This flag is subsequently used to skip power device and power policy programming in PMU. Bug 1903258 Change-Id: Ia6b5ce563b5cc3593e138635639025b830e4535e Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1460936 (cherry picked from commit 42f236c210931d28d2699858bb0663b91cf11046) Reviewed-on: http://git-master/r/1463104 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add wrapper nvgpu/kref.hDeepak Nibade2017-04-17
| | | | | | | | | | | | | Add wrapper header file nvgpu/kref.h. It #includes <linux/kref.h> in Linux. JIRA NVGPU-13 Change-Id: Ib8b002268b1960646986551ecb9f286e1e21e7f6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1463770 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use PMU ver to check ZBC support.Deepak Goyal2017-04-17
| | | | | | | | | | | | | | | | From Volta onwards, new DSS ZBC registers are added for ZBC feature and save/restore of new ZBC reglist is taken care by ctxsw firmware. Therefore, PMU should save ZBC reglist only for PRE-volta chips. JIRA GPUT19X-20 Change-Id: I7d92274208ca42cc77bf57ea3cc416b5ecf32842 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1460244 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-25 08:07:13 -0400