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path: root/drivers/gpu/nvgpu/gk20a/gk20a.c
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* video: tegra: host: gk20a: Remove duplicated codeTerje Bergstrom2015-03-18
| | | | | | | | | | Two calls to gk20a_init_gpu_characteristics() is not needed. GPU sim aperture was defined twice. Change-Id: Iaf78611717c55b1cae456358fcae2641ad552d9f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/383855 Reviewed-by: Automatic_Commit_Validation_User
* video: tegra: host: gm20b: Re-enable gm20b driverTerje Bergstrom2015-03-18
| | | | | | | Change-Id: I473d7ac712afc10bc255d57d441965556fa0e957 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/383840 Reviewed-by: Automatic_Commit_Validation_User
* video: tegra: host: gm20b: Implement gr opsTerje Bergstrom2015-03-18
| | | | | | | | | | | Implement gm20b specific gr ops. Bug 1387211 Change-Id: I4523311f1c155ba2d3403dcf222769f6817b2450 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/362415 Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
* video: tegra: host: t210: Fix opsPrashant Gaikwad2015-03-18
| | | | | | | | | Change-Id: I99deddd7323f9ee7f8de4a032296ceeaebd81a95 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/375310 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
* video: tegra: host: Read GPU arch earlyTerje Bergstrom2015-03-18
| | | | | | | | | | | | Read GPU architecture and implementation early. Bug 1387211 Change-Id: Iffc1aa013f28ec786b0325ae055d016cf004ee06 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/360237 (cherry picked from commit b7071920b90ff1b21a5d14039e609a95ba48bd64) Reviewed-on: http://git-master/r/359754
* video: tegra: gpu: provide generic ops interfaceAlex Waterman2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds an interface for the gk20a driver to have generic ops which are implemented by a chip specific HAL layer. The HAL layer is provided by the gpu_ops struct which defines function pointers for chip specific oeprations. This is necessary for supporting multiple chips with the same code base and minimal per chip hacking. Also, since much code is common except in the HW headers that are needed, the LTC common code is compiled by first including the necessary chip specific header(s) and then including the ltc common code file. This allows for easy updating of functions that are only different between chips as a result of register offset and field changes whereas the HAL provides the mechanism for functions that have actual semantic changes. Change-Id: I96f9a8350d34e7e101beb141d4521fab69dcfbae Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/360627 (cherry picked from commit fe90cad939cf979fc2516a96e5911bd8ab6fc457) Reviewed-on: http://git-master/r/362228 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* video: tegra: host: add gm20b platform dataKevin Huang2015-03-18
| | | | | | | | | | Bug 1387211 Change-Id: If093c1f64ed8f79099ea8f115db6c91177a5e3ef Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/359987 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* video: tegra: host: gk20a: GM20B characteristicsSami Kiminki2015-03-18
| | | | | | | | | | | | | This patch adds initial support for GM20B for GPU characteristics IOCTL. Bug 1392902 Change-Id: I55bfb7e087244eae1462d44319bd91c7c0901c2e Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/359227 Reviewed-by: Automatic_Commit_Validation_User
* video: tegra: host: gk20a: GPU characteristicsSami Kiminki2015-03-18
| | | | | | | | | | | | | | | | | | | This adds new IOCTL that provides information for the userspace for GPU characterization. Specifically, the following items are provided: GPU arch/impl/rev, number of GPCs, L2 cache size, on-board video memory size, num of tpc:s per gpc, and bus type. The primary user of the new IOCTL will be rmapi_tegra. Bug 1392902 Change-Id: Ia7c25c83c8a07821ec60be3edd018c6e0894df0f Reviewed-on: http://git-master/r/346379 (cherry picked from commit 0b9ceca5a06d07cc8d281a92b76ebef8d4da0c92) Reviewed-on: http://git-master/r/350658 Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
* gpu: nvgpu: Turn off scaling when not poweredSantosh Katvate2015-03-18
| | | | | | | | | | | | | | | | | | | | | This far the scaling has been disabled only when we suspend the system and therefore we unnecessarily keep gpu workers running even if the gpu itself would be railgated. This is not proper behaviour and it causes a race in suspend sequence. This patch reorders scaling disable to happen always when we turn off the GPU. Bug 200004860 Change-Id: Ief0bfd89378d5a7ced26c3ef29094dd5c378b01a Signed-off-by: Santosh Katvate <skatvate@nvidia.com> Reviewed-on: http://git-master/r/410443 (cherry picked from commit bcae65bea24be2a1e0abe42522d99ba70c94cbe2) Reviewed-on: http://git-master/r/413249 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Disable pm runtime on shutdownArto Merilainen2015-03-18
| | | | | | | | | | | | | | In some cases the gpu has still work pending while the device is being suspended. This patch forces pm runtime to be disabled for the device to avoid powering up the gpu unnecessarily. Bug 1515437 Change-Id: I4b57d72eb34e794f0457d7a074d26c9d096a13b3 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/411968 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
* gpu: nvgpu: Balance usage count on resume failTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | | If PM runtime resume fails, pm_runtime_get_sync() still increments the usage count. Balance the usage count by decrementing it on fail. Bug 200003289 Change-Id: I127d2697ff2601d4884a4ecfdec8ad50894bf7d0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/411285 (cherry picked from commit 736846ff999bb9d1ca3340fc02ab49f8c65c4145) Reviewed-on: http://git-master/r/411473 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Register as subdomain of host1xTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Add gk20a as a sub power domain of host1x. This enforces keeping host1x on when using gk20a. Bug 200003112 Change-Id: I08db595bc7b819d86d33fb98af0d8fb4de369463 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/407543 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
* gpu: nvgpu: Define module licenseArto Merilainen2015-03-18
| | | | | | | | | | | This patch adds missing license definition (GPL v2). Change-Id: I73d48dffd60eaab9517d09370875d51901853c4e Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/397590 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Request irq at probeTerje Bergstrom2015-03-18
| | | | | | | | | | Request irq at probe instead of at poweron. This allows investigating interrupt numbers across rail gating cycles. Change-Id: I6db4b3f1d865c6fbbd9d6a96c3df89617e169891 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/374859
* gpu: nvgpu: Disable IRQs after channel suspendArto Merilainen2015-03-18
| | | | | | | | | | | | | | Interrupts may be needed before we have actually silenced all channels. Few possible scenarios include channel recovery during teardown and sw method before the channels have been suspended. This patch modifies the teardown path so that we disable interrupts after the channels have been suspended. Change-Id: Ifc36dbb74b1d36bd88d1220fa50a53c4072df4d8 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/394599 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not dump top_fs_statusTerje Bergstrom2015-03-18
| | | | | | | | | Result of top_fs_status_r() is always constant. Do not dump it anymore. Change-Id: Ie1cfe872d70b2c3c8a7cef4df3870dacae8f8793 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/395208
* platform: tegra: move pm_domain to driversPrashant Gaikwad2015-03-18
| | | | | | | | Change-Id: I30baee4084399b8078232f31296c4d891a903d47 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/395123 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: gk20a: disable devfreq before gk20aPrashant Malani2015-03-18
| | | | | | | | | | | | | Ensure devfreq is disabled before shutting down gk20a, to prevent possible races with reading of gpu load, and the shutdown of gpu itself. Bug 1492913 Change-Id: I016fdba9515120fc6cf3e771f60c61b9bf2027cb Signed-off-by: Prashant Malani <pmalani@nvidia.com> Reviewed-on: http://git-master/r/394296 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gk20a: fix genpd nameShridhar Rasal2015-03-18
| | | | | | | | | | domain name should be different from device name. Change-Id: I6c7d6927d6fc5bada203d749f107c17043233501 Signed-off-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-on: http://git-master/r/392327 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* video: tegra: host: gk20a: reorder free_irqPrashant Malani2015-03-18
| | | | | | | | | | | | Free IRQs before the various subunits are suspended. This is to prevent potential races between the IRQ thread and the suspend routine. Bug 1437749 Change-Id: Iffef918feecae0b256be96efd02b01b2677c225d Signed-off-by: Prashant Malani <pmalani@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Export pde coverageArto Merilainen2015-03-18
| | | | | | | | | | This patch adds a field to the gpu capability ioctl to allow requesting the maximum VA a single PDE entry can hold. Bug 1456570 Change-Id: I5cf29c8816fa6ea396c36419e6821c27a805b8af Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: Add NVIDIA GPU DriverArto Merilainen2015-03-18
This patch moves the NVIDIA GPU driver to a new location. Bug 1482562 Change-Id: I24293810b9d0f1504fd9be00135e21dad656ccb6 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/383722 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-27 01:46:45 -0400