| Commit message (Collapse) | Author | Age |
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- Defined FALCON_ID_GSPLITE for GSP falcon.
- Created variable gsp_flcn of struct nvgpu_falcon
for GSP falcon & registered to falcon module to access
falcon functions.
- Created HAL file gsp_gv100.c/h for GSP.
- Modified Makefile & Makefile.sources files to include
gsp_gv100 HAL file.
- Enabled GSP falcon support for GV100 by registering
to common falcon module.
- Defined function gv100_gsp_reset() & assigned to
falcon reset as GSP engine reset.
- Updated falcon HAL init code not to return error
if requested falcon is not supported, instead log
the info and return non-error.
JIRA NVGPU-1160
Change-Id: Ice032cf443ae87254375265628b3c022f41544cd
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804551
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for calls to nvgpu_mutex_init and
improves related error handling.
JIRA NVGPU-677
Change-Id: I609fa138520cc7ccfdd5aa0e7fd28c8ca0b3a21c
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805598
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces by introducing the braces.
JIRA NVGPU-671
Change-Id: Iedac7d50aa2ebd409434eea5fda902b16d9c6fea
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797695
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fix violations where a boolean is used as an operand in bit-shift
operations and is interpreted as a numerical value.
JIRA NVGPU-649
Change-Id: I4494c3b69d0e53319331b47d0a4de0b3de279f4f
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1799322
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com>
Reviewed-by: Amulya Murthyreddy <amurthyreddy@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA rule-10.4 only allows arithmetic conversions on operands of the
same essential type category.
Fix violations where an arithmetic conversion is performed on enum and
non-enum types.
JIRA NVGPU-993
Change-Id: I5391bb670d68982e0b5af6600995f70fe0cb2ad3
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1792852
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This fixes errors due to single statement loop bodies
without braces, which is part of Rule 15.6 of MISRA.
This patch covers in gpu/nvgpu/gk20a/
JIRA NVGPU-989
Change-Id: I2f422e9bc2b03229f4d2c3198613169ce5e7f3ee
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1791019
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-Renamed "struct pmu_queue" to "struct
nvgpu_falcon_queue" & moved to falcon.h
-Renamed pmu_queue_* functions to flcn_queue_* &
moved to new file falcon_queue.c
-Created ops for queue functions in struct
nvgpu_falcon_queue to support different queue
types like DMEM/FB-Q.
-Created ops in nvgpu_falcon_engine_dependency_ops
to add engine specific queue functionality & assigned
correct HAL functions in hal*.c file.
-Made changes in dependent functions as needed to replace
struct pmu_queue & calling queue functions using
nvgpu_falcon_queue data structure.
-Replaced input param "struct nvgpu_pmu *pmu" with
"struct gk20a *g" for pmu ops pmu_queue_head/pmu_queue_tail
& also for functions gk20a_pmu_queue_head()/
gk20a_pmu_queue_tail().
-Made changes in nvgpu_pmu_queue_init() to use nvgpu_falcon_queue
for PMU queue.
-Modified Makefile to include falcon_queue.o
-Modified Makefile.sources to include falcon_queue.c
Change-Id: I956328f6631b7154267fd5a29eaa1826190d99d1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776070
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In the current code, gk20a.h includes io.h which gets directly included
in a lot of other files. io.h contains methods which uses a struct
gk20a as a parameter leading to a circular dependency between io.h
and gk20a.h. This can be mitigated by removing io.h from gk20a.h as
part of larger effort to moving gk20a.h to nvgpu/gk20a.h
JIRA NVGPU-597
Change-Id: I93e504fa9371b88152737b342a75580c65e8f712
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1787316
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-Created common falcon function nvgpu_flcn_bl_bootstrap() to
bootstrap falcon bootloader
-Created HAL gk20a_falcon_bl_bootstrap() which does actual
bootloader bootstrap by fetching parameters and loading
code/parameters as needed.
-Created HAL ops bl_bootstrap under nvgpu_falcon_ops.
-Created struct nvgpu_falcon_bl_info to hold info required
for bootloader to pass to common function
-Removed falcons bootstrap code in multiple file & made
changes to fill struct nvgpu_falcon_bl_info & call
nvgpu_flcn_bl_bootstrap().
Change-Id: Iee275233915ff11f9afb5207ac0c3338ca9dacc1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756104
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Add methods to read/write falcon mailbox
at interface layer
- Created falcon mailbox read/write HAL
- Added HAL methods to read/write mailbox
- Added macro to get next block based on address
- Added macro to get IMEM tag using IMEM address
- Added ucode header format
Change-Id: I879b1df4538d403cac40fd4ed6e723190f62922c
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
(cherry picked from commit 30e8b76a7be9d9e6d8225bdc08e441f408692f63)
Reviewed-on: https://git-master.nvidia.com/r/1509469
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Added "nvgpu_flacon nvdec_flcn" member to gk20a
- Added base address & flacon id of NVDEC falcon
- Included nvdec falcon to access common falcon code
- Enabled nvdec falcon support for GP106
- Disabled nvdec falcon support for iGPU
- Made call to enable nvdec falcon support if supported
Change-Id: Ia928d082275a720e4e8c6852384e489c8ec444f8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
(cherry picked from commit 3d80aeff295bad8365af6022555ad151f1a32cf6)
Reviewed-on: https://git-master.nvidia.com/r/1564305
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- timers and bug header files should be
included directly. Linux maybe getting
it via indirect includes. Also, QNX
requires non-static function to be
declared explicitly.
Change-Id: I2458654f535d8079347e4a0be744530f56388238
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577527
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
Tested-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Change license of OS independent source code files to MIT.
JIRA NVGPU-218
Change-Id: I1474065f4b552112786974a16cdf076c5179540e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1565880
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Added falcon interface/HAL for IMEM-copy-from
to read data from IMEM from given location with requested
size
-Added falcon interface to print data of IMEM/DMEM
from given location with requested size using falcon HAL.
JIRA NVGPU-105
Change-Id: I84cf7b5769b84a2baee2c7e65027539598ec1295
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514536
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- Added support to dump flacon controller status
- Method to print recent PC history to know call trace
- Method to dump IMBLK info
- Updated falcon hw header files to include
registers of PC trace & IMBLK
JIRA NVGPU-105
Change-Id: Id4aaafd87113d47e552afb21b87f8b087d36004e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1515371
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
falcon sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: Ib1aaaa248b079bb591ccfada3382b689452de0e9
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514012
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- Added falcon interface/HAL to bootstrap
falcon by taking boot vector as parameter
- Replaced falcon bootstrap code in multiple
files with nvgpu_flcn_bootstrap() method
JIRA NVGPU-102
Change-Id: I4324824c50c6196d8b7ecf981f815ec778da2fd9
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1513643
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- Added falcon interface/HAL copy to IMEM method
- Deleted copy to IMEM code & then replaced with
nvgpu_flcn_copy_to_imem() in multiple files
- Code cleanup
JIRA NVGPU-117
Change-Id: Ic47197ef7dc449e5bf1f418ac02598500c96da21
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1513273
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Added nvgpu_flcn_clear_halt_intr_status() to
Wait for halt interrupt status clear by
clear_halt_interrupt_status() HAL within timeout
- Added gk20a_flcn_clear_halt_interrupt_status()
to clear falcon controller halt interrupt status
- Replaced flacon halt interrupt clear with
nvgpu_flcn_clear_halt_intr_status() method
NVGPU JIRA-99
Change-Id: I762a3c01cd1d02028eb6aaa9898a50be94376619
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1511333
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- Updated falcon controller HAL to support SEC2 falcon
& used "is_falcon_supported" flag to know the support on chip.
- Created falcon HAL flcn_gp106.c/h under gp106 to enable
support for SEC2 & inherited gk20a flcn support.
- Deleted SEC2 falcon related methods to make use of
generic flacon controller methods for SEC2.
- GP106 SEC2 code cleanup
NVPU JIRA-99
Change-Id: I846e8015ed33554b3d8a45795314f1d28eee482f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1510200
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- nvgpu_pmu_reset() as pmu reset for
all chips & removed gk20a_pmu_reset() &
gp106_pmu_reset() along with dependent
code.
- Created ops to do PMU engine reset & to
know the engine reset status
- Removed pmu.reset ops & replaced with
nvgpu_flcn_reset(pmu->flcn)
- Moved sec2 reset to sec2_gp106 from
pmu_gp106 & cleaned PMU code part of sec2.
JIRA NVGPU-99
Change-Id: I7575e4ca2b34922d73d171f6a41bfcdc2f40dc96
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1507881
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- replace usage of pmu_copy_to_dmem() with
nvgpu_flcn_copy_to_dmem()
- delete nvgpu_flcn_copy_to_dmem()
JIRA NVGPU-99
Change-Id: I9bb5837556e144521b181f9e15731beee08b435a
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1506577
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Added falcon interface/HAL copy to DMEM
method.
JIRA NVGPU-99
Change-Id: I783f8046e96d9e47091afb943697256c289ebab6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1506576
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Added interface/HAL method for falcon
to support copy from dmem
- Method to read dmem size
- Method to check error on input parameters
JIRA NVGPU-99
Change-Id: Id27b2b7f4f338196fc3b187555718543445d35bd
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1506525
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- set nvgpu_flcn_reset() to point to gk20a_pmu_reset()
- set PMU interrupt using nvgpu_flcn_enable_irq()
- replace pmu_idle with nvgpu_flcn_wait_idle()
JIRA NVGPU-57
Change-Id: I50d0310ae78ad266da3c1e662f1598d61ff7abb6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1469478
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Added flacon reset dependent interface & HAL
methods to perform falcon reset.
- method to wait for idle
- method to reset falcon
- method to set irq
- method to read status of CPU
- Updated falcon ops pointer to point gk20a
falcon HAL methods
- Added members to know support of falcon
& interrupt.
- Added falcon dependency ops member to support
flacon speicifc methods
JIRA NVGPU-99
JIRA NVGPU-101
Change-Id: I411477e5696a61ee73caebfdab625763b522c255
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1469453
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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mark functions local to the file as static
fixing errors in volt and flcn modules.
Bug 200299572
Change-Id: Ibacbd83649fee3066a90694a3df90bb909b24aa5
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1475357
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Assign base address for falcon based on falcon id.
- Init mutex for falcon
- Init ops with NULL
Change-Id: I9efee5c2b15106c7dfc6e55c996f62c7f7b85fc2
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1468452
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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