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Add support for chip engine specific error counters
JIRA: GPUT19X-82
Change-Id: I1b2686bd58c2d4e060a0a79c6b9e505811490a90
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1490824
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Adding support for handling of chip specific ECC memory errors
JIRA: GPUT19X-112
Change-Id: I1c04ac1d5233c332b300540eade1b73527c46ff7
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1489020
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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(1) Re-arrange the structure for parity counters reporting so multiple
units can be managed
JIRA: GPUT19X-84
Change-Id: If59a883dfe22d5a1d91a6d0ed2f5a6254434ffcb
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1485276
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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