| Commit message (Collapse) | Author | Age |
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CONFIG_TEGRA_CLK_FRAMEWORK is no longer supported
hence remove this config and all the code that is
protected with this config
Jira NVGPU-49
Change-Id: Ica28019e0c99e95743216e005ba2fba20357b2d5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1483090
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Added GPCPLL poweron voltage field to GPU clock structure. Initialized
it differently for GPCPLL revisions B1 and C1.
Bug 1924194
Change-Id: Ide7a08445afd3ab9aea21f75871b750f45c02c99
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1481263
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
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Set GPC PLL id in Tegra platform probe, to match Tegra SoC.
Bug 1851797
Bug 1867980
Change-Id: Ie6d2625a0009bcb96511aeda8c5af4734cf04929
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1461698
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Instead of using Linux APIs for mutex and spinlocks
directly, use new APIs defined in <nvgpu/lock.h>
Replace Linux specific mutex/spinlock declaration,
init, lock, unlock APIs with new APIs
e.g
struct mutex is replaced by struct nvgpu_mutex and
mutex_lock() is replaced by nvgpu_mutex_acquire()
And also include <nvgpu/lock.h> instead of including
<linux/mutex.h> and <linux/spinlock.h>
Add explicit nvgpu/lock.h includes to below
files to fix complilation failures.
gk20a/platform_gk20a.h
include/nvgpu/allocator.h
Jira NVGPU-13
Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1293187
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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JIRA DNVGPU-164
Adding export functions to gk20a and gk20a_clk structure
Change-Id: Ia448f17a6c456139544c1d36a3e17ceec0edd2f6
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1239465
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1268000
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Change-Id: I354d4bbddb2aba2a1a668cc0401437f1e2403b79
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1259495
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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Register gpcclk with Common Clock Framework to expose GPCPLL frequency
control
Bug 200233943
Change-Id: Id6f7bbaca15f22157b91b092c2a035af933fa71e
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1236979
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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It attaches the neccesary namemap structures to the clock struct so we can enumerate the clock domains in the debugfs code in nvgpu-t18x.
the other is to add an accessor for the fields.
JIRA DNVGPU-98
Change-Id: I6e5c6e763b2b88daa1995f4136a9a7b33ea25b17
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1199083
Reviewed-on: http://git-master/r/1204016
(cherry picked from commit b9d95a45791b93ddc010d1aeddbe798d2a9705d4)
Reviewed-on: http://git-master/r/1227910
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Specified locking timeout and IDDQ exit delay as GK20A PLL parameters,
and used this data instead of hard-coded numbers.
Change-Id: I59e16ed11fdba6911f2751195d182e68aed96851
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/735481
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Added delays definitions to GPCPLL parameters structure:
- locking timeout delay (applied to locking in fixed frequency mode and
to PLL dynamic ramp in any mode)
- lock delay for GPCPLL NA mode
- IDDQ exit delay in any mode
Specified delay parameters for GM20B PLL, and used this data instead of
hard-coded numbers.
Change-Id: I63ce0abc9ee900c36ec34b8641513db3cbb6f7d5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/732094
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Do not build clock code if TEGRA_CLK_FRAMEWORK is not defined. Also
make GK20A_DEVFREQ depend on TEGRA_CLK_FRAMEWORK, and build scaling
governor only if GK20A_DEVFREQ is enabled.
Bug 1567274
Change-Id: I6ea1462e7a110fb46c9d66ceda71167cff19699e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/562475
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To help remove the nvhost dependency from nvgpu, rename ioctl defines
and structures used by nvgpu such that nvhost is replaced by nvgpu.
Duplicate some structures as needed.
Update header guards and such accordingly.
Change-Id: Ifc3a867713072bae70256502735583ab38381877
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/542620
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Added basic support for GM20b GPCPLL noise-aware(NA) mode. In this
mode PLL internal DVFS mechanism is engaged, and output frequency is
scaled with voltage automatically. The scaling coefficients in this
commit are preliminary, pending characterization.
If NA mode is enabled, any frequency change is done under PLL bypass,
with no dynamic ramp allowed.
This commit kept NA mode disabled.
Bug 1555318
Change-Id: I8d96a10006155635797331bae522fb048d3dc4a0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/499488
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Moved detection of idempotent GPCPLL operations from set_pll_freq()
function to its callers, e.g., explicitly check when enable operation
is called on already enabled PLL, instead of passing same frequency
to set_pll_freq() in such case. Similarly explicitly check when disable
operation is called on already disabled PLL.
Also moved check for GPU powered on from set_pll_freq() to callers,
and skip call to set interface if not.
Added last GPCPLL configuration structure updated after successful
completion of set_pll_freq() function.
Bug 1450787
Change-Id: I8c14b8cab2a8548e98c9b2d223c465c68fb87b61
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/488027
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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Used GPU device name in clock get operation (instead of fixed name),
to make operation is common for GK20A and GM20B. Updated clock ids
in tegra clock framework accordingly.
Bug 1450787
Change-Id: Ifd5b9c3a6fd8db5b06e6dcd989285e8410794803
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/441711
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
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Made GK20A and GM20B clock operations static, since they are invoked
only via HAL interfaces.
Bug 1450787
Change-Id: Ia30218ad4244bd8790b5ef96d1963678d0ba39e1
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/441710
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
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Bug 1450787
Change-Id: Id7fb699d9129a272286d6bc93e0e95844440a628
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/440536
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Initialized GK20A clock debugfs after clock support
hardware and software are ready.
Bug 1450787
Change-Id: I8ec2ef303a84b9151b7ce209a1864f1729382a44
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/440973
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Removed unused, obsolete GK20A cooling device.
Bug 1450787
Change-Id: I5b02546d0405dd518ec841d903e650a8d38db8f2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/437942
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Used 1kHz resolution (instead of 1 MHz) for GPCPLL programming:
limits specifications, calculating GPCPLL settings, storing target
frequency values, and proving output from debug monitor. Updated
comments in clock header to properly reflect frequency units.
Bug 1450787
Change-Id: Ica58f794b82522288f2883c40626d82dbd794902
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/437943
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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This patch moves the NVIDIA GPU driver to a new location.
Bug 1482562
Change-Id: I24293810b9d0f1504fd9be00135e21dad656ccb6
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/383722
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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