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* gpu: nvgpu: pmgr: fix MISRA Rule 10.4 ViolationsSai Nikhil2018-09-27
| | | | | | | | | | | | | | | | | | | | | | | MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Id3b2c8ea1af1807087468c6978abfbfc85bee2ec Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809757 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: volt: fix MISRA Rule 10.4 ViolationsSai Nikhil2018-09-27
| | | | | | | | | | | | | | | | | | | | | | MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Ic9a911beb6d161df950ca85eb4813547603a8743 Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809751 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Update number of LUT entriesVaikundanathan S2018-09-20
| | | | | | | | | | | | | | CTRL_CLK_LUT_NUM_ENTRIES to 128 And fix build issues that appeared with 128 entries. Bug 2331655 Change-Id: If116bff14be9a1923e075f783fdb9a2e992208b8 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810493 Reviewed-on: https://git-master.nvidia.com/r/1813861 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: ctrl: MISRA Rule 21.2 header guard fixessmadhavan2018-09-18
| | | | | | | | | | | | | | | | | | | | | | | MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in ctrl by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: Ia7e5bf76dd2a8689e365bdeb27eac4b6e9ca4cfd Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1815657 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu:ps35: Clock domain changesVaikundanathan S2018-09-10
| | | | | | | | | | | | | | | | 1. PMU interface changes 2. Split PS3.0 and PS3.5 into two dev init functions. 3. Split construct and pmu_data_init to two funcitons. 4. Fixing GV100 impact on PS3.5 changes Change-Id: I46ba80325d4a249918edbe4cf868ddf47c778aa1 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1777739 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: Add dummy variables to accomodate PS3.5 structureVaikundanathan S2018-05-14
| | | | | | | | | | | | Change-Id: I437f2aba6a63de87033721fa9a29c565cf8f4256 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694546 Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vf inject changesVaikundanathan S2018-05-14
| | | | | | | | | | | | | | | | | | | | - Added vf change inject support for gv10x - Updated clk_pmu_vf_inject() to fill required data for pascal or volta vf change inject support - Added new ctrl clk interface for gv10x clk domain list - Added pmu interface for gv10x clk domain list & vf change inject request - Modified clk cmd, msg & RPC id's to match with chips_a_23609936 branch Bug 200399373 Change-Id: Ib9dc10073386f63bdfd92110c7ec3e09b1c484ce Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700746 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update clk_vin interface as per chips_aVaikundanathan S2018-05-04
| | | | | | | | | | | | | | | | clk_vin data structures updated as new calibration type (v20) is added. GP106 header does not have vin calibration type. Assuming V10 if calibration type is not V20. Add fuse calibration for V20 type. Bug 200399373 Change-Id: I9449de1ecb0d0873f3bc16f46660f93fab5b9eac Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1687591 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Port vf_point as per Chips_aVaikundanathan S2018-04-25
| | | | | | | | | | | | | | - Update PMU interface for vf_point Change-Id: I1c457026938025266a9325a93985d81fae3b9fa5 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1684286 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update vfe_var interface as per chips_a_23609936Tejal Kudav2018-04-25
| | | | | | | | | | | | | | | | | | | | | Changes made: 1. Fuse value can now be signed or unsigned. A new boolean added to check if the value is signed or not. 2. Masks added for dependent variable and equations 3. Restructing some data structures as per r384 JIRA NVGPUGV100-39 Change-Id: I7d9d1a55e26a06686f6253dedeb55925a32fd0ad Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1597761 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com> Tested-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update clk_fll interface as per chips_aTejal Kudav2018-04-12
| | | | | | | | | | | | | | | | | | | Two new members added to fll struct and code modified to support GV100 VBIOS NAFLL tables Add g->ops for getting vbios clk domains JIRA NVGPUGV100-39 Change-Id: Iaabea893d55d44a272e2bce2b1d525b122cd36f5 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594289 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Port clkdomain & clkprog from chips_aVaikundanathan S2018-04-12
| | | | | | | | | | | | | | | | | Update clk_domain_3x_prog, Add vbios hal entry for GV100 Add stubbing in place of boardobj_interfaces. Change-Id: Id880f303f40a07a6bf2a7f4f21d612124e89fe03 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1660697 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv10x volt policy boardobj changesMahantesh Kumbar2018-03-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added support for single rail multi step volt policy & below are the list of define & struct added/updated to support same. CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04, NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04, Updated struct vbios_voltage_policy_table_1x_entry, struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set, this holds members which help to config single rail multi step like delay between switch step, ramp up & ramp down step size in uv. - Added case to support SINGLE_RAIL_MULTI_STEP in volt_volt_policy_construct() based on boardobj type. - Added case to support SINGLE_RAIL_MULTI_STEP in volt_get_volt_policy_table() to read data from VBIOS table vbios_voltage_policy_table_1x_entry & extract to voltage_policy_single_rail_multi_step. - Added methods to forward single rail multi step data to PMU using below methods by assigning data read from VBIOS voltage_policy_single_rail_multi_step to nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set interface. volt_construct_volt_policy_single_rail_multi_step() volt_policy_pmu_data_init_sr_multi_step() volt_policy_pmu_data_init_single_rail() construct_volt_policy_single_rail() Change-Id: I17bc8c320777191611365ee63274c38ffe5ecbf7 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1660687 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv10x volt rail boardobj changesMahantesh Kumbar2018-03-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Created volt ops under pmu_ver to support volt_set_voltage, volt_get_voltage & volt_send_load_cmd_to_pmu. - Renamed volt load, set_voltage & get_voltage gp10x method names. - Added new volt load, set_voltage & get_voltage methods for gv10x using RPC & added code to handle ack in pmu_rpc_handler() along with struct rail_list changes. - Updated volt ops of gp106 & gv100 to point to respective methods. - Added member volt_dev_idx_ipc_vmin & volt_scale_exp_pwr_equ_idx to "struct nv_pmu_volt_volt_rail_boardobj_set" & "struct voltage_rail" made changes to update members as needed. - Added member volt_scale_exp_pwr_equ_idx to "struct vbios_voltage_rail_table_1x_entry" to read value from VBIOS table & update rail boardobj set interface. - Defines for volt RPC "NV_PMU_RPC_ID_VOLT_*" - Define struct's volt load, set_voltage & get_voltage to execute volt RPC. Change-Id: I4a41adcf7536468beaa8a73f551b1d608aabd161 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1659728 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix license of ctrlclkavfs.hTerje Bergstrom2017-11-29
| | | | | | | | | | | | | ctrlclkavfs.h was missing a license. Add MIT license text. Change-Id: I45a60e9c8cf378bcabfa4167a4f8859c5378a8eb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1606426 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Change license for common files to MITTerje Bergstrom2017-09-26
| | | | | | | | | | | | Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I1474065f4b552112786974a16cdf076c5179540e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1565880 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Don't recursively #include ctrlvolt.hTerje Bergstrom2017-01-06
| | | | | | | | | | | | | ctrlvolt.h #includes ctrlperf.h, which recursively #includes ctrlvolt.h without needing anything from it. Remove the #include to improve built time. Bug 200192125 Change-Id: I8c917533127e6d42aae6ad1401860c1f5d110d81 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1280345 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add thermal module supportLakshmanan M2016-11-03
| | | | | | | | | | | | | | | | | The following CL contains the following VBIOS thermal table parsing and PMU interface support. 1) Thermal device table 2) Thermal channel table JIRA DNVGPU-130 Change-Id: I3c1baca3fec2727b6d20aa6c007096372a6a3efe Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1240631 (cherry picked from commit 1d6fa9ab49b1c84e7f845de206821d879cbda356) Reviewed-on: http://git-master/r/1246204 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: update pwm source enum & VFE entryMahantesh Kumbar2016-10-30
| | | | | | | | | | | | | | JIRA DNVGPU-123 Change-Id: Ia28db5d645aa431f11dc8720bf1d08e6d756e20f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1227670 (cherry picked from commit 2c7f89ceef3f9173fefa44b1a959345744e66536) Reviewed-on: http://git-master/r/1244659 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: voltage changesMahantesh Kumbar2016-10-30
| | | | | | | | | | | | | | | | - added voltage interface & ctrl defines. JIRA DNVGPU-122 Change-Id: Ia1a4c655c3c5faa638cafcdc75bdfb0e3c3be54f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1222775 (cherry picked from commit 46ff4d54d3cc02d9f039091f09eea09a5d6c22ce) Reviewed-on: http://git-master/r/1244654 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add SW_THRESHOLD policy supportLakshmanan M2016-10-27
| | | | | | | | | | | | | | Added SW_THRESHOLD policy support for over power protection. JIRA DNVGPU-70 Change-Id: I021f47f234d42be15ddbfd02a22e9299fd486636 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1233051 (cherry picked from commit 301e0ac123a7a65a7f83e5615f3a89e55253a0bd) Reviewed-on: http://git-master/r/1241958 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add pmgr supportLakshmanan M2016-10-27
| | | | | | | | | | | | | | | | | | | | | This CL covers the following implementation, 1) Power Sensor Table parsing. 2) Power Topology Table parsing. 3) Add debugfs interface to get the current power(mW), current(mA) and voltage(uV) information from PMU. 4) Power Policy Table Parsing 5) Implement PMU boardobj interface for pmgr module. 6) Over current protection. JIRA DNVGPU-47 Change-Id: I620f4470aa704f1cc920e03947831440fbb0eb05 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1217176 (cherry picked from commit ed56743c2ac8dc325c75f85a82271d2d5ed8d96a) Reviewed-on: http://git-master/r/1241952 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix getstatus support for boardobjgrpVijayakumar2016-10-07
| | | | | | | | | | | | | | | | | | JIRA DNVGPU-118 move vidmem allocation for pmuboardobj to cmd specific functions and do a copy of data from pmu incase of getstatus. fixes for getstatus boardobjgrp implementation and added one #define for rail id to make getstatus of vf table more meaningful Change-Id: I366a022c13e51e823116ce2354794babc48981a2 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1209841 (cherry picked from commit 8c12599f801decc77bbc1acfd1937dfefb21f35e) Reviewed-on: http://git-master/r/1231839 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add dGPU clocks supportVijayakumar Subbu2016-09-29
JIRA DNVGPU-45 Change-Id: I237ce81e31b036c05c82d46eea8694ffe1c2e3df Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1205849 (cherry picked from commit 9a4006f76b75a8ad525e7aa5ad1f609aaae49126) Reviewed-on: http://git-master/r/1227256 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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