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* gpu: nvgpu: replace tsgid input variable with pointer to a struct tsg_gk20aDebarshi Dutta2019-02-11
| | | | | | | | | | | | | | | | | | | | | | replace tsgid with a pointer to a struct tsg_gk20a in the function gk20a_fifo_tsg_abort(). gk20a_fifo_tsg_abort needs to enumerate through all the channels within the tsg as well as pass the tsg pointer to other functions, qualifying the need to use a pointer instead as an input parameter. Jira NVGPU-1461 Change-Id: I59cec05d5d778f733d0c3e9ffadf46e74e249080 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1956567 (cherry picked from commit e5bebd880f28fe719c5e01e165fb189e7cafee01 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2013724 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add safe channel id lookupKonsta Holtta2019-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add gk20a_channel_from_id() to retrieve a channel, given a raw channel ID, with a reference taken (or NULL if the channel was dead). This makes it harder to mistakenly use a channel that's dead and thus uncovers bugs sooner. Convert code to use the new lookup when applicable; work remains to convert complex uses where a ref should have been taken but hasn't. The channel ID is also validated against FIFO_INVAL_CHANNEL_ID; NULL is returned for such IDs. This is often useful and does not hurt when unnecessary. However, this does not prevent the case where a channel would be closed and reopened again when someone would hold a stale channel number. In all such conditions the caller should hold a reference already. The only conditions where a channel can be safely looked up by an id and used without taking a ref are when initializing or deinitializing the list of channels. Jira NVGPU-1460 Change-Id: I0a30968d17c1e0784d315a676bbe69c03a73481c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1955400 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 7df3d587502c2de997dfbe8ea8ddc114d0a0481e in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2008515 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gm20b: clear priv intr in log_pending_intrsSeema Khowala2019-02-02
| | | | | | | | | | | | | | | | | | | | | Clear pending priv interrupt in log_pending_intrs. Priv ring errors have not been cleaned up in gm20b. It is ok to just clear it. Bug 200477291 Bug 200486293 Change-Id: I850a261828a9d49b6b4a82d75f5347acbc17b0fe Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2008818 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove unnecessary error print of falcon queueMahantesh Kumbar2018-12-26
| | | | | | | | | | | | | | | | | | | | | | | | | -For queue full there is pmu_dbg message & returned with EAGAIN error to end caller for retry, so intermediate error message is not correct print for queue full. Bug 200477085 Bug 200477931 Bug 200475876 Change-Id: I1109f15d0815f4ab2d8f8ca303db447d856f372c Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> (cherry picked from commit I263f66f7a8d8f1b98985f32f9daa49b09309c359) Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1979935 Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Tested-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com>
* nvgpu: pmu: cleanup init thread on destroyPeter Daifuku2018-12-15
| | | | | | | | | | | | | | | | | | | | | | | | In nvgpu_kill_task_pg_init(), call nvgpu_thread_join() if the init thread is no longer running in order to reclaim thread resources. Bug 2452799 JIRA ESRM-437 Change-Id: Id9c67f689027f00039ac2df226ee9c28ad89dd1d Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1967983 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1970058 Reviewed-by: Shmuel Ungerfeld <sungerfeld@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Tested-by: Shmuel Ungerfeld <sungerfeld@nvidia.com> Reviewed-by: Rahul Jain (SW-TEGRA) <rahuljain@nvidia.com>
* gpu: nvgpu: disable/clear PMU IRQs on power offSagar Kamble2018-11-20
| | | | | | | | | | | | | | | | | | | | | | While tearing down PMU state during power off, nvgpu doesn't disable the PMU interrupts. Disable them unconditionally. Bug 200457485 Change-Id: Ia2462d879c1e7bbb4b5e8295ce211c38567c13e5 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1939025 Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1951361 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: Bibek Basu <bbasu@nvidia.com>
* gpu: nvgpu: Fix comment in priv_cmd_buf allocationAlex Waterman2018-11-16
| | | | | | | | | | | | | | | | | | | Update the comment to fix obvious issues and describe the new allocation logic. Bug 2327792 Change-Id: Ica0dd4159467e3023cc487a2bf9f525db3ad76e6 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1831096 (cherry picked from commit c64f9432b13d47a791220578e823efcae4fe2a80) Reviewed-on: https://git-master.nvidia.com/r/1949221 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: James Norton <jnorton@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Make priv_cmd_buf honor num_in_flight jobsAlex Waterman2018-11-16
| | | | | | | | | | | | | | | | | | | | | | If num_in_flight jobs is set use that to determine the proper size of the priv_cmd_buf. If num_in_flight is not set then use the original logic: the priv_cmd_buf is sized based on a worst case assumption for the GPFIFO. Also clean up MISRA issues. Bug 2327792 Change-Id: Ie192caeb6cc48fdcac57e5cbb71c534aeaf46011 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1831095 (cherry picked from commit b9ec592f1d3ce23db736ff9c36eab994fc86ed46) Reviewed-on: https://git-master.nvidia.com/r/1949220 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: James Norton <jnorton@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use deterministic flag to decide pre-allocAlex Waterman2018-11-16
| | | | | | | | | | | | | | | | | | | | | | Instead of using num_inflight_jobs to determine whether to pre-alloc resources for a channel use the c->deterministic flag and the number of inflight jobs field. Non-determinsitic channels do not require pre-alloced resources and deterministic channels with 0 in flight jobs (i.e no kernel job tracking, AKA fast path sumits) also do not require pre-alloced resources. Bug 2327792 Change-Id: I7e8eb0478c22e005ca2c46c555415afa0ded0be1 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1850123 (cherry picked from commit 05ec7b80ebeabbc27d369ebd88dfe511c30d1bad) Reviewed-on: https://git-master.nvidia.com/r/1949219 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: James Norton <jnorton@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove VPR HALs from dGPUsDeepak Nibade2018-09-29
| | | | | | | | | | | | | | | | | | | | gops.fb.dump_vpr_wpr_info() accesses both VPR and WPR registers. Split this into two different HALs gops.fb.dump_vpr_info() and gops.fb.dump_wpr_info() Also unset HALs accessing VPR registers on dGPUs We don't support VPR on dGPUs Remove fb_mmu_vpr_info_r() register and all its accessors from dGPU headers Bug 2173122 Change-Id: I5b2712f8c5389e422a84c375a7e836add48bfd1c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1850947 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Update PMU ucode version.Deepak2018-09-28
| | | | | | | | | | | | | | | | | | | | | | | | PMU ucode is updated to use acrlib from t19xbringup branch. We are seeing build issues due to incompatibility with acrlib from tegra_acr branch. CTX_DMA aperture to be used for loading LS falcons needed update in the local acrlib. Bug 2400729. Change-Id: Iad00a332acfac307c389bde504893a87abaf7460 Signed-off-by: Deepak <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1849182 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: SEC2 RTOS support s/w initMahantesh Kumbar2018-09-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Created struct nvgpu_sec2 to hold members related to SEC2-RTOS ucode support in header file sec2.h -Created nvgpu_sec2 variable under struct gk20a. -Created NVGPU_SUPPORT_SEC2_RTOS enable flag to enable SEC2 RTOS support. -Defined method nvgpu_init_sec2_support() to init SEC2 RTOS support by performing s/w setup like mutex-init, sequence-init & add support for remove_support. -Defined method nvgpu_sec2_destroy() to deinit SEC2 RTOS support. -Added nvgpu_init_sec2_support()/nvgpu_sec2_destroy() as part gk20a_finalize_poweron()/gk20a_prepare_poweroff() sequence based on NVGPU_SUPPORT_SEC2_RTOS enable flag -Assigned g->sec2->flcn to point to g->sec2_flcn to access falcon. -Made Makefile changes to include sec2.c to build JIRA NVGPUT-80 Change-Id: Icdc8c25994e305427ad465a5a20e9ce533759a9e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1791955 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move FB reset to MC unitTerje Bergstrom2018-09-27
| | | | | | | | | | | | FB reset is done by accessing MC register. Move the code to MC unit. JIRA NVGPU-954 Change-Id: I1636887af805f016da5490af65e808f9ac015cde Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1823385 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add MC APIs for reset masksTerje Bergstrom2018-09-27
| | | | | | | | | | | | | | Add API for querying reset mask corresponding to a unit. The reset masks need to be read from MC HW header, and we do not want all units to access Mc HW headers themselves. JIRA NVGPU-954 Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1823384 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Standardize HAS_SYNCPOINTs checkAlex Waterman2018-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nvgpu uses many ways to check if sync points are enabled. The four ways used to be: platform->has_syncpoints g->has_syncpoints nvgpu_is_enabled(g, NVPGU_HAS_SYNCPOINTS) gk20a_platform_has_syncpoints() This patch standardizes all usage to now be nvgpu_has_syncpoints() which is based on gk20a_platform_has_syncpoints() - just renamed to be general to nvgpu. All usage of the other forms have now been consolidated. However, under the hood nvgpu_has_syncpoints() does check the is_enabled flag. This flag is now set where g->has_syncpoints used to be set based on the platform data. The basic dependency chain is this: nvgpu_has_syncpoints -> NVGPU_HAS_SYNCPOINTS -> platform->has_syncpoints However, note: there are several places where syncpoints can be disabled if some other driver initialization fails (for ex. host1x). Also note that nvgpu_has_syncpoints() also considers a disable variable set by debugfs. Bug 2327574 Change-Id: Ia2375a80f5f2e27285e6175568dd13e6bb25fd33 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803975 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add support to load dbg/prod mem_unlock ucodeMahantesh Kumbar2018-09-27
| | | | | | | | | | | | | | | | | | | -Add support to load dbg/prod mem_unlock ucode based on debug Signal SCP_CTL_STAT_DEBUG_MODE. -Defined MEM_UNLOCK_PROD_BIN & MEM_UNLOCK_DBG_BIN to hold dbg/prod ucode names. JIRA NVGPUT-76 Change-Id: Ie282a281fe502ada31a69e3b3c734e9a3a725395 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1842880 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon engine EMEM queue supportMahantesh Kumbar2018-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | -Removed _dmem postfix to some functions which can be common for DMEM & EMEM queue, and made changes as needed. -Defined flcn_queue_push_emem() & flcn_queue_pop_emem() functions to to read/write queue data to/from EMEM -Defined flcn_queue_init_emem_queue() function to assign EMEM specific functions to support EMEM queue type. -Defined QUEUE_TYPE_DMEM to support DMEM based queue. -Defined QUEUE_TYPE_EMEM to support EMEM based queue. -Modified nvgpu_flcn_queue_init() to call queue type flcn_queue_init_dmem/emem_queue() function to assign its ops. JIRA NVGPU-1161 Change-Id: I06333fa318b7ca4137c977ad63f5a857e7b36cc8 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1841084 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon engine EMEM supportMahantesh Kumbar2018-09-27
| | | | | | | | | | | | | | | | | -Added HAL copy_from_emem & copy_to_emem to struct nvgpu_falcon_engine_dependency_ops data struct to point to engine specific EMEM access functions. -Added function nvgpu_flcn_copy_from_emem() & nvgpu_flcn_copy_to_emem() at interface layer to access EMEM using flacon engine EMEM HAL's. JIRA NVGPU-1161 Change-Id: Ifb72a617277e73f25f1772c969791b642585e7fb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807336 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: increase bootstrap allocator size to 512MDeepak Nibade2018-09-26
| | | | | | | | | | | | | | | | | | Bootstrap size of 256M is insufficient on some platforms, hence increase it to 512M Bug 2402730 Bug 200448236 Change-Id: I5f67e76db0e37d2044f5fc3c27014d6fda853abd Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1845051 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: QNX devg-nvrm crash fix.Amurthyreddy2018-09-26
| | | | | | | | | | | | | | | | | | | | | | | | Input paran VM Will be used to get PTE size for GVA spaces and it can be NULL if buddy_allocator initialization is not for GVA space. As part of recent changes VM was being accessed for non GVA space case and for that VM was NULL, causing the crash. In this fix added a prior check and VM will be accessed only if input flag is set to GPU_ALLOC_GVA_SPACE. Bug 200452730 Change-Id: I9dcb1f2bd5e639c37a7152b99453bb5b46fe4087 Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1842530 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Prateek Sethi <prsethi@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: GPU_NEXT pmu version updateMahantesh Kumbar2018-09-26
| | | | | | | | | | | | | | | | | | PMU version update for ucode CL https://git-master.nvidia.com/r/1844810 JIRA NVGPUT-85 Change-Id: I87ca4d06fdae0fb6977e7aaf3cba7ded00d23ac1 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1844863 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename PMU perf unit to pmu_perfDeepak Nibade2018-09-25
| | | | | | | | | | | | | | | | Move all files under perf/* to pmu_perf/* since pmu_perf is logically appropriate name for PMU's perf unit Rename perf.c to pmu_perf.c Also rename the HAL from gops.perf to gops.pmu_perf Jira NVGPU-1102 Change-Id: I79e73b8b102ddf6b49783c2f38d861cd43b0b4c6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1819301 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move header location of gk20a.hDebarshi Dutta2018-09-25
| | | | | | | | | | | | | Update header path of gk20a.h in files present in common/ to <nvgpu/gk20a.h> Jira NVGPU-597 Change-Id: I3431dae93ada9bd561454c89a0b99c5292ab4a8d Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1832024 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: common: MISRA Rule 21.2 header guard fixessmadhavan2018-09-25
| | | | | | | | | | | | | | | | | | MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in common directory by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: Idf10f6b179cfd96bfb8ab8e9e2bf79c26591905d Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809086 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add GSP falcon supportMahantesh Kumbar2018-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | - Defined FALCON_ID_GSPLITE for GSP falcon. - Created variable gsp_flcn of struct nvgpu_falcon for GSP falcon & registered to falcon module to access falcon functions. - Created HAL file gsp_gv100.c/h for GSP. - Modified Makefile & Makefile.sources files to include gsp_gv100 HAL file. - Enabled GSP falcon support for GV100 by registering to common falcon module. - Defined function gv100_gsp_reset() & assigned to falcon reset as GSP engine reset. - Updated falcon HAL init code not to return error if requested falcon is not supported, instead log the info and return non-error. JIRA NVGPU-1160 Change-Id: Ice032cf443ae87254375265628b3c022f41544cd Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1804551 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move tsg code to commonKonsta Holtta2018-09-24
| | | | | | | | | | | | | | | tsg_gk20a.c doesn't depend on any specific hardware, so move it to the common directory. Rename the posix tsg file to posix-tsg.c. Jira NVGPU-967 Change-Id: I6e8908a8f6cf43132db8dffe3a99e424e4f764b1 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1821509 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add HALs to implement pdb cache WARDeepak Nibade2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | We have a h/w bug on some chips and we need to support below additional HALs to implement a s/w WAR gops.fifo.init_pdb_cache_war() gops.fifo.deinit_pdb_cache_war() gops.fb.apply_pdb_cache_war() Add new API nvgpu_init_mm_pdb_cache_war() to initialize WAR sequence and call this from MM initialization and before setting up rest of the memory management units Deinitialize WAR while cleaning up MM support Add pdb_cache_war_mem member to gk20a to hold all the memory needed for the WAR Bug 200449545 Change-Id: Id2ac0d940c7881c7b0cf396413273c0f329a1a1f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1834901 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: read GPC mask from h/wDeepak Nibade2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_ctrl_ioctl_gpu_characteristics() we right now just calculate GPC mask in s/w and return to user space But this could give incorrect result as any GPC could be floorswept in h/w Add gops.fuse.fuse_status_opt_gpc() to read GPC floorsweep status from fuse Add gops.gr.get_gpc_mask() to get actual GPC mask from h/w Set these HALs only for dGPUs right now. Fuse register to read GPC mask is not yet supported in simulation and hence simulation boot fails These HALs will be set for iGPU once simulation issue is resolved Use gops.gr.get_gpc_mask() if it is defined in gk20a_ctrl_ioctl_gpu_characteristics() to send the actual GPC mask to user space Jira NVGPUT-132 Change-Id: I3b552de07883328fcfa41d4334ec0d777e04bdd3 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822811 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PMU init sequence changeMahantesh Kumbar2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | -Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c method nvgpu_init_pmu_support() -Modified nvgpu_init_pmu_support() to init required interface for PMU RTOS & does start PMU RTOS in secure & non-secure based on NVGPU_SEC_PRIVSECURITY flag. -Created secured_pmu_start ops under PMU ops to start PMU falcon in low secure mode. -Updated PMU ops update_lspmu_cmdline_args, setup_apertures & secured_pmu_start assignment for gp106 & gv100 to support modified PMU init sequence. -Removed duplicate PMU non-secure bootstrap code from multiple files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method to handle non secure PMU bootstrap, reused this method for need chips. JIRA NVGPU-1146 Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1818099 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: ACR code refactorMahantesh Kumbar2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Created struct nvgpu_acr to hold acr module related member within single struct which are currently spread across multiple structs like nvgpu_pmu, pmu_ops & gk20a. -Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members -Created struct hs_acr to hold ACR ucode specific members like bootloader data using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run. -Created acr ops under struct nvgpu_acr to perform ACR specific operation, currently ACR ops were part PMU which caused to have always dependence on PMU even though ACR was not executing on PMU. -Added acr_remove_support ops which will be called as part of gk20a_remove_support() method, earlier acr cleanup was part of pmu remove_support method. -Created define for ACR types, -Ops acr_sw_init() function helps to set ACR properties statically for chip currently in execution & assign ops to point to needed functions as per chip. -Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr function to alloc blob space. -Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde based on interfaces used to bootstrap ACR ucode. -Created function gm20b_bootstrap_hs_acr() function which is now common HAL for all chips to bootstrap ACR, earlier had 3 different function for gm20b/gp10b, gv11b & for all dgpu based on interface needed. -Removed duplicate code for falcon engine wherever common falcon code can be used. -Removed ACR code dependent on PMU & made changes to use from nvgpu_acr. JIRA NVGPU-1148 Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813231 GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: PMU cleanup for ACRMahantesh Kumbar2018-09-24
| | | | | | | | | | | | | | | | | | | | | - Removed ACR support code from PMU module - Deleted ACR related ops from pmu ops - Deleted assigning of ACR related ops using pmu ops during HAL init -Removed code related to ACR bootstrap & dependent code for all chips. JIRA NVGPU-1147 Change-Id: I47a851a6b67a9aacde863685537c34566f97dc8d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817990 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: increase sync-unmap timeout to 100msRichard Zhao2018-09-21
| | | | | | | | | | | | | | | | | | | - sync-unmap timeout was observed intermittently. so doubled the timeout value. - also check ref count after last round of sleep. The polling could succeed during the last sleep. - fix error print on timeout. Bug 200434475 Change-Id: If821dfaca9b86873711f436645523dc49a5eba34 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1828562 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove circular dependency between hal.c and gk20a/ddutta2018-09-21
| | | | | | | | | | | | | | | | | gk20a/hal.c depends on HAL init functions in all chips. But all chips also depend on gk20a. That creates a circular dependency. In order to solve the above, move gpu_init_hal and gk20a_detect_chip to common/init/hal_init.c. These methods are declared in include/nvgpu/hal_init.h. Also, the above methods are renamed to nvgpu_init_hal and nvgpu_detect_chip respectively. Jira NVGPU-613 Change-Id: Ib0df90287d4491571e4751475739b75fabd1041b Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1827576 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix some dma.[ch] MISRA violationsAlex Waterman2018-09-20
| | | | | | | | | | | | | This doesn't correspond to a specific rule; it just cleans up the violations introduced by http://git-master/r/1799807. JIRA NVGPU-990 Change-Id: Ia20af754da9ad60f81d58ba00bf781a8c441827b Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1804887 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move lts intr servicing to separate functionsDeepak Nibade2018-09-20
| | | | | | | | | | | | | | | | | | | | | We right now service LTS interrupts as part of LTC interrupt service routine Separate out the LTS interrupt handling in separate functions e.g. gp10b_ltc_lts_isr() for gp10b and gv11b_ltc_lts_isr() for gv11b gv11b_ltc_lts_isr() now calls gp10b_ltc_lts_isr() to service legacy LTS interrupts instead of calling gp10b_ltc_isr() directly Bug 2216662 Jira NVGPU-767 Change-Id: Ia8499feca83f67ac455cee311edf32390acb83b8 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1821430 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix race condition in pmu_rpc_handlerThomas Fleury2018-09-20
| | | | | | | | | | | | | | | | | There was a race condition between pmu_rpc_handler and nvgpu_pmu_rpc_execute. The later could free the buffer before pmu_rpc_handler could access related data. Added explicit field in rpc_payload, so that nvgpu_pmu_rpc_execute can wait until pmu_rpc_handler completes. Bug 2331655 Change-Id: Ic2653524159eff10504b9c2625b5241610b5f5f0 Reviewed-on: https://git-master.nvidia.com/r/1811299 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817582 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Add GV10x perf eventVaikundanathan S2018-09-20
| | | | | | | | | | | | | | | In case of VFE update, schedule work to set P0 clocks. Added function nvgpu_clk_set_fll_clk_gv10x to update P0 clocks on perf event. Fixed MISRA issues caused by this excluding external functions and MACROs Bug 2331655 Change-Id: Id96c473092ee7f0b651413aefdd4b6f2f59e0b12 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808014 Reviewed-on: https://git-master.nvidia.com/r/1813881 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: minor fixes in channel_sync.cddutta2018-09-20
| | | | | | | | | | | | | | | | | | | | This patch comes as a follow up to commit 2517d59be282426eec7a97745b76d745ff36c388 containing minor fixes i.e. changing type of 'pos' to u32 instead of int and renaming syncpt_get_id to channel_sync_syncpt_get_id Jira NVGPU-1086 Change-Id: I8bd9271c20d88ff5f68ccfc48a0b533844bbcaaa Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1829832 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: common: MISRA 10.1 boolean fixesAmulya2018-09-19
| | | | | | | | | | | | | | | | Fix violations where a variable of type non-boolean is used as a boolean in gpu/nvgpu/common. JIRA NVGPU-646 Change-Id: I9773d863b715f83ae1772b75d5373f77244bc8ca Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807132 GVS: Gerrit_Virtual_Submit Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move channel_sync_gk20a.* to common directoryDebarshi Dutta2018-09-18
| | | | | | | | | | | | | | | | | | | | 1) Move channel_sync_gk20a.* from gk20a/ to common/ directory as they donot program any hardware registers. Also as an add-on rename channel_sync_gk20a.* to channel_sync.* and update the headers in required files. 2) Rename the struct gk20a_channel_sync to struct nvgpu_channel_sync. Also, corresponding syncpt and semaphore versions of the struct alongwith related methods are renamed by removing "gk20a" from their names and adding "nvgpu". 3) Add misra-c cleanups Jira NVGPU-1086 Change-Id: I4e0e21803ca3858dd7a5fc4d2454dba1f1bfcecd Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812594 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move FBPA interrupt HAL to MCTerje Bergstrom2018-09-13
| | | | | | | | | | | | | | | | FBPA interrupt is reported via a register in MC. Move the HAL dealing with that interrupt to MC. JIRA NVGPU-954 Change-Id: Ic2b8439e82788f851536bcbb5cba6580f4d5ee7e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813520 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move MC HAL to commonTerje Bergstrom2018-09-13
| | | | | | | | | | | | | | | | | | | | | | | Move implementation of MC HAL to common/mc. Also bump gk20a implementation to gm20b. gk20a_mc_boot_0 was used via a HAL, but we have only one possible implementation. It also has to be anyway called directly to detect which HALs to assign, so make it a true common function. mc_gk20a_handle_intr_nonstall was also used only in os/linux/intr.c so move it there. JIRA NVGPU-954 Change-Id: I79aedc9158f90d578db0edc17b714617b52690ac Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813519 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations (pd_cache.c)Alex Waterman2018-09-12
| | | | | | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. Fixes for all the pd_cache functions that use '__' prefixes. This was trivial: the '__' prefix was simply deleted. JIRA NVGPU-1029 Change-Id: Ia91dabe3ef97fb17a2a85105935fb3a72d7c2c5e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813643 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations (nvgpu_mem.c, mm.c)Alex Waterman2018-09-12
| | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. Handle the 21.2 fixes for nvgpu_mem.c and mm.c; this deletes the '__' prefixes and slightly renames the __nvgpu_aperture_mask() function since there's a coherent version and a general version. Change-Id: Iee871ad90db3f2622f9099bd9992eb994e0fbf34 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813623 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations (buddy_allocator.c)Alex Waterman2018-09-12
| | | | | | | | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. Fixes for the buddy allocator. These are all pretty trivial; mostly the '__' prefix is simply deleted since the functions are all static. The one exception is the list accessors were also renamed slightly to include a 'do' component to show more clearly that the other list accessors are convenience functions. JIRA NVGPU-1029 Change-Id: Ia39cdde9a81e740537fc9b4d70d87eadc12f8d4d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813601 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations (public allocator APIs)Alex Waterman2018-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. This fixes places in the public allocator APIs. This consists of the various init routines which are used to create an allocator and the debug macro used within the allocator code. The buddy allocator was handled by collapsing the internal '__' prepended version with the non-prefixed version. The only required change was in the page_allocator code which now had to pass in a NULL vm pointer (since the VM is not needed for managing VIDMEM). JIRA NVGPU-1029 Change-Id: I484a144e61789bf594c525c1ca307b96d120830f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813578 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 15.6 violationssmadhavan2018-09-12
| | | | | | | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces by introducing the braces. JIRA NVGPU-671 Change-Id: I8046a09fa7ffc74c3d737ba57132a0a9ae2ff195 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797699 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move programming of debug page to FBTerje Bergstrom2018-09-10
| | | | | | | | | | | | | | | Debug page was allocated and programmed to HUB MMU in GR code. This introduces a dependency from GR to FB and is anyway the wrong place. Move the code to allocate memory to generic MM code, and the code to program the addresses to FB. Change-Id: Ib6d3c96efde6794cf5e8cd4c908525c85b57c233 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801423 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move FB size query to FBTerje Bergstrom2018-09-10
| | | | | | | | | | | | | Vidmem size query was in mm_xxx.c. It involves reading a register from FB, so move the query to FB HAL. JIRA NVGPU-1063 Change-Id: I30dfd2c4fdcdd6c841f85aaab7431d52473759bd Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801425 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add Top as a unitTejal Kudav2018-09-10
| | | | | | | | | | | | | | | | | | | | | NVHSCLK registers used by NVLINK IP are part of dev_top hardware headers. This patch adds "Top" as a separate unit and exposes HALs to access dev_top registers. The top unit contains top-level configuration information and any extra registers or features that do not fit into another block's feature set. JIRA NVGPU-1053 JIRA NVGPU-966 Change-Id: Id9a43d4a1c5397959897a242ea97a39a1b95f916 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803632 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 22:58:22 -0400