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path: root/drivers/gpu/nvgpu/common
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* gpu: nvgpu: Add Ctrl API to read SM error stateVinod G2018-06-14
| | | | | | | | | | | | | | Expose IOCTL to Ctrl node to read Single SM error under NVGPU_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE bug 200412642 JIRA NVGPU-700 Change-Id: I3cbcf4d7f23a53dbd2350b38a5e259559d5fd3af Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1728931 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gpu railgate handling with runtime pmseshendra Gadagottu2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Earlier implementation of railgate disable config is disabling runtime pm during pm_init. This is causing multiple issues: 1. gpu rail will be on as soon as nvgpu driver probe is called. Actual gpu hw init may happen at much later point of time. 2. This is breaking railgate_enable sysfs node functionality. railgate_enable is not working if runtime pm is disabled. To avoid all these issues for railgate disable, enable runtime pm during pm_init and set auto-suspend delay to negative (-1), which will disable runtime pm suspend calls. Also fixed following issues along with this: 1. Updated railgate_enable debugfs implementation to use auto-suspend delay. To disable railgating: Set auto-suspend delay with negative value(-1) which will disable runtime pm suspend. To enable railgating: Set auto-suspend delay with railgate_delay value. Also removed redundant user_railgate_disabled gk20a device data and replaced with can_railgate, where ever it is applicable. 2. Initialized default railgate_delay to 500msec to avoid railgate on/off transitions with railigate enable from disabled state. 3. Created railgate_residency debug fs node irrespective of can_railgate initial state. This is helping with the case, where initial state of railgate state off and then railgate enable is done through sysfs node. Bug 2073029 Change-Id: I531da6d93ba8907e806f65a1de2a447c1ec2665c Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694944 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set gv10x boot clockVaikundanathan S2018-06-14
| | | | | | | | | | | | | | | - Set gv10x boot gpcclk to 952 MHz - Created ops to set gv10x boot gpcclk instead of using clk arbiter to set clocks Bug 200399373 Change-Id: Ice5956f79d4a52abf455506a798cf7b914f3d3ed Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700788 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu : nvgpu: gv100 pmu f/w version updateVaikundanathan S2018-06-14
| | | | | | | | | | | | | | -gv100 f/w version update for ucode https://git-master.nvidia.com/r/#/c/1708170/ Change-Id: I91b900dc3c2e702ec1341ac882b4abc7df875c4c Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1726913 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Update vfe_load for GV100Vaikundanathan S2018-06-14
| | | | | | | | | | | | Add gops to choose vfe_load between GP and GV. Bug 200399373 Change-Id: I73e0fbd2f1956e81c241f09639c69f33082e617b Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702143 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Set DMA mask on a per-platform basisAlex Waterman2018-06-14
| | | | | | | | | | | | | | | | | | | | Each GPU platform has different DMA limitations. For older chips the maximum size of a DMA buffer was more limited than newer SoCs (read: Xavier) and discrete GPUs. This patch adds support to set the DMA mask for a GPU on a per platform basis by adding a platform field that is populated with the maximum allowed DMA mask. That mask is programmed by the driver common code. If no mask is specified then the default mask size is 16GB (34 bits). Bug 2043276 Change-Id: I9c3c76c86bac6c485eb1197326e662516fbcaa41 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700980 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add g->fifo_eng_timeout_usThomas Fleury2018-06-14
| | | | | | | | | | | | | | Add g->fifo_eng_timeout_us to define engine timeout in microseconds. It is initialized with GRFIFO_TIMEOUT_CHECK_PERIOD_US. In RM server case, it can be overriden with value defined in device tree. Jira EVLR-2674 Change-Id: I69ac2ce779fe575566c8ba48e8cd2d0e6b2d93cf Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1728391 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: posix: undef min, max macros is definedAlex Waterman2018-05-30
| | | | | | | | | | | | | | | | | | | These macros are sometimes defined by the std library headers. So when they are defined #undef them and use our own version. Also explicitly include types.h from gmmu.c since it uses the min and max macros. JIRA NVGPU-525 Change-Id: I905ff23ef7a4a96467be59c4a124cb09b63f1f96 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1721015 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: posix: add impl for nvgpu_is_soc_t194_a01()Alex Waterman2018-05-29
| | | | | | | | | | | | | | | | | This function was added for Linux but not for posix. Thankfully the implementation for posix is trivial: just return false. JIRA NVGPU-525 Change-Id: Ib5af66dedeabb754ce36cbf6f0351e4af3926c52 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730742 Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: abstract submit profilingKonsta Holtta2018-05-25
| | | | | | | | | | | | | | | | Add gk20a_fifo_profile_snapshot() to store the submit time in a profiling entry that was acquired from gk20a_fifo_profile_acquire(). Also get rid of ifdef CONFIG_DEBUG_FS by stubbing the acquire and free functions when debugfs is not enabled. This reduces some cyclomatic complexity in the submit path. Jira NVGPU-708 Change-Id: I39829a6475cfe3aa582620219e420bde62228e52 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729545 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove empty gk20a_mm_debugfs_initKonsta Holtta2018-05-25
| | | | | | | | | | | | gk20a_mm_debugfs_init() used to initialize one mm-specific debugfs knob, but now that there aren't any, delete the function and the related files. Change-Id: Ic3177945bbab501c506b5199b44c87450df75452 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729530 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: posix: Use GCC builtins for ffs(), fls()Alex Waterman2018-05-25
| | | | | | | | | | | | | | | | These intrinsics will be fast for the given platform that the compiler is targeting. This also reduces complexity in the code. Change-Id: I6cfb761d6f881056446fa9a5de53dca50ed93c34 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1727383 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move bus HAL to commonTerje Bergstrom2018-05-25
| | | | | | | | | | | Move implementation of bus HAL to common/bus. Change-Id: Ia89350f9d94f3ccfd5500a340e6a677cd7d4cfaa Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1726337 GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add types.h to clock gating headersAlex Waterman2018-05-24
| | | | | | | | | | | | | | The headers use u32 and bool but do not include <nvgpu/types.h>. Moving around header includes exposed this issue in the cascade builds. This patch fixes the problem in all clock gating headers to avoid this being a concern in the future. Change-Id: Id56074df393d95bf65baf4062ac811d80d87e96b Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729748 Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: fix oob access in submit profiling dumpKonsta Holtta2018-05-24
| | | | | | | | | | | | | | | | The number of samples has to be at least the number of percentile ranges (here 20) for the reporting to work as expected and also to not cause negative indices in reading the sorted profile data. If there are not enough samples, just report all zeroes. Change-Id: Ie893859d95074f5ceabf6abe873941873668861d Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1721892 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Code updates for MISRA violationsVinod G2018-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Regenerated the gating_reglist.c files for various chips after fixing the script for MISRA C-2012 violations Rule 15.5: Multiple points of exit detected Rule 15.6: "if" body without compound statement Rule 10.3: Implicit conversions of 64bit to 32bit int Rule 7.2: Const must be declared with "U" Rule 5.7: Tags with name xxx already declared Add preprocessor conditional gaurds in gating_reglist header files JIRA NVGPU-671 JIRA NVGPU-656 JIRA NVGPU-688 JIRA NVGPU-686 JIRA NVGPU-644 Change-Id: Ie5a688cb8c39f072d2a15d86fb0ee0f2039a2cf1 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1724444 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove broken force_pramin featureKonsta Holtta2018-05-24
| | | | | | | | | | | | | | The forced PRAMIN reads and writes for sysmem buffers haven't worked in a while since the PRAMIN access code was refactored to work with vidmem-only sgt allocs. This feature was only ever meant for testing and debugging PRAMIN access and early dGPU support, but that is stable enough now so just delete the broken feature instead of fixing it. Change-Id: Ib31dae4550f3b6fea3c426a2e4ad126864bf85d2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1723725 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu_current_time_ns in submit profilingKonsta Holtta2018-05-24
| | | | | | | | | | | | | Replace Linux-specific and dubious sched_clock() with common nvgpu_current_time_ns(). sched_clock() used also nanoseconds. Jira NVGPU-708 Change-Id: I70f992fe42cc9c3ffed374fdebd582867475e84f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1723202 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add nvgpu_current_time_ns()Konsta Holtta2018-05-24
| | | | | | | | | | | | | | | | | | | | Add an abstraction over a monotonic system clock in nanosecond units. Use ktime_get() for the Linux implementation, similarly to nvgpu_current_time_ms(). Jira NVGPU-708 Change-Id: I3165c20abf2652f1a1fa04e66c04cd34a8fe6dcc Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1723201 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: chip revision check for invalidatesseshendra Gadagottu2018-05-24
| | | | | | | | | | | | | | | Only for T194 A01 version following invalidates are disabled: -CBM alpha and beta invalidations for L2 -SCC pagepool invalidates -SWDX spill buffer invalidates Bug 2053668 Change-Id: I7122b223946a1bfa4b11ed8ee782572215313dc1 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1680500 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu types.h in clock gating sourceSourab Gupta2018-05-22
| | | | | | | | | | | | | | | | Use the nvgpu/types.h instead of linux/types.h in the clock gating sources Jira VQRM-3700 Change-Id: Ib399cc4367c77f0d08454aa7639bb619367f673b Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1726782 Reviewed-by: Shashank Singh <shashsingh@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add GPU Fmax@Vmin access through BPMPAlex Frid2018-05-22
| | | | | | | | | | | | | | On Tegra platforms that have clock management under BPMP, and do not support Tegra DVFS, GPU driver cannot access Fmax@Vmin (get interface always returns "0"). Added such access through BPMP DVFS shim driver. Bug 2045903 Change-Id: I0222f2e2917cda15d18ea3296dd1fe53b2ea6b45 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1722431 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Code updates for MISRA violationsVinod G2018-05-21
| | | | | | | | | | | | | | | | As part of the MISRA fixes, moving all the gating_reglist files to common/clock_gating dir, the new directory structure suggested to follow. Removed unused gating_reglist files for gk20a JIRA NVGPU-646 Change-Id: I388855befcf991ee68eeffed10fe9ac456210649 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1722330 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: call nvgpu_init_ltc_supportRichard Zhao2018-05-20
| | | | | | | | | | | | | | | vgpu needs to call nvgpu_init_ltc_support to floor sweep and set ltc_count. And set gops.ltc.set_enabled to null as guest is not allowed to change ltc settings. Jira VQRM-2345 Change-Id: I83517d631aa947db4a0a4c312f0cecda9ba03973 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1703626 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add timeouts_disabled_refcount for enabling timeoutSeema Khowala2018-05-18
| | | | | | | | | | | | | | | | -timeouts will be enabled only when timeouts_disabled_refcount will reach 0 -timeouts_enabled debugfs will change from u32 type to file type to avoid race enabling/disabling timeout from debugfs and ioctl -unify setting timeouts_enabled from debugfs and ioctl Bug 1982434 Change-Id: I54bab778f1ae533872146dfb8d80deafd2a685c7 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588690 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: drop force_need_sync_fence in submit pathKonsta Holtta2018-05-18
| | | | | | | | | | | | | | | | For CDE work a sync fence is always requested, but kernel does not need it and submit flags from userspace will be passed to the submit function in cde path so a sync fence will get created if necessary. To reduce some complexity, remove the explicit boolean in favor of just NVGPU_SUBMIT_FLAGS_SYNC_FENCE. Jira NVGPU-705 Change-Id: I8aac85288513ed7cc640acd021d892cee86f41d8 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1721785 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle clk arb event posting in OS specific codeSourab Gupta2018-05-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mechanism of posting events to userspace is OS specific. In linux this works through poll fd, wherein we can make use of nvgpu_cond variables to poll and trigger the corresponding wait_queue. The post event functionality on QNX doesn't work on poll though. It uses iofunc_notify_trigger to post the events to the calling process. As such QNX can't work with nvgpu_cond's. To overcome this issue, it is proposed to create OS specific interface function for posting clk arb events. Linux can call nvgpu_cond based implementation, which makes sense since these are already initialized and poll'ed in Linux specific code only. QNX can implement this interface to call iofunc_notify_* functions, as per its need. Jira VQRM-3741 Change-Id: I7d9f71dae2ae7f6a09cd56662003fd1b7e50324c Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709656 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add conversion function for clk domainSourab Gupta2018-05-18
| | | | | | | | | | | | | | | Add a conversion function for NVGPU_GPU_CLK_DOMAIN_* defines present in uapi header. This enables movement of related code to the OS agnostic clk_arb.c Jira VQRM-3741 Change-Id: I922d1cfb91d6a5dda644cf418f2f3815d975fcfd Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709653 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add macro for clk arb debug logsSourab Gupta2018-05-18
| | | | | | | | | | | | | | | Introduce a macro for clk arbiter debug logs. Jira VQRM-3741 Change-Id: I9f4ebf5f979e84b6383dc8755eb34c0ffa3d0f43 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709652 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move clk_arb.c to common codeSourab Gupta2018-05-18
| | | | | | | | | | | | | | | | Now that clk_arb.c is free of Linux'isms, move it to the clk/ directory. Jira VQRM-741 Change-Id: I53298c76f834322aa586781cdfd2e6031f4826a1 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709651 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLISTDavid Li2018-05-18
| | | | | | | | | | | | | | | | | | | | | | | Add NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST ioctl to reschedule runlist, and optionally check host and FECS status to preempt pending load of context not belonging to the calling channel on GR engine during context switch. This should be called immediately after a submit to decrease worst case submit to start latency for high interleave channel. There is less than 0.002% chance that the ioctl blocks up to couple miliseconds due to race condition of FECS status changing while being read. For GV11B it will always preempt pending load of unwanted context since there is no chance that ioctl blocks due to race condition. Also fix bug with host reschedule for multiple runlists which needs to write both runlist registers. Bug 1987640 Bug 1924808 Change-Id: I0b7e2f91bd18b0b20928e5a3311b9426b1bf1848 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1549050 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Translate as_alloc flagsAlex Waterman2018-05-17
| | | | | | | | | | | | | | | | | | | Translate the as_alloc flags so that the common/as.c code no longer needs to include <uapi/linux/nvgpu.h>. This was an oversight from prior MM unification efforts which was caught by the userspace POSIX build on QNX. JIRA NVGPU-525 Change-Id: I6af6cb9904c2ae9edeb8dbb970846c31b56822bf Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1720918 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update PMU firmware versionDeepak Goyal2018-05-17
| | | | | | | | | | | | | | | | | Removed PMU breakpoints if there is failure during GR save/restore during ELPG entry/exit. Bug 2108544 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Change-Id: I08c342f5f79b7484d31e2437ede1881c4dceb6d0 Reviewed-on: https://git-master.nvidia.com/r/1719659 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to insert semaphore commandsDeepak Nibade2018-05-16
| | | | | | | | | | | | | | | | | | | | | Add below new HALs gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer Separate out new API gk20a_fifo_add_sema_cmd() to implement semaphore acquire/ release sequence and set it to gops.fifo.add_sema_cmd() Add gk20a_fifo_get_sema_wait_cmd_size() and gk20a_fifo_get_sema_incr_cmd_size() to return respective command buffer sizes Jira NVGPUT-16 Change-Id: Ia81a50921a6a56ebc237f2f90b137268aaa2d749 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704490 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp106 pmu f/w version updateMahantesh Kumbar2018-05-14
| | | | | | | | | | | | | | | | | | | - gp106 f/w version update for ucode https://git-master.nvidia.com/r/#/c/1708195/ - APP_VERSION_GP10X 24008084 to 24069912 - nvgpu driver cl's for current changes https://git-master.nvidia.com/r/#/c/1694546/ https://git-master.nvidia.com/r/#/c/1700746/ p4 CL# 24076634 Change-Id: If15663983a8753a256e47451938be1cf0102fadb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1708199 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vf inject changesVaikundanathan S2018-05-14
| | | | | | | | | | | | | | | | | | | | - Added vf change inject support for gv10x - Updated clk_pmu_vf_inject() to fill required data for pascal or volta vf change inject support - Added new ctrl clk interface for gv10x clk domain list - Added pmu interface for gv10x clk domain list & vf change inject request - Modified clk cmd, msg & RPC id's to match with chips_a_23609936 branch Bug 200399373 Change-Id: Ib9dc10073386f63bdfd92110c7ec3e09b1c484ce Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700746 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move sync_gk20a under common/linux directoryDebarshi Dutta2018-05-14
| | | | | | | | | | | | | | | | sync_gk20a.* files are no longer used by core code and only invoked from linux specific implementations of the OS_FENCE framework which are under the common/linux directory. Hence, sync_gk20a.* files are also moved under common/linux. JIRA NVGPU-66 Change-Id: If623524611373d2da39b63cfb3c1e40089bf8d22 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1712900 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix Gpu sysfs access to Fmax@VminAlex Frid2018-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | Currently gpu sysfs retrieves Fmax@Vmin by direct call into Tegra DVFS driver that introduces compile time dependencies on CONFIG_TEGRA_DVFS. In addition incorrect clock is used for DVFS information access. Re-factored sysfs node to use generic GPU clock operation for Fmax@Vmin read. This would fix a bug in target clock selection, and allows to remove dependency of sysfs on CONFIG_TEGRA_DVFS. Updated nvgpu_linux_get_fmax_at_vmin_safe operation itself so it can be called on platforms that does not support Tegra DVFS, although 0 will still be returned as Fmax@Vmin on such platforms. Bug 2045903 Change-Id: I32cce25320df026288c82458c913b0cde9ad4f72 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1710924 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pmc access through pmc driverkalyani chidambaram2018-05-11
| | | | | | | | | | | | | The pmc access has to be through pmc driver. This prevents the direct access to pmc registers and supports onlt tz access to it in t210 platforms. Bug 1811649 Change-Id: I235768a07fa93ce4cced656aade160bbd853be62 Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704315 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove sync_fence dependencies from fence_gk20aDebarshi Dutta2018-05-10
| | | | | | | | | | | | | | | | | Replaced all instances of sync_fence in gk20a_fence* code with nvgpu_os_fence. Added the API install_fence for the nvgpu_os_fence abstraction. sync_fence mechanism and its dependencies are completely removed from the fence_gk20a methods. Due to the recent os_fence changes and the changes to fence_gk20a, we can finally get rid of all the CONFIG_SYNCS present in the submit path. JIRA NVGPU-66 Change-Id: I3551dab04b93b1e94db83fc102a41872be89e9ed Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1701245 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: adapt gk20a_channel_syncpt to use os_fenceDebarshi Dutta2018-05-10
| | | | | | | | | | | | | This patch adapts gk20a_channel_syncpt to use os_fence for post fence as well as pre-fence(wait) use cases. Jira NVGPU-66 Change-Id: I49627d1f88d52a53511a02f5de60fed6df8350de Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1676631 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: create a wrapper over sync_fencesDebarshi Dutta2018-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch constructs an abstraction to hide the sync_fence functionality from the common code. struct nvgpu_os_fence acts as an abstraction for struct sync_fence. struct nvgpu_os_fence consists of an ops structure named nvgpu_os_fence_ops which contains an API to do pushbuffer programming to generate wait commands for the fence. The current implementation of nvgpu only allows for wait method on a sync_fence which was generated using a similar backend(i.e. either Nvhost Syncpoints or Semaphores). In this patch, a generic API is introduced which will decide the type of the underlying implementation of the struct nvgpu_os_fence at runtime and run the corresponding wait implementation on it. This patch changes the channel_sync_gk20a's semaphore specific implementation to use the abstract API. A subsequent patch will make the changes for the nvhost_syncpoint based implementations as well. JIRA NVGPU-66 Change-Id: If6675bfde5885c3d15d2ca380bb6c7c0e240e734 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1667218 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support TSG IOCTL to unbind channelDeepak Nibade2018-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We so far do not support unbinding a channel from TSG explicitly through IOCTL Channel is unbound from TSG when channel fd is closed But this could create issue in case process is forked and fd is duplicated In worst case it is possible that duplicate fd is closed sometime later when TSG is active and that could lead to corruption of TSG state Fix this by implementing NVGPU_TSG_IOCTL_UNBIND_CHANNEL API This API will simply call gk20a_tsg_unbind_channel() API to unbind the channel Note that we also mark the channel has_timedout since unbound channel does not have any context of its own and it cannot serve any job Remove call to gk20a_disable_channel() while closing the channel. We do not support bare channels without TSG, and if channel is not part of TSG then it means channel is already unbound from TSG with call to NVGPU_TSG_IOCTL_UNBIND_CHANNEL, and there is nothing to do while closing the channel Bug 200327095 Jira NVGPU-229 Change-Id: Ib7f6710f0dc8125caafabe7bee737622c3dd9fa3 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1708902 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: added nvgpu_sim_init_lateAntony Clince Alex2018-05-09
| | | | | | | | | | | | | | | | | | | | Split sim initialization to two parts, first part gets invoked as part of probe and second part gets invoked in the finalize_poweron after the hal has been initialized. This is done because some of the sim init code uses mm api's which are assigned as part of hal init. replaced sim buffer allocation api's with nvgpu_dma_sys_alloc. Change-Id: Ib019fbb747bdf6dcc74e7deba732ab41f0869e96 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1705424 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove gk20a_dbg* functionsTerje Bergstrom2018-05-09
| | | | | | | | | | | | | | | Switch all logging to nvgpu_log*(). gk20a_dbg* macros are intentionally left there because of use from other repositories. Because the new functions do not work without a pointer to struct gk20a, and piping it just for logging is excessive, some log messages are deleted. Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704148 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: created os-agnostic sim header.Antony Clince Alex2018-05-09
| | | | | | | | | | | | | | added a os-agnostic sim.h header which could be included in by any platform, moved out os specific headers to nvgpu/linux. JIRA VQRM-2368 Change-Id: I3861bfa75a6b8d2d909bc7223467fd68c208275b Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702816 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: os-agnostic segregation of sim/sim_pciAntony Clince Alex2018-05-09
| | | | | | | | | | | | | | | | | | segregated os-agnostic function from linux/sim.c and linux/sim_pci.c to sim.c and sim_pci.c, while retaining os-specific functions. renamed all gk20a_* api's to nvgpu_*. renamed hw_sim_gk20a.h to nvgpu/hw_sim.h moved hw_sim_pci.h to nvgpu/hw_sim_pci.h JIRA VQRM-2368 Change-Id: I040a6b12b19111a0b99280245808ea2b0f344cdd Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702425 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: refactored struct sim_gk20aAntony Clince Alex2018-05-09
| | | | | | | | | | | | | | | | | | moved sim buffer(send, recv and msg) from os-specific structure to OS agnostic structure. JIRA VQRM-2368 Change-Id: I10ff23fe24d86f2bd372f1bae0369cc45aadfb80 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702178 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: refectored sim_readl/sim_writelAntony Clince Alex2018-05-09
| | | | | | | | | | | | | | | | | | | | | refactored sim_readl and sim_writel to use os-agnostic structures. converted all sim buffers to the type nvgpu_mem and replaced all alloc_page and free_page calls with corresponding nvgpu_dma_alloc/nvgpu_dma_free calls. JIRA VQRM-2368 Change-Id: Ia9d29119d31f239ed16be932cfd16c334002c727 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702050 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink endpoint ops to common codeThomas Fleury2018-05-09
| | | | | | | | | | | | | Move nvlink endpoint operations to common code. These operations are invoked when handling nvlink core driver requests. Jira VQRM-3523 Change-Id: I93024bf88a8caa3765b33c1264dde452c1a85ee3 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1698686 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 23:34:28 -0400