| Commit message (Collapse) | Author | Age |
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Implement BAR2 bind as a bus HAL and remove the corresponding MM HAL.
BAR2 bind HW API is in bus.
JIRA NVGPU-588
Change-Id: I3a8391b00f1ba65f9ed28b633f1d52bf7c984230
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730896
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All chips should use the waiting version of BAR1 bind since gm20b.
Change gp10b and gp106 to do that. BAR1 is not used in Volta.
JIRa NVGPU-588
Change-Id: Ib6957ebea4effa7c64f4d71522447fa6245728ed
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730895
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Code touching timer registers was combined with bus code. They're two
logically separate register spaces, so separate the code accordingly.
JIRA NVGPU-588
Change-Id: I40e2925ff156669f41ddc1f2e7714f92a2da367b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730893
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PRI timeout should always use the HW initialization value. Do not set it
explicitly.
JIRA NVGPU-588
Change-Id: Idb63caba07c5fa7e0439e572861443f2783d0adc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730892
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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bus_gk20a.c had some debug dump references to MC and GR registers.
The dumps have not been very useful, so instead of refactoring the
code just remove the dumps.
JIRA NVGPU-588
Change-Id: Id974731716d058ef4a3fe77240c11b1c53db169c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730891
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Move setting of BAR0_WINDOW to bus HAL. Also moves the usage of spinlock to
common code so that pramin_gk20a.[ch] can be deleted.
JIRA NVGPU-588
Change-Id: I3ceabc56016711b2c93f31fedf07daa778a4873a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730890
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Registers to set priv interrupts are in priv_ring, but the code was
in bus HAL. Move the code and related HALs to priv_ring instead.
JIRA NVGPU-588
Change-Id: I708d11f77405dbba86586a0d1da42f65bcc1de9d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730889
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bus_gk20a.c had a few unnecessary includes. Remove them to speed up
compilation.
JIRA NVGPU-588
Change-Id: I0e94e788104ba6acb259c315734e6b42f69a8074
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730888
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Sysfs nodes for GR stats are created on GR init. If nvgpu
module is removed without any ops, then it tries to remove
sysfs nodes which do not exist resulting in kernel panic.
Fix this issue by removing sysfs nodes only if ecc counters
are initialized.
Bug 1987855
Change-Id: I3f967ee92ec02ad19ffbd9bfa8bace5bfd229dd2
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730536
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The vidmem shall be destroyed only if it has been
initialized. If not skipped, it accesses mutexes
which are in invalid state. This results in BUG like:
BUG: spinlock bad magic on CPU#0, rmmod/1560
Also, destroy vidmem bootstrap allocator which is
set up in nvgpu_vidmem_init().
Bug 1987855
Change-Id: I68e91422a54b40feeb9071158b797828e2391303
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730535
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Expose IOCTL to Ctrl node to read Single SM error
under NVGPU_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE
bug 200412642
JIRA NVGPU-700
Change-Id: I3cbcf4d7f23a53dbd2350b38a5e259559d5fd3af
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1728931
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Earlier implementation of railgate disable config is disabling
runtime pm during pm_init. This is causing multiple issues:
1. gpu rail will be on as soon as nvgpu driver probe is called.
Actual gpu hw init may happen at much later point of time.
2. This is breaking railgate_enable sysfs node functionality.
railgate_enable is not working if runtime pm is disabled.
To avoid all these issues for railgate disable, enable runtime pm
during pm_init and set auto-suspend delay to negative (-1), which
will disable runtime pm suspend calls.
Also fixed following issues along with this:
1. Updated railgate_enable debugfs implementation to use auto-suspend delay.
To disable railgating:
Set auto-suspend delay with negative value(-1) which will disable runtime
pm suspend.
To enable railgating:
Set auto-suspend delay with railgate_delay value.
Also removed redundant user_railgate_disabled gk20a device data and
replaced with can_railgate, where ever it is applicable.
2. Initialized default railgate_delay to 500msec to avoid railgate
on/off transitions with railigate enable from disabled state.
3. Created railgate_residency debug fs node irrespective of can_railgate
initial state. This is helping with the case, where initial state of
railgate state off and then railgate enable is done through sysfs node.
Bug 2073029
Change-Id: I531da6d93ba8907e806f65a1de2a447c1ec2665c
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1694944
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- Set gv10x boot gpcclk to 952 MHz
- Created ops to set gv10x boot gpcclk instead
of using clk arbiter to set clocks
Bug 200399373
Change-Id: Ice5956f79d4a52abf455506a798cf7b914f3d3ed
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700788
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-gv100 f/w version update for ucode
https://git-master.nvidia.com/r/#/c/1708170/
Change-Id: I91b900dc3c2e702ec1341ac882b4abc7df875c4c
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1726913
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GVS: Gerrit_Virtual_Submit
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Add gops to choose vfe_load between GP and GV.
Bug 200399373
Change-Id: I73e0fbd2f1956e81c241f09639c69f33082e617b
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702143
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Each GPU platform has different DMA limitations. For older
chips the maximum size of a DMA buffer was more limited than
newer SoCs (read: Xavier) and discrete GPUs.
This patch adds support to set the DMA mask for a GPU on a
per platform basis by adding a platform field that is populated
with the maximum allowed DMA mask. That mask is programmed by
the driver common code. If no mask is specified then the
default mask size is 16GB (34 bits).
Bug 2043276
Change-Id: I9c3c76c86bac6c485eb1197326e662516fbcaa41
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700980
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Add g->fifo_eng_timeout_us to define engine timeout in microseconds.
It is initialized with GRFIFO_TIMEOUT_CHECK_PERIOD_US. In RM server
case, it can be overriden with value defined in device tree.
Jira EVLR-2674
Change-Id: I69ac2ce779fe575566c8ba48e8cd2d0e6b2d93cf
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1728391
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These macros are sometimes defined by the std library headers.
So when they are defined #undef them and use our own version.
Also explicitly include types.h from gmmu.c since it uses the min
and max macros.
JIRA NVGPU-525
Change-Id: I905ff23ef7a4a96467be59c4a124cb09b63f1f96
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1721015
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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This function was added for Linux but not for posix. Thankfully the
implementation for posix is trivial: just return false.
JIRA NVGPU-525
Change-Id: Ib5af66dedeabb754ce36cbf6f0351e4af3926c52
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730742
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add gk20a_fifo_profile_snapshot() to store the submit time in a
profiling entry that was acquired from gk20a_fifo_profile_acquire().
Also get rid of ifdef CONFIG_DEBUG_FS by stubbing the acquire and free
functions when debugfs is not enabled. This reduces some cyclomatic
complexity in the submit path.
Jira NVGPU-708
Change-Id: I39829a6475cfe3aa582620219e420bde62228e52
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729545
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gk20a_mm_debugfs_init() used to initialize one mm-specific debugfs knob,
but now that there aren't any, delete the function and the related
files.
Change-Id: Ic3177945bbab501c506b5199b44c87450df75452
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729530
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These intrinsics will be fast for the given platform that the
compiler is targeting. This also reduces complexity in the
code.
Change-Id: I6cfb761d6f881056446fa9a5de53dca50ed93c34
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1727383
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move implementation of bus HAL to common/bus.
Change-Id: Ia89350f9d94f3ccfd5500a340e6a677cd7d4cfaa
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1726337
GVS: Gerrit_Virtual_Submit
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The headers use u32 and bool but do not include <nvgpu/types.h>.
Moving around header includes exposed this issue in the cascade
builds.
This patch fixes the problem in all clock gating headers to
avoid this being a concern in the future.
Change-Id: Id56074df393d95bf65baf4062ac811d80d87e96b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729748
Reviewed-by: Bo Yan <byan@nvidia.com>
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The number of samples has to be at least the number of percentile ranges
(here 20) for the reporting to work as expected and also to not cause
negative indices in reading the sorted profile data. If there are not
enough samples, just report all zeroes.
Change-Id: Ie893859d95074f5ceabf6abe873941873668861d
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1721892
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Regenerated the gating_reglist.c files for various
chips after fixing the script for MISRA C-2012
violations
Rule 15.5: Multiple points of exit detected
Rule 15.6: "if" body without compound statement
Rule 10.3: Implicit conversions of 64bit to 32bit int
Rule 7.2: Const must be declared with "U"
Rule 5.7: Tags with name xxx already declared
Add preprocessor conditional gaurds in
gating_reglist header files
JIRA NVGPU-671
JIRA NVGPU-656
JIRA NVGPU-688
JIRA NVGPU-686
JIRA NVGPU-644
Change-Id: Ie5a688cb8c39f072d2a15d86fb0ee0f2039a2cf1
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1724444
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The forced PRAMIN reads and writes for sysmem buffers haven't worked in
a while since the PRAMIN access code was refactored to work with
vidmem-only sgt allocs. This feature was only ever meant for testing and
debugging PRAMIN access and early dGPU support, but that is stable
enough now so just delete the broken feature instead of fixing it.
Change-Id: Ib31dae4550f3b6fea3c426a2e4ad126864bf85d2
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1723725
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Replace Linux-specific and dubious sched_clock() with common
nvgpu_current_time_ns(). sched_clock() used also nanoseconds.
Jira NVGPU-708
Change-Id: I70f992fe42cc9c3ffed374fdebd582867475e84f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1723202
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Add an abstraction over a monotonic system clock in nanosecond units.
Use ktime_get() for the Linux implementation, similarly to
nvgpu_current_time_ms().
Jira NVGPU-708
Change-Id: I3165c20abf2652f1a1fa04e66c04cd34a8fe6dcc
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1723201
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Only for T194 A01 version following invalidates are disabled:
-CBM alpha and beta invalidations for L2
-SCC pagepool invalidates
-SWDX spill buffer invalidates
Bug 2053668
Change-Id: I7122b223946a1bfa4b11ed8ee782572215313dc1
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1680500
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Use the nvgpu/types.h instead of linux/types.h in the clock
gating sources
Jira VQRM-3700
Change-Id: Ib399cc4367c77f0d08454aa7639bb619367f673b
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1726782
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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On Tegra platforms that have clock management under BPMP, and do not
support Tegra DVFS, GPU driver cannot access Fmax@Vmin (get interface
always returns "0"). Added such access through BPMP DVFS shim driver.
Bug 2045903
Change-Id: I0222f2e2917cda15d18ea3296dd1fe53b2ea6b45
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1722431
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As part of the MISRA fixes, moving all the
gating_reglist files to common/clock_gating dir,
the new directory structure suggested to follow.
Removed unused gating_reglist files for gk20a
JIRA NVGPU-646
Change-Id: I388855befcf991ee68eeffed10fe9ac456210649
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1722330
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vgpu needs to call nvgpu_init_ltc_support to floor sweep and
set ltc_count.
And set gops.ltc.set_enabled to null as guest is not allowed to change
ltc settings.
Jira VQRM-2345
Change-Id: I83517d631aa947db4a0a4c312f0cecda9ba03973
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1703626
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-timeouts will be enabled only when timeouts_disabled_refcount
will reach 0
-timeouts_enabled debugfs will change from u32 type to file type
to avoid race enabling/disabling timeout from debugfs and ioctl
-unify setting timeouts_enabled from debugfs and ioctl
Bug 1982434
Change-Id: I54bab778f1ae533872146dfb8d80deafd2a685c7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588690
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For CDE work a sync fence is always requested, but kernel does not need
it and submit flags from userspace will be passed to the submit function
in cde path so a sync fence will get created if necessary. To reduce
some complexity, remove the explicit boolean in favor of just
NVGPU_SUBMIT_FLAGS_SYNC_FENCE.
Jira NVGPU-705
Change-Id: I8aac85288513ed7cc640acd021d892cee86f41d8
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1721785
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The mechanism of posting events to userspace is OS specific.
In linux this works through poll fd, wherein we can make use
of nvgpu_cond variables to poll and trigger the corresponding
wait_queue.
The post event functionality on QNX doesn't work on poll though.
It uses iofunc_notify_trigger to post the events to the calling
process. As such QNX can't work with nvgpu_cond's.
To overcome this issue, it is proposed to create OS specific
interface function for posting clk arb events. Linux can call
nvgpu_cond based implementation, which makes sense since these
are already initialized and poll'ed in Linux specific code only.
QNX can implement this interface to call iofunc_notify_*
functions, as per its need.
Jira VQRM-3741
Change-Id: I7d9f71dae2ae7f6a09cd56662003fd1b7e50324c
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709656
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add a conversion function for NVGPU_GPU_CLK_DOMAIN_*
defines present in uapi header.
This enables movement of related code to the OS agnostic
clk_arb.c
Jira VQRM-3741
Change-Id: I922d1cfb91d6a5dda644cf418f2f3815d975fcfd
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709653
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Introduce a macro for clk arbiter debug logs.
Jira VQRM-3741
Change-Id: I9f4ebf5f979e84b6383dc8755eb34c0ffa3d0f43
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709652
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Now that clk_arb.c is free of Linux'isms, move
it to the clk/ directory.
Jira VQRM-741
Change-Id: I53298c76f834322aa586781cdfd2e6031f4826a1
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709651
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST ioctl to reschedule runlist,
and optionally check host and FECS status to preempt pending load of
context not belonging to the calling channel on GR engine during context
switch.
This should be called immediately after a submit to decrease worst case
submit to start latency for high interleave channel.
There is less than 0.002% chance that the ioctl blocks up to couple
miliseconds due to race condition of FECS status changing while being read.
For GV11B it will always preempt pending load of unwanted context since
there is no chance that ioctl blocks due to race condition.
Also fix bug with host reschedule for multiple runlists which needs to
write both runlist registers.
Bug 1987640
Bug 1924808
Change-Id: I0b7e2f91bd18b0b20928e5a3311b9426b1bf1848
Signed-off-by: David Li <davli@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1549050
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Translate the as_alloc flags so that the common/as.c code no longer
needs to include <uapi/linux/nvgpu.h>. This was an oversight from
prior MM unification efforts which was caught by the userspace
POSIX build on QNX.
JIRA NVGPU-525
Change-Id: I6af6cb9904c2ae9edeb8dbb970846c31b56822bf
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1720918
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Removed PMU breakpoints if there is failure during
GR save/restore during ELPG entry/exit.
Bug 2108544
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Change-Id: I08c342f5f79b7484d31e2437ede1881c4dceb6d0
Reviewed-on: https://git-master.nvidia.com/r/1719659
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Seema Khowala <seemaj@nvidia.com>
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Add below new HALs
gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods
gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer
gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer
Separate out new API gk20a_fifo_add_sema_cmd() to implement semaphore acquire/
release sequence and set it to gops.fifo.add_sema_cmd()
Add gk20a_fifo_get_sema_wait_cmd_size() and gk20a_fifo_get_sema_incr_cmd_size()
to return respective command buffer sizes
Jira NVGPUT-16
Change-Id: Ia81a50921a6a56ebc237f2f90b137268aaa2d749
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704490
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- gp106 f/w version update for ucode
https://git-master.nvidia.com/r/#/c/1708195/
- APP_VERSION_GP10X 24008084 to 24069912
- nvgpu driver cl's for current changes
https://git-master.nvidia.com/r/#/c/1694546/
https://git-master.nvidia.com/r/#/c/1700746/
p4 CL# 24076634
Change-Id: If15663983a8753a256e47451938be1cf0102fadb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1708199
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- Added vf change inject support for gv10x
- Updated clk_pmu_vf_inject() to fill required data
for pascal or volta vf change inject support
- Added new ctrl clk interface for gv10x clk domain list
- Added pmu interface for gv10x clk domain list &
vf change inject request
- Modified clk cmd, msg & RPC id's to match
with chips_a_23609936 branch
Bug 200399373
Change-Id: Ib9dc10073386f63bdfd92110c7ec3e09b1c484ce
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700746
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sync_gk20a.* files are no longer used by core code and only invoked
from linux specific implementations of the OS_FENCE framework which are
under the common/linux directory. Hence, sync_gk20a.* files are also
moved under common/linux.
JIRA NVGPU-66
Change-Id: If623524611373d2da39b63cfb3c1e40089bf8d22
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1712900
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Currently gpu sysfs retrieves Fmax@Vmin by direct call into Tegra DVFS
driver that introduces compile time dependencies on CONFIG_TEGRA_DVFS.
In addition incorrect clock is used for DVFS information access.
Re-factored sysfs node to use generic GPU clock operation for Fmax@Vmin
read. This would fix a bug in target clock selection, and allows to
remove dependency of sysfs on CONFIG_TEGRA_DVFS.
Updated nvgpu_linux_get_fmax_at_vmin_safe operation itself so it can be
called on platforms that does not support Tegra DVFS, although 0 will
still be returned as Fmax@Vmin on such platforms.
Bug 2045903
Change-Id: I32cce25320df026288c82458c913b0cde9ad4f72
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1710924
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The pmc access has to be through pmc driver. This prevents the direct access
to pmc registers and supports onlt tz access to it in t210 platforms.
Bug 1811649
Change-Id: I235768a07fa93ce4cced656aade160bbd853be62
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704315
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Replaced all instances of sync_fence in gk20a_fence* code with
nvgpu_os_fence. Added the API install_fence for the nvgpu_os_fence
abstraction. sync_fence mechanism and its dependencies are completely
removed from the fence_gk20a methods. Due to the recent os_fence changes
and the changes to fence_gk20a, we can finally get rid of all the CONFIG_SYNCS
present in the submit path.
JIRA NVGPU-66
Change-Id: I3551dab04b93b1e94db83fc102a41872be89e9ed
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1701245
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