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* gpu: nvgpu: pass pid/tid from os specific code to common codeRichard Zhao2018-04-16
| | | | | | | | | | | | | | | | | | linux driver runs in user's process but qnx driver has dedicate driver process, so they have different way to get user pid. nvgpu common code expect calls from os specific code pass pid/tid. ce/cde open channel for internal use, we use driver pid. Jira VQRM-3534 Change-Id: I892372ac5f1dc4d25f9928d16992bcc659d12a56 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694145 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: enable elcg, blcg, slcgSeema Khowala2018-04-12
| | | | | | | | | | | | | | Bug 200399393 Change-Id: I60b2704ba447e45c330f2dc133cb2fa17e107f1c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683105 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp106 f/w version updateMahantesh Kumbar2018-04-12
| | | | | | | | | | | | | - gp106 f/w version update for ucode https://git-master.nvidia.com/r/#/c/1684238/ - APP_VERSION_GP10X "23647537" updated to "23732390" Change-Id: Id534b041e4ae90e82b2a8259bb0372689500e871 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1684250 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update clk_fll interface as per chips_aTejal Kudav2018-04-12
| | | | | | | | | | | | | | | | | | | Two new members added to fll struct and code modified to support GV100 VBIOS NAFLL tables Add g->ops for getting vbios clk domains JIRA NVGPUGV100-39 Change-Id: Iaabea893d55d44a272e2bce2b1d525b122cd36f5 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594289 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove uapi include from ce2Sourab Gupta2018-04-11
| | | | | | | | | | | | | | | | | Remove the include of a uapi header from ce2.c since this file no longer makes use of any uapi definition. VQRM-3465 Change-Id: Ib9ba7090021f5fc21734adca80be8a0ea224bf90 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691980 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add conversion function for uapi submit gpfifo flagsSourab Gupta2018-04-11
| | | | | | | | | | | | | | | | | | The submit gpfifo flags are splattered everywhere inside the nvgpu code. Though the usage is inside nvgpu Linux code only, still it needs to be gotten rid of and replaced with the defines present in common code. VQRM-3465 Change-Id: I901b33565b01fa3e1f9ba6698a323c16547a8d3e Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691979 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove usage of nvgpu_gpfifoSourab Gupta2018-04-11
| | | | | | | | | | | | | | | | | | | Remove the usage of nvgpu_gpfifo splattered across nvgpu, and replace with a struct defined in common code. The usage is still inside Linux, but this helps the subsequent unification efforts, e.g. to unify the submit path. VQRM-3465 Change-Id: I9e5ac697a0c7f85239ddba319085c09481d20d6b Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691978 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove usage of nvgpu_fenceSourab Gupta2018-04-11
| | | | | | | | | | | | | | | | | | | Remove the usage of nvgpu_fence splattered across nvgpu, and replace with a struct defined in common code. The usage is still inside Linux, but this helps the subsequent unification efforts, e.g. to unify the submit path. VQRM-3465 Change-Id: Ic3737450123dfc5e1c40ca5b6b8d8f6b3070aa0d Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691977 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix misc issue for dgpu code on QNX buildShashank Singh2018-04-10
| | | | | | | | | | | | | | | | - QNX is pulling dgpu code from linux which has multiple build failure on QNX. Like QNX needs explicit declaration for all non-static functions. Some linux specific headers need to be put under __KERNEL__ flag. Change-Id: I15af1a1f6a069c82f9a81449f4f7c7d48612de42 Signed-off-by: Shashank Singh <shashsingh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1665752 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check null before accessing nvgpu_firmware.Debarshi Dutta2018-04-10
| | | | | | | | | | | | | | | | | | | check for null value of nvgpu_firmware before accessing them in nvgpu_firmware_release(). Coverity defect id: 2983427, 2983428 Bug 200291879 Change-Id: I946cb448351441ee820aa3e5d8db649943d20d16 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683505 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use tegra_alloc_fd() only on Tegra kernelTerje Bergstrom2018-04-06
| | | | | | | | | | | | | | | | tegra_alloc_fd() exists only in Tegra kernel. Use get_unused_fd_flags() in other platforms. JIRA NVGPU-4 Change-Id: I12b16957263f6cea771314a9da229384c865e65f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1689538 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100 temperature read supportMahantesh Kumbar2018-04-06
| | | | | | | | | | | | | | | | | | | | | | - Enabled internal temperature sensor read for gv100 dgpu. - Added check to temperature read support before proceeding to read temperature from H/W - Assigned GP106 temperature HAL's for GV100 as no changes between GP106 & GV100 H/W registers. Bug 200352328 Change-Id: I86b5a1859b87ace49a07d0ff3749bb5b085bba91 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673347 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: De-linuxify pmgr codeAlex Waterman2018-04-05
| | | | | | | | | | | | | | | | | | | | The pmgr code is in theory common code. However there were uses of Linux stuff within this code. This patch cleans that up by deleting the unnecessary os_linux.h includes, usage of kfree() and adds several platform fields to the gk20a struct. The platform data is copied to the gk20a struct in the platform initialization code so that this common code can access said data without requiring any knowledge of the OS platform data. JIRA NVGPU-525 Change-Id: Ic4bb6021f60b0a0778779ab5f3e15b7e5ca98306 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673825 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pass alloc_gpfifo args to gk20a_channel_alloc_gpfifoSourab Gupta2018-04-05
| | | | | | | | | | | | | | | | The patch defines 'struct nvgpu_gpfifo_args' to be filled by alloc_gpfifo(_ex) ioctls and passed to the gk20a_channel_alloc_gpfifo function. This is required as a prep towards having the usermode submission support in the core channel core. Change-Id: I72acc00cc5558dd3623604da7d716bf849f0152c Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683391 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use u64 for log maskTerje Bergstrom2018-04-04
| | | | | | | | | | | | | | | BIT() is defined as returning a 64-bit value. We use it to create the log mask values, but the functions that accept log mask take only u32 as parameter. Use u64 as log mask parameter for the logging functions to match the sizes. Change-Id: I6f0803a7d04ee6a2ee725b5defc4cc14b5b7acf5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683818 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: enable rail gatingseshendra Gadagottu2018-04-03
| | | | | | | | | | | | | | | | | | Enable gpu rail gating with idle delay of 500msec. Bug 2051863 Change-Id: I1bdfc1b3db38dff871cd5d62542dd51efbd07496 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640557 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle pm suspend/resume with runtime pm disableseshendra Gadagottu2018-04-02
| | | | | | | | | | | | | | | | | | | | | When runtime pm is disabled, then gpu rail will be on as soon as nvgpu module is loaded. If pm suspend/resume called before gpu hw initialization(g->poweron = false) then pm suspend is skipping gpu railgate, which is causing issues with SC7 entry/exit. To fix this issue: 1. During pm suspend, if g->poweron is false, check for runtime pm disable to railgate gpu rail. 2. On pm resume, check for runtime pm disable to enable gpu rail, though gpu driver not initialized. Bug 2073029 Change-Id: I7631109d79cda5882d2864557f1b7b3d2d89c9f6 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1679010 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "nvgpu: Remove ASYNC PROBE for vgpu"Aniruddha Banerjee2018-04-02
| | | | | | | | | | | | | | | | This reverts commit dbdf57fb3c34227b26c1858d85c83c18d34de453. The aync-probe was causing an issue because the arm-gic set_type did not have the proper locking constructs to prevent races in gic distributor. Bug 200385192 Change-Id: Ic4f51705e58da8145845b4812c8e61e1c73932cd Signed-off-by: Aniruddha Banerjee <aniruddhab@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1676616 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: set apply_ctxsw_timeout and ch_wdt_timeout_msVijayakumar2018-03-30
| | | | | | | | | | | | | | | -set apply_ctxsw_timeout_intr to NULL. This was added as part of DNI change SHA 1f71f475e25fe786ec76d76a986aac8afec51b01 -change ch_wdt_timeout_ms from 30ms to 7ms Bug 2040544 Bug 2069807 Change-Id: I9125207146e1e3e42325ecda6a2aa7f1c07fdd3a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683719 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix memory leaks in error pathDeepak Nibade2018-03-23
| | | | | | | | | | | | | | | | | | | Error path is not implemented in nvgpu_pci_probe(), and that could lead to memory leaks if any of the step in nvgpu_pci_probe() fails Fix this by implementing error path and freeing all allocated buffers Bug 200291879 Coverify defect id : 2845621 Change-Id: Iee1abb041089e47a517a6698f0a4067c9c4fa289 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1681028 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: disallow invalid syncpoint wait idsKonsta Holtta2018-03-23
| | | | | | | | | | | Instead of ignoring a wait when a raw syncpoint prefence has an invalid id, reject the submit with -EINVAL just like with syncpoints in syncfds. Change-Id: I9b5c417bd1c7cd081c79659d088ac2c915de8c0e Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1680281 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allow syncfds as prefences on deterministicKonsta Holtta2018-03-23
| | | | | | | | | | | | | | | | | | | | | | Accept submits on deterministic channels even when the prefence is a syncfd, but only if it has just one fence inside. Because NVGPU_SUBMIT_GPFIFO_FLAGS_SYNC_FENCE is shared between pre- and postfences, a postfence (SUBMIT_GPFIFO_FLAGS_FENCE_GET) is not allowed at the same time though. The sync framework is problematic for deterministic channels due to certain allocations that are not controlled by nvgpu. However, that only applies for postfences, yet we've disallowed FLAGS_SYNC_FENCE for deterministic channels even when a postfence is not needed. Bug 200390539 Change-Id: I099bbadc11cc2f093fb2c585f3bd909143238d57 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1680271 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check sema pool alloc failure properlyKonsta Holtta2018-03-23
| | | | | | | | | | | | | | | | | | | | nvgpu_semaphore_pool_alloc() returns an ERR_PTR instead of NULL which the caller checks on failure. Common code should not use ERR_PTRs though, so modify nvgpu_semaphore_pool_alloc() to return error code separately and fix nvgpu_init_sema_pool() to consider this. Jira NVGPU-513 Change-Id: I435c0d2794d226774ed4c6b3bcbdde1e741854d8 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673458 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set safe state for user managed syncpointsDeepak Nibade2018-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | MAX/threshold value of user managed syncpoint is not tracked by nvgpu So if channel is reset by nvgpu there could be waiters still waiting on some user syncpoint fence Fix this by setting a large safe value to user managed syncpoint when aborting the channel and when closing the channel We right now increment the current value by 0x10000 which should be sufficient to release any pending waiter Bug 200326065 Jira NVGPU-179 Change-Id: Ie6432369bb4c21bd922c14b8d5a74c1477116f0b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1678768 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove traces in nvgpu_clk_set_infoThomas Fleury2018-03-21
| | | | | | | | | | | | | | | | | | | Cleanup superfluous traces in nvgpu_clk_set_info. Jira DNVGPU-210 Jira DNVGPU-211 Change-Id: I78249d7a2a11e205c808695ea76293bff8892efc Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627357 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: delete unused job->pre_fenceKonsta Holtta2018-03-19
| | | | | | | | | | | | | | | | | | | The pre_fence member in channel_gk20a_job is no longer used for anything. Delete it. Only the post fence needs to be tracked. Jira NVGPU-527 Jira NVGPU-528 Bug 200390539 Change-Id: Ia1a556728dabf9a8e305ed76020ac1aa0b4d6b88 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1676735 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove fence param from channel_syncKonsta Holtta2018-03-16
| | | | | | | | | | | | | | | | | | | The fence parameter that gets output from gk20a_channel_sync's wait() and wait_fd() APIs is no longer used for anything. Delete it. Jira NVGPU-527 Jira NVGPU-528 Bug 200390539 Change-Id: I659504062dc6aee83a0a0d9f5625372b4ae8c0e2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1676734 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove support for foreign sema syncfdsKonsta Holtta2018-03-16
| | | | | | | | | | | | | | | | | | | | Delete the proxy waiter for non-semaphore-backed syncfds in sema wait path to simplify code, to remove dependencies to the sync framework (and thus Linux) and to support upcoming refactorings. This feature has never been used for actually foreign fences. Jira NVGPU-43 Jira NVGPU-66 Change-Id: I2b539aefd2d096a7bf5f40e61d48de7a9b3dccae Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1665119 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: remove aggressive_sync_destroy_thresh check for user ↵Deepak Nibade2018-03-16
| | | | | | | | | | | | | | | | | | | | | | syncpoint" This reverts commit fb40f2a80739985abac273bc493e07341aa003af. aggressive_sync_destroy_thresh was inadvertently set for gv11b vGPU, and that is now being removed hence restore original check Bug 200397265 Bug 200326065 Change-Id: If56e1c462adb2db7d9186fbb6038169aa7ea33dc Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1676556 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: remove aggressive_sync_destroy_thresh for gv11bDeepak Nibade2018-03-16
| | | | | | | | | | | | | | | | | | | | aggressive_sync_destroy_thresh was inadvertently set for gv11b on vGPU, and that caused issues while allocating user managed syncpoint remove that threshold as it is no longer needed Bug 200397265 Bug 200326065 Change-Id: I63dfdcae1fd7b99068d07807c84775b9a9f9f95d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1676555 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Abstract get_cycles()Alex Waterman2018-03-16
| | | | | | | | | | | | | | | | | | | | | | | get_cycles is a linux specific API used in common code. This API is being used, it seems, as a method to generate time stamps. So add an API to generate 'high resolution' time stamps. This API returns an opaque time stamp: that is not something one may use directly as a time since in the Linux implementation we just use this cycle counter. Other implementations will, of course, be free to implement as a real time stamp. JIRA NVGPU-525 Change-Id: I237aac9bd6c795d000459025bdb4fce92e8aaa3d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673811 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add gpu_va to update_hwpm_ctxsw_mode parameters()Aparna Das2018-03-16
| | | | | | | | | | | | | | | | | It'll allow the function to use fixed mapping. Jira VQRM-2982 Change-Id: I98159c5b199ce1854b1b40704392237cadb71ef2 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1660225 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove aggressive_sync_destroy_thresh check for user syncpointDeepak Nibade2018-03-15
| | | | | | | | | | | | | | | | | | VGPU has set aggressive_sync_destroy_thresh even for GV11B, and that breaks allocation of user managed syncpoint on VGPU Remove this check for now until some solution is finalized Bug 200397265 Bug 200326065 Change-Id: Idd765cfdd40b9055d9e083d59c85c84d8b213ee9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1675678 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
* nvgpu: Remove ASYNC PROBE for vgpuNagaraj P N2018-03-15
| | | | | | | | | | | | | | | | | | | | | | | | Async probe of vgpu driver results in a race condition where GICD registers are being programmed incorrectly because of the race. Remove ASYNC_PROBE for vgpu driver as a WAR to prevent it. This change would be reverted after GICD register programming is serialized bug 200385192 Change-Id: I7279152867470ece93c5efbd72ac24db28878024 Signed-off-by: Nagaraj P N <nagarajp@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1674898 Reviewed-by: Sreenivasulu Velpula <svelpula@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vipin Kumar <vipink@nvidia.com> Tested-by: Vipin Kumar <vipink@nvidia.com> Reviewed-by: Sandeep Trasi <strasi@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10x PMU f/w version updateMahantesh Kumbar2018-03-15
| | | | | | | | | | | | | | | | | - Updating gp10x PMU f/w version for ucode git cl : https://git-master.nvidia.com/r/#/c/1674816/ P4 CL# : 23732390 Change-Id: I4426f7fc96b52f342ac885199e7dd3e413af4a8e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1674857 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv10x volt rail boardobj changesMahantesh Kumbar2018-03-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Created volt ops under pmu_ver to support volt_set_voltage, volt_get_voltage & volt_send_load_cmd_to_pmu. - Renamed volt load, set_voltage & get_voltage gp10x method names. - Added new volt load, set_voltage & get_voltage methods for gv10x using RPC & added code to handle ack in pmu_rpc_handler() along with struct rail_list changes. - Updated volt ops of gp106 & gv100 to point to respective methods. - Added member volt_dev_idx_ipc_vmin & volt_scale_exp_pwr_equ_idx to "struct nv_pmu_volt_volt_rail_boardobj_set" & "struct voltage_rail" made changes to update members as needed. - Added member volt_scale_exp_pwr_equ_idx to "struct vbios_voltage_rail_table_1x_entry" to read value from VBIOS table & update rail boardobj set interface. - Defines for volt RPC "NV_PMU_RPC_ID_VOLT_*" - Define struct's volt load, set_voltage & get_voltage to execute volt RPC. Change-Id: I4a41adcf7536468beaa8a73f551b1d608aabd161 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1659728 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: init soc vars from nvgpu_probeThomas Fleury2018-03-14
| | | | | | | | | | | | | | | | | | | Invoke nvgpu_init_soc_vars from common nvgpu_probe instead of pci specific nvgpu_pci_tegra_probe. Bug 200392719 Change-Id: Ibb0474f2497234ba2e393790020af89a0266f5df Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1674016 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Bhosale <dbhosale@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Pass correct va_allocated field in .gmmu_unmap()Alex Waterman2018-03-14
| | | | | | | | | | | | | | | | | | | | | When nvgpu maps an nvgpu_mem struct the nvgpu driver has a choice of either using a fixed or non-fixed mapping. For non-fixed mappings the GMMU APIs allocate a VA space for the caller. In that case the GMMU APIs must also free that VA range when nvgpu unmaps the nvgpu_mem. For fixed mappings the GMMU APIs must instead not manage the life time of the VA space. To support these two possibilities add a field to nvgpu_mem that specifies whether the GMMU APIs must or must not free the GPU VA range during the GMMU unmap operation. Also fix a case in the nvgpu vm_area code that would double free a VA allocation in some cases (sparse allocs). Change-Id: Idc32dbb8208fa7c1c05823e67b54707fea51c6b7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1669920 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Updated RPC to support copyback & callbackMahantesh Kumbar2018-03-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Updated & added new parameter "bool is_copy_back" to nvgpu_pmu_rpc_execute() to support copy back processed RPC request from PMU to caller by passing parameter value true & this blocks method till it receives ACK from PMU for requested RPC. - Added "struct rpc_handler_payload" to hold info required for RPC handler like RPC buff address & clear memory if copy back is not requested. - Added define PMU_RPC_EXECUTE_CPB to support to copy back processed RPC request from PMU to caller. - Updated RPC callback handler support, crated memory & assigned default handler if callback is not requested else use callback parameters data to request to PMU. - Added define PMU_RPC_EXECUTE_CB to support callback - Updated pmu_wait_message_cond(), restricted condition check to 8-bit instead 32-bit condition check. Change-Id: Ic05289b074954979fd0102daf5ab806bf1f07b62 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1664962 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PMU nv_pmu_boardobj & queue updateMahantesh Kumbar2018-03-13
| | | | | | | | | | | | | | | | | | | | | | | | | - Updated "struct nv_pmu_boardobj, nv_pmu_boardobj_query & nv_pmu_boardobjgrp_super" by adding new members as per gv10x PMU ucode boardobj interface. - Created "PMU_QUEUE_COUNT_FOR_V5 4" for gv10x PMU ucode - Created "PMU_QUEUE_MSG_IDX_FOR_V5 3" for gv10x PMU ucode - Deleted unused "PMU_QUEUE_MSG_IDX_FOR_4" - Updating "APP_VERSION_GV10X 23616379" for ucode git CL: https://git-master.nvidia.com/r/#/c/1662993/ P4 CL#: 23647491 - Updating "APP_VERSION_GP10X 22099494" for ucode git CL: https://git-master.nvidia.com/r/#/c/1662995/ P4 CL#: 23647537 Change-Id: I6e8e2b30e81422f8b529a2fad6d926f93bd73d3e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1656643 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use also normal logging with TRACE_PRINTKKonsta Holtta2018-03-13
| | | | | | | | | | | | | | | When CONFIG_GK20A_TRACE_PRINTK is set to support printing to ftrace log instead of the normal kernel log, but log_trace from debugfs is not set, fall back to normal kernel logging instead of not logging anything. Change-Id: I553baed20a52108229dbcc5c63e8af4e1bcd1b30 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1674250 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: decouple sema and hw semaKonsta Holtta2018-03-13
| | | | | | | | | | | | | | | | | | | | | | | | struct nvgpu_semaphore represents (mainly) a threshold value that a sema at some index will get and struct nvgpu_semaphore_int (aka "hw_sema") represents the allocation (and write access) of a semaphore index and the next value that the sema at that index can have. The threshold object doesn't need a pointer to the sema allocation that is not even guaranteed to exist for the whole threshold lifetime, so replace the pointer by the position of the sema in the sema pool. This requires some modifications to pass a hw sema around explicitly because it now represents write access more explicitly. Delete also the index field of semaphore_int because it can be directly derived from the offset in the sema location and is thus unnecessary. Jira NVGPU-512 Change-Id: I40be523fd68327e2f9928f10de4f771fe24d49ee Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1658102 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: add IPA to PA translationThomas Fleury2018-03-13
| | | | | | | | | | | | | | | | | | | | | | | Add IPA to PA translation for GV100 nvlink / pass-through mode - define platform->phys_addr(g, ipa) method - call nvgpu_init_soc_vars from nvgpu_tegra_pci_probe - in nvgpu_init_soc_vars, define set platform->phys_addr to nvgpu_tegra_hv_ipa_pa, if hypervisor is present. - in __nvgpu_sgl_phys, use sg_phys, then apply platform->phys_addr if defined. - implement IPA to PA translation in nvgpu_tegra_hv_ipa_pa Bug 200392719 Change-Id: I622049ddc62c2a57a665dd259c1bb4ed3843a537 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673582 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add placeholder for IPA to PAThomas Fleury2018-03-13
| | | | | | | | | | | | | | | | Add __nvgpu_sgl_phys function that can be used to implement IPA to PA translation in a subsequent change. Adapt existing function prototypes to add pointer to gpu context, as we will need to check if IPA to PA translation is needed. JIRA EVLR-2442 Bug 200392719 Change-Id: I5a734c958c8277d1bf673c020dafb31263f142d6 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673142 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add refcounting for ctxsw disable/enableShashank Singh2018-03-12
| | | | | | | | | | | | | | | | | | | | ctxsw disable could be called recursively for RM server. Suspend contexts disables ctxsw at the beginning, then call tsg disable and preempt. If preempt timeout happens, it goes to recovery path, which will try to disable ctxsw again. More details on Bug 200331110. Jira VQRM-2982 Change-Id: I4659c842ae73ed59be51ae65b25366f24abcaf22 Signed-off-by: Shashank Singh <shashsingh@nvidia.com> Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1671716 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check for syncpt enableseshendra Gadagottu2018-03-12
| | | | | | | | | | | | | | | | Check for syncpt enable before querying for synpt ro map. Otherwise it is getting result in kernel crash with syncpt support disabled. Change-Id: Iaa13d802ec66a368f2bedd2dd1061bae29b4aaa2 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1671652 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support per-channel wdt timeoutsKonsta Holtta2018-03-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the padding in nvgpu_channel_wdt_args with a timeout value in milliseconds, and add NVGPU_IOCTL_CHANNEL_WDT_FLAG_SET_TIMEOUT to signify the existence of this new field. When the new flag is included in the value of wdt_status, the field is used to set a per-channel timeout to override the per-GPU default. Add NVGPU_IOCTL_CHANNEL_WDT_FLAG_DISABLE_DUMP to disable the long debug dump when a timed out channel gets recovered by the watchdog. Printing the dump to serial console takes easily several seconds. (Note that there is NVGPU_TIMEOUT_FLAG_DISABLE_DUMP about ctxsw timeout separately for NVGPU_IOCTL_CHANNEL_SET_TIMEOUT_EX as well.) The behaviour of NVGPU_IOCTL_CHANNEL_WDT is changed so that either NVGPU_IOCTL_CHANNEL_ENABLE_WDT or NVGPU_IOCTL_CHANNEL_DISABLE_WDT has to be set. The old behaviour was that other values were silently ignored. The usage of the global default debugfs-controlled ch_wdt_timeout_ms is changed so that its value takes effect only for newly opened channels instead of in realtime. Also, zero value no longer means that the watchdog is disabled; there is a separate flag for that after all. gk20a_fifo_recover_tsg used to ignore the value of "verbose" when no engines were found. Correct this. Bug 1982826 Bug 1985845 Jira NVGPU-73 Change-Id: Iea6213a646a66cb7c631ed7d7c91d8c2ba8a92a4 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1510898 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: don't reset semaphores to 0 on initKonsta Holtta2018-03-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With proper wrap-handling comparisons now supported, it's safe to not reset a kernel-managed semaphore to 0 when initializing it to be used by some channel; the value can be left unchanged, so that any pending waits on other channels for this sema can't get corrupted anymore. This makes semaphore values very similar to syncpoints, i.e., just monotonically increasing counters. Also clear the semaphore sea to values of 0xfffffff0 when allocating it. This way it takes 16 increments on each sema to wrap over the 32-bit integer range; such wrapping would eventually happen if the memory was initialized to zeros, so this way any bugs possibly caused by wrapping not taken into account would uncover quickly after boot. Jira NVGPU-514 Change-Id: I93f9b1d32d020a4c23824f5856bc463b1895b99d Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1652087 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Correctly plumb -EAGAIN from vidmem allocationsAlex Waterman2018-03-08
| | | | | | | | | | | | | | | | | | Userspace can and should retry vidmem allocations if there are pending clears still to be executed by the GPU. But this requires the -EAGAIN to properly propagate back to userspace. Bug 200378648 Change-Id: Ib930711270439843e043d65c2e87b60612a76239 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1669099 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: boardobj update for gv10x branchMahantesh Kumbar2018-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Created ops for below boardobj methods to support gp10x & gv10x branch boardobj changes, and defined methods for gv10x with postfix _v1 with below names boardobjgrp_pmucmd_construct_impl boardobjgrp_pmuset_impl boardobjgrp_pmugetstatus_impl is_boardobjgrp_pmucmd_id_valid - These ops are assigned based on PMU version to respective chip. - Modified BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT & BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT to support gp10x & gv10x branch changes - Updated struct boardobjgrp_pmu_cmd to include members needed for gv10x boardobj changes - Created "struct nv_pmu_rpc_struct_board_obj_grp_cmd" to execute BOARD_OBJ_GRP_CMD using RPC. - Defined method boardobjgrp_pmucmdsend_rpc() to send BOARD_OBJ_GRP_CMD to PMU. Change-Id: If2551bdda80e897e7b21d2966881586f3bbc7a9b Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1656511 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 21:08:58 -0400