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* strncpy: it should depend on size of 1st argumentdmitry pervushin2020-05-13
| | | | | | | | | | | | | | | | | | | | There is no point to depend on strlen of second argument, otherwise it could be a simple strcpy. Instead, let's make it depending on sizeof(destination) ...and make sure that result is NUL-terminated, too Bug 2973859 Change-Id: Ifc941fab07e503b7b980696950d65b8bb10bf4ff Signed-off-by: dmitry pervushin <dpervushin@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2342281 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Phoenix Jung <pjung@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: decrease refcount when sync-unmap failsddutta2020-03-05
| | | | | | | | | | | | | | | | | | | | | | | | | When nvgpu_vm_unmap_sync fails, nvgpu_unmap_sync currently bails out without decreasing the buffer refcount. This prevents from releasing the buffer, in case a deferred job completes after the timeout (which was observed 2 times during overnight stress tests). This also means that the fixed address is not re-useable. Throw out a warning when nvgpu_vm_unmap_sync fails, but proceed with decreasing refcount. Bug 200578193 Change-Id: Ie0cc7caa7d12ca0a3b42123a5f7a28bda72dabbc Signed-off-by: ddutta <ddutta@nvidia.com> (cherry picked from commit a433f26d5bb1ec3253fc2655998b1ef7fb2847cb in dev-main) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2291352 Tested-by: Naveen Kumar S <nkumars@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove blcg_enable/disableddutta2020-02-28
| | | | | | | | | | | | | | | | | | blcg is always enabled by default and there is no need for disabling this during gr init or gr reset. Bug 2866010 Change-Id: Iaf17b7fdf05ad04fe435e1a1fda758deedc6484c Signed-off-by: ddutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2303114 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: fix tsg_unbind in recovery casePeter Daifuku2020-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When unbinding a channel from a tsg when virtual, vgpu_tsg_unbind_channel would return an error if unbinding the channel on the guest side failed, and did so before notifying the RM server of the unbind. Later on in the recovery process, the guest OS would remove the channel from the TSG's list, but this would leave the RM server with an out-of-date channel list. Fix this by making the tsg_unbind_channel HAL optional and implemented only for vgpu: the vgpu version now just notifies the RM server so that it can clean up its version of the TSG; if vgpu, always call the tsg_unbind_channel HAL whether or not the local unbind succeeded. Minimal port from dev-main of https://git-master.nvidia.com/r/c/linux-nvgpu/+/2084029 Bug 2766920 Bug 200587845 Change-Id: I75bddf3a28ac20bf4fb7510ff64097a32c7eec3f Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287774 (cherry picked from commit 471c72c1efcc4fe6d547f556edf7773827fd2674) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2289928 Reviewed-by: Thomas Steinle <tsteinle@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: move cg_enable after pmu_init is completeDebarshi Dutta2020-02-19
| | | | | | | | | | | | | | | | | | This patch help resolve the boot time failures happening with pmu_exterr for porg. cg_enable can race with pmu_init thread, cg_enable is moved post pmu init thread to avoid the above race. Bug 200565050 Change-Id: I2192053eff8767847ea012ca20b3607d2f6cd26f Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2239959 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: use refcnt for ch mmu_debug_modeThomas Fleury2020-01-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Replaced ch->mmu_debug_mode_enabled with ch->mmu_debug_mode_refcnt. If channel is enabled multiple times by userspace, then ref count is updated accordingly. There is an expectation that enable/disable calls are balanced for setting channel's mmu debug mode. When unbinding the channel, decrease refcnt for the channel until it reaches 0. Also, removed tsg parameter from nvgpu_tsg_set_mmu_debug_mode as it can be retrieved from ch. Bug 2515097 Bug 2713590 Change-Id: If334e374a55bd14ae219edbfd3b1fce5ff25c226 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2184702 (cherry picked from commit f422aee39387a5aa337de69cc21a67f16697ae0e) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208772 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: set FB/HSMMU debug modeThomas Fleury2020-01-30
| | | | | | | | | | | | | | | | | | | | | | | Set NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL and NV_PFB_PRI_MMU_DEBUG_CTRL in addition to NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL, in NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE Bug 2515097 Bug 2713590 Change-Id: I1763b43e79fac3edb68a35980683d58bfa89519f Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2115785 (cherry picked from commit 8057514a9f7fc5f175e2e0571dfa91d78ebb6410) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208771 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add refcounting for MMU debug modeThomas Fleury2020-01-30
| | | | | | | | | | | | | | | | | | | | | | | GPC MMU debug mode should be set if at least one channel in the TSG has requested it. Add refcounting for MMU debug mode, to make sure debug mode is disabled only when no channel in the TSG is using it. Bug 2515097 Bug 2713590 Change-Id: Ic5530f93523a9ec2cd3bfebc97adf7b7000531e0 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2123017 (cherry picked from commit a1248d87fe6e20aab3e5f2e0764f9fe8d80d0552) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208769 Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: enable platform atomic featureVinod G2020-01-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support following changes related to platform atomic feature NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2 NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_NCOH_ATOMIC_MODE to USE_READ In gv11b, FBHUB_NUM_ACTIVE_LTCS register has read only privilege, so atomic mode register bits cannot be updated from kernel code. atomic capability and atomic_sys_ncoh_mode bits are copied from fb mmu_ctrl to gpcs_mmu_ctrl register. new tu104 hal for fb_enable_nvlink function. bug 200580236 Change-Id: Ia78986c1c56795c6efad20f4ba42700ef1c2c1ad Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2013481 (cherry picked from commit 251e3eaa8029c4ae07b2cde7af5d9775e1cd8ec1) Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2274932 GVS: Gerrit_Virtual_Submit Tested-by: Sreeniketh H <sh@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add platform atomic supportVinod G2020-01-08
| | | | | | | | | | | | | | | | | | | | | | | | | Add new variable in nvgpu_as_map_buffer_ex_args for app to specify the platform atomic support for the page. When platform atomic attribute flag is set, pte memory aperture is set to be coherent type. renamed nvgpu_aperture_mask_coh -> nvgpu_aperture_mask_raw function. bug 200580236 Change-Id: I18266724dafdc8dfd96a0711f23cf08e23682afc Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2012679 (cherry picked from commit 9e0a9004b71f92b7713fd3b30141b0d9d4cfa2c6) Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2274914 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Sreeniketh H <sh@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: re-enable elpg after golden img initPeter Daifuku2019-11-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Typically, the PMU init thread will finish up long before the golden context image has been initialized, which means that ELPG hasn't truly been enabled at that point. Create a new function, nvgpu_pmu_reenable_pg(), which checks if elpg had been enabled (non-zero refcnt), and if so, disables then re-enables it. Call this function from gk20a_alloc_obj_ctx() after the golden context image has been initialized to ensure that elpg is truly enabled. Manually ported from dev-main Bug 200543218 Change-Id: I0e7c4f64434c5e356829581950edce61cc88882a Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2245768 (cherry picked from commit 077b6712b5a40340ece818416002ac8431dc4138) Reviewed-on: https://git-master.nvidia.com/r/2250091 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add clock gating support for HSHUBDeepak Nibade2019-11-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add BLCG and SLCG clock gating support for HSHUB unit on gv11b Register list for BLCG and SLCG is auto generated with scripts. Add HAL operations to enable/disable HSHUB clock gating Re-generate gv11b reglist so that all the manually commented registers are automatically deleted. Some of the unicast registers are also deleted. We already have corresponding broadcast registers present. Cherry-pick/manually port from dev-main Bug 2526212 Change-Id: I2654f158daa802bcf992e103ed4a44675aa5fd4d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2150199 (cherry picked from commit e34b6f76d38ad5641c1ed7c3a4b36752d9dd4750) Reviewed-on: https://git-master.nvidia.com/r/2224708 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Luis Dib <ldib@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: channel_setup_bind: must be bound to TSGPeter Daifuku2019-10-14
| | | | | | | | | | | | | | | | | In nvgpu_channel_setup_bind, return an error if the channel isn't bound to a TSG, as future operations rely on being bound. Bug 200543218 Change-Id: If33b01b8176c7488445c23080ad9d11f341bff43 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2215160 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Luis Dib <ldib@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix PMU destroy sequenceAbhiroop Kaginalkar2019-09-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A call to exit the PMU state machine/kthread must be prioritized over any other state change. It was possible to set the state as PMU_STATE_EXIT, signal the kthread and overwrite the state before the kthread has had the chance to exit its loop. This may lead to a "lost" signal, resulting in indefinite wait during the destroy sequence. Faulting sequence: 1. pmu_state = PMU_STATE_EXIT in nvgpu_pmu_destroy() 2. cond_signal() 3. pmu_state = PMU_STATE_LOADING_PG_BUF 4. PMU kthread wakes up 5. PMU kthread processes PMU_STATE_LOADING_PG_BUF 6. PMU kthread sleeps 7. nvgpu_pmu_destroy() waits indefinitely This patch adds a sticky flag to indicate PMU_STATE_EXIT, irrespective of any subsequent changes to pmu_state. The PMU PG init kthread may wait on a call to NVGPU_COND_WAIT_INTERRUPTIBLE, which requires a corresponding call to nvgpu_cond_signal_interruptible() as the core kernel code requires this task mask to wake-up an interruptible task. Bug 2658750 Bug 200532122 Change-Id: I61beae80673486f83bf60c703a8af88b066a1c36 Signed-off-by: Abhiroop Kaginalkar <akaginalkar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2177112 (cherry picked from commit afa49fb073a324c49a820e142aaaf80e4656dcc6) Reviewed-on: https://git-master.nvidia.com/r/2190733 Tested-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: don't report max load when counter overflowLeon Yu2019-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is to prevent GPU (and thus EMC) frequency from being boosted from time to time when system is completely idle. It's caused by max GPU load being incorrectly reported by perfmon. When the issue happens, it can be observed that max load is reported but busy_cycles read from PMU is actually zero. Even though busy and total cycles returned by PMU may not be completely accurate when counter overflows, the counters accumulated so far still have some value that we shouldn't ignore. OTOH, returning max load could be the least accurate approximation in such cases. So let's just clear the interrupt status and let rest of the code handle the exception cases. Bug 200545546 Change-Id: I6882ae265029e881f5417fb2b82005b0112b0fda Signed-off-by: Leon Yu <leoyu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2180771 Reviewed-by: Peng Liu <pengliu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Mubushir Rahman <mubushirr@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use vpr resize APIVedashree Vidwans2019-08-30
| | | | | | | | | | | | | | | | | | | | This patch adds nvgpu API in linux and qnx to query vpr resize. The new API nvgpu_is_vpr_resize_enabled() is used in nvgpu_submit_channel_gpfifo(). Previously, if non-deterministic channel has timeout disabled and GPU cannot railgate on some platform, then channel doesn't power ref count and results in video freeze. This requires non-determinstic channel job tracking to be enabled if vpr resize is supported or if GPU can railgate. Bug 200532122 Change-Id: Icfbff6253762b195b2f5955749343974b1a7a269 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2167082 Reviewed-on: https://git-master.nvidia.com/r/2180581 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix race for channel sync read/writeVedashree Vidwans2019-08-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CTS test dEQP-VK.api.object_management.max_concurrent.device_group crashes with invalid userspace memory access. Currently, nvgpu_submit_prepare_syncs() races with gk20a_channel_clean_up_jobs() and this race condition is exposed when aggressive_sync_destroy_thresh is set to non-zero value. nvgpu_submit_prepare_syncs() gets ref for c->sync to submit job and releases channel sync_lock immediately. Meanwhile, gk20a_channel_worker_process() triggers gk20a_channel_clean_up_jobs(), which destroys ref'd c->sync pointer. Channel sync is deleted by gk20a_channel_clean_up_jobs() only if aggressive_sync_destroy_thresh is non-zero. So, gk20a_channel_clean_up_jobs() and nvgpu_submit_prepare_syncs() will race only in this scenario. Hence, if aggressive_sync_destroy_thresh value is non-zero, this patch protects channel's sync pointer by holding channel sync_lock during complete execution of nvgpu_submit_prepare_syncs(). Bug 2613870 Change-Id: I6f3d48aff361d1cb38c30d2ce5de276d0c55fb6f Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2180550 Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support usermode submit buffersKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import userd and gpfifo buffers from userspace if provided via NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX. Also supply the work submit token (i.e., the hw channel id) to userspace. To keep the buffers alive, store their dmabuf and attachment/sgt handles in nvgpu_channel_linux. Our nvgpu_mem doesn't provide such data for buffers that are mainly in kernel use. The buffers are freed via a new API in the os_channel interface. Fix a bug in gk20a_channel_free_usermode_buffers: also unmap the usermode gpfifo buffer. Bug 200145225 Bug 200541476 Change-Id: I8416af7085c91b044ac8ccd9faa38e2a6d0c3946 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795821 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 99b1c6dcdf328efcfe47338ad1b71a114ab7f272 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170603 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add CHANNEL_SETUP_BIND IOCTLDebarshi Dutta2019-08-15
| | | | | | | | | | | | | | | | | | | | | | | | For a long time now, the ALLOC_GPFIFO_EX channel IOCTL has done much more than just gpfifo allocation, and its signature does not match support that's needed soon. Add a new one called SETUP_BIND to hopefully cover our future needs and deprecate ALLOC_GPFIFO_EX. Change nvgpu internals to match this new naming as well. Bug 200145225 Bug 200541476 Change-Id: I766f9283a064e140656f6004b2b766db70bd6cad Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1835186 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry-picked from e0c8a16c8d474eac6723fea3980833873ab921a6 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2169882 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set channel to serviceable after it is bound to tsgSeema Khowala2019-06-15
| | | | | | | | | | | | | | | | | Channel's unserviceable status should to set to false only after channel is bound to tsg. Bug 200460037 Change-Id: I24976c673b3b08cc652d2c203b9fc1f3aaed403f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2135923 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add check for "vm->num_user_mapped_buffers"Kary Jin2019-05-31
| | | | | | | | | | | | | | | | | | | | The "nvgpu_big_zalloc()" will be failed if the passed-in argument "vm->num_user_mapped_buffers" is zero. The returned value is 16 which will bypass the NULL-check and then causes the panic. This patch adds a check on the "vm->num_user_mapped_buffers" to avoid the zero is passed-in the "nvgpu_big_zalloc()". Bug 2603292 Change-Id: I399eecf72a288e13992730651a34a6cea1ef56d1 Signed-off-by: Kary Jin <karyj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2123499 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Daniel Fu <danifu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix synchronization in nvgpu_vm_mapShih-hsin Li2019-05-09
| | | | | | | | | | | | | | | | | | | | | | The mapping early returned from nvgpu_vm_map might already be unmapped during channel clean up. Increase refcount of an already mapped buffer inside the scope of update_gmmu_lock mutex to avoid this race. Bug 200494150 Change-Id: I66d9272e42c40cd3aae7ba3bb8106ec37691bf8e Signed-off-by: Shih-hsin Li <seasonl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2114163 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vinayak Pane <vpane@nvidia.com> Reviewed-by: Daniel Fu <danifu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: protect recovery with engines_reset_mutexDebarshi Dutta2019-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename gr_reset_mutex to engines_reset_mutex and acquire it before initiating recovery. Recovery running in parallel with engine reset is not recommended. On hitting engine reset, h/w drops the ctxsw_status to INVALID in fifo_engine_status register. Also while the engine is held in reset h/w passes busy/idle straight through. fifo_engine_status registers are correct in that there is no context switch outstanding as the CTXSW is aborted when reset is asserted. Use deferred_reset_mutex to protect deferred_reset_pending variable If deferred_reset_pending is true then acquire engines_reset_mutex and call gk20a_fifo_deferred_reset. gk20a_fifo_deferred_reset would also check the value of deferred_reset_pending before initiating reset process Bug 2092051 Bug 2429295 Bug 2484211 Bug 1890287 Change-Id: I47de669a6203e0b2e9a8237ec4e4747339b9837c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2022373 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry-picked from cb91bf1e13740023903282d1c2271d9154e940ba in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2024901 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: wait for gr.initialized before changing cg/pgDebarshi Dutta2019-05-09
| | | | | | | | | | | | | | | | | | | | | | | | set gr.initialized to false in the beginning of gk20a_gr_reset() and set it to true at the end of successful execution of gk20a_gr_reset. Use gk20a_gr_wait_initialized() to enable/disable cg/pg functions to make sure engine is out of reset and initialized. Bug 2092051 Bug 2429295 Bug 2484211 Bug 1890287 Change-Id: Ic7b0b71382c6d852a625c603dad8609c43b7f20f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry-picked from 7e2f124fd12caf37172f12da8de65093622941a5 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2111038 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add cg and pg functionDebarshi Dutta2019-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new power/clock gating functions that can be called by other units. New clock_gating functions will reside in cg.c under common/power_features/cg unit. New power gating functions will reside in pg.c under common/power_features/pg unit. Use nvgpu_pg_elpg_disable and nvgpu_pg_elpg_enable to disable/enable elpg and also in gr_gk20a_elpg_protected macro to access gr registers. Add cg_pg_lock to make elpg_enabled, elcg_enabled, blcg_enabled and slcg_enabled thread safe. JIRA NVGPU-2014 Change-Id: I00d124c2ee16242c9a3ef82e7620fbb7f1297aff Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2025493 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry-picked from c90585856567a547173a8b207365b3a4a3ccdd57 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2108406 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: using pmu counters for load estimatePeng Liu2019-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | PMU counters #0 and #4 are used to count total cycles and busy cycles. These counts are used by podgov to estimate GPU load. PMU idle intr status register is used to monitor overflow. Overflow rarely occurs because frequency governor reads and resets the counters at a high cadence. When overflow occurs, 100% work load is reported to frequency governor. Bug 1963732 Change-Id: I046480ebde162e6eda24577932b96cfd91b77c69 Signed-off-by: Peng Liu <pengliu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1939547 (cherry picked from commit 34df0035194e0203f68f679acdd84e5533a48149) Reviewed-on: https://git-master.nvidia.com/r/1979495 Reviewed-by: Aaron Tian <atian@nvidia.com> Tested-by: Aaron Tian <atian@nvidia.com> Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Tested-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove gk20a_is_channel_marked_as_tsgSeema Khowala2019-03-18
| | | | | | | | | | | | | | | | | | | | | Use tsg_gk20a_from_ch to get tsg pointer for tsgid of a channel. For invalid tsgid, tsg pointer will be NULL Bug 2092051 Bug 2429295 Bug 2484211 Change-Id: I82cd6a2dc5fab4acb147202af667ca97a2842a73 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2006722 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 13f37f9c70b9ae2e0d179830cded93a0a6f86494 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2025507 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove code for ch not bound to tsgSeema Khowala2019-02-22
| | | | | | | | | | | | | | | | | | | | | | | | - Remove handling for channels that are no more bound to tsg as channel could be referenceable but no more part of a tsg - Use tsg_gk20a_from_ch to get pointer to tsg for a given channel - Clear unhandled gr interrupts Bug 2429295 JIRA NVGPU-1580 Change-Id: I9da43a2bc9a0282c793b9f301eaf8e8604f91d70 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1972492 (cherry picked from commit 013ca60edd97e7719e389b3048fed9b165277251 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2018262 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Tested-by: Debarshi Dutta <ddutta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: do not use raw spinlock for ch->timeout.lockSeema Khowala2019-02-18
| | | | | | | | | | | | | | | | | | | | | | | | | | With PREEMPT_RT kernel, regular spinlocks are mapped onto sleeping spinlocks (rt_mutex locks), and raw spinlocks retain their behaviour. Schedule while atomic can occur in gk20a_channel_timeout_start, as it acquires ch->timeout.lock raw spinlock, and then calls functions that acquire ch->ch_timedout_lock regular spinlock. Bug 200484795 Change-Id: Iacc63195d8ee6a2d571c998da1b4b5d396f49439 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2004100 (cherry picked from commit aacc33bb47aa8019c1a20b867d3722c241f7f93a in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2017923 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: abstract out timeout rewindingKonsta Holtta2019-02-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The channel timeout ends up in a strange state during timeout handling for a brief moment; it can become stopped and started again, and the timeout lock is released in the middle. Add a more explicit rewind function to reset the timeout to start if it's active. The active check allows to use this from gk20a_channel_timeout_restart_all_channels(), so that's also modified. Also replace the return statements with more readable control flow in gk20a_channel_timeout_handler(). Bug 200484795 Change-Id: Ia7d67242dfc149ace1f4f841a837e90b6c985308 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1989327 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry picked from commit 8979a97af3dbb65904f9db8a22a6a168a3f41447 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2017922 Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check ch_timedout for poll/restartSeema Khowala2019-02-13
| | | | | | | | | | | | | | | | | | | | | | | | poll_timeouts and timeout_restart_all_channels should only handle channels that have not been recovered/aborted. Check ch_timedout status of the channel to make sure channel is still alive to be used. A channel reference could still be available even if it is recovered but not closed. Bug 2404865 Change-Id: I016c8b9952ef1d4c349c2a2a2ca55cb81326d380 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1929339 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit def687d4dfbc92dbc8a13781f8cee606eab4f3f3 in rel-32) Reviewed-on: https://git-master.nvidia.com/r/2016995 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: do not suspend/resume recovered channelSeema Khowala2019-02-13
| | | | | | | | | | | | | | | | | | | | | | Already torn down channels should not be suspended or resumed. A channel reference could still be available even if it is recovered but not closed. Use ch_timedout status to check if channel is already recovered/aborted. Bug 2404865 Change-Id: I718eab6032ee94a9322da7a239a978b388de2b01 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1929338 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 88cff206ae31999240945a870683e8a10be584d7 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2016994 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename has_timedout and make it thread safeSeema Khowala2019-02-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently has_timedout variable is protected by wmb at places where it is being set and there is no correspoding rmb whenever has_timedout variable is read. This is prone to errors for concurrent execution. This change is supposed to fix this issue. Rename has_timedout variable of channel struct to ch_timedout. Also to avoid rmb every time ch_timedout is read, ch_timedout_spinlock is added to protect ch_timedout variable for taking care of concurrent execution. Bug 2404865 Bug 2092051 Change-Id: I0bee9f50af0a48720aa8b54cbc3af97ef9f6df00 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1930935 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 1f54ea09e3445d9ca3cf7a69b4967849cc9defc8 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2016975 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: replace input param chid with pointer to channelDebarshi Dutta2019-02-11
| | | | | | | | | | | | | | | | | | | | | | | | | preempt_channel needs to use the channel to pass it to other public functions, get access to a tsg etc. This qualifies it to take a pointer to a channel as an input parameter instead of a chid. Increment the channel ref counter using the function gk20a_channel_from_id in functions where we get the chid from the h/w registers directly. Once the prempt_channel function call is done, use a gk20a_channel_put on the referenced channel. Jira NVGPU-1461 Change-Id: I6c87c8104cfcb418d468c8c590087fd4aeabf4bd Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1963200 (cherry picked from commit 9abe9fe062367902ede7721cff55396859f8e4e8 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2013728 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: replace tsgid input variable with pointer to a struct tsg_gk20aDebarshi Dutta2019-02-11
| | | | | | | | | | | | | | | | | | | | | | replace tsgid with a pointer to a struct tsg_gk20a in the function gk20a_fifo_tsg_abort(). gk20a_fifo_tsg_abort needs to enumerate through all the channels within the tsg as well as pass the tsg pointer to other functions, qualifying the need to use a pointer instead as an input parameter. Jira NVGPU-1461 Change-Id: I59cec05d5d778f733d0c3e9ffadf46e74e249080 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1956567 (cherry picked from commit e5bebd880f28fe719c5e01e165fb189e7cafee01 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2013724 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add safe channel id lookupKonsta Holtta2019-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add gk20a_channel_from_id() to retrieve a channel, given a raw channel ID, with a reference taken (or NULL if the channel was dead). This makes it harder to mistakenly use a channel that's dead and thus uncovers bugs sooner. Convert code to use the new lookup when applicable; work remains to convert complex uses where a ref should have been taken but hasn't. The channel ID is also validated against FIFO_INVAL_CHANNEL_ID; NULL is returned for such IDs. This is often useful and does not hurt when unnecessary. However, this does not prevent the case where a channel would be closed and reopened again when someone would hold a stale channel number. In all such conditions the caller should hold a reference already. The only conditions where a channel can be safely looked up by an id and used without taking a ref are when initializing or deinitializing the list of channels. Jira NVGPU-1460 Change-Id: I0a30968d17c1e0784d315a676bbe69c03a73481c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1955400 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 7df3d587502c2de997dfbe8ea8ddc114d0a0481e in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2008515 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gm20b: clear priv intr in log_pending_intrsSeema Khowala2019-02-02
| | | | | | | | | | | | | | | | | | | | | Clear pending priv interrupt in log_pending_intrs. Priv ring errors have not been cleaned up in gm20b. It is ok to just clear it. Bug 200477291 Bug 200486293 Change-Id: I850a261828a9d49b6b4a82d75f5347acbc17b0fe Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2008818 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Tested-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove unnecessary error print of falcon queueMahantesh Kumbar2018-12-26
| | | | | | | | | | | | | | | | | | | | | | | | | -For queue full there is pmu_dbg message & returned with EAGAIN error to end caller for retry, so intermediate error message is not correct print for queue full. Bug 200477085 Bug 200477931 Bug 200475876 Change-Id: I1109f15d0815f4ab2d8f8ca303db447d856f372c Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> (cherry picked from commit I263f66f7a8d8f1b98985f32f9daa49b09309c359) Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1979935 Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Tested-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com>
* nvgpu: pmu: cleanup init thread on destroyPeter Daifuku2018-12-15
| | | | | | | | | | | | | | | | | | | | | | | | In nvgpu_kill_task_pg_init(), call nvgpu_thread_join() if the init thread is no longer running in order to reclaim thread resources. Bug 2452799 JIRA ESRM-437 Change-Id: Id9c67f689027f00039ac2df226ee9c28ad89dd1d Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1967983 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1970058 Reviewed-by: Shmuel Ungerfeld <sungerfeld@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Tested-by: Shmuel Ungerfeld <sungerfeld@nvidia.com> Reviewed-by: Rahul Jain (SW-TEGRA) <rahuljain@nvidia.com>
* gpu: nvgpu: disable/clear PMU IRQs on power offSagar Kamble2018-11-20
| | | | | | | | | | | | | | | | | | | | | | While tearing down PMU state during power off, nvgpu doesn't disable the PMU interrupts. Disable them unconditionally. Bug 200457485 Change-Id: Ia2462d879c1e7bbb4b5e8295ce211c38567c13e5 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1939025 Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1951361 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: Bibek Basu <bbasu@nvidia.com>
* gpu: nvgpu: Fix comment in priv_cmd_buf allocationAlex Waterman2018-11-16
| | | | | | | | | | | | | | | | | | | Update the comment to fix obvious issues and describe the new allocation logic. Bug 2327792 Change-Id: Ica0dd4159467e3023cc487a2bf9f525db3ad76e6 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1831096 (cherry picked from commit c64f9432b13d47a791220578e823efcae4fe2a80) Reviewed-on: https://git-master.nvidia.com/r/1949221 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: James Norton <jnorton@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Make priv_cmd_buf honor num_in_flight jobsAlex Waterman2018-11-16
| | | | | | | | | | | | | | | | | | | | | | If num_in_flight jobs is set use that to determine the proper size of the priv_cmd_buf. If num_in_flight is not set then use the original logic: the priv_cmd_buf is sized based on a worst case assumption for the GPFIFO. Also clean up MISRA issues. Bug 2327792 Change-Id: Ie192caeb6cc48fdcac57e5cbb71c534aeaf46011 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1831095 (cherry picked from commit b9ec592f1d3ce23db736ff9c36eab994fc86ed46) Reviewed-on: https://git-master.nvidia.com/r/1949220 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: James Norton <jnorton@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use deterministic flag to decide pre-allocAlex Waterman2018-11-16
| | | | | | | | | | | | | | | | | | | | | | Instead of using num_inflight_jobs to determine whether to pre-alloc resources for a channel use the c->deterministic flag and the number of inflight jobs field. Non-determinsitic channels do not require pre-alloced resources and deterministic channels with 0 in flight jobs (i.e no kernel job tracking, AKA fast path sumits) also do not require pre-alloced resources. Bug 2327792 Change-Id: I7e8eb0478c22e005ca2c46c555415afa0ded0be1 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1850123 (cherry picked from commit 05ec7b80ebeabbc27d369ebd88dfe511c30d1bad) Reviewed-on: https://git-master.nvidia.com/r/1949219 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: James Norton <jnorton@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove VPR HALs from dGPUsDeepak Nibade2018-09-29
| | | | | | | | | | | | | | | | | | | | gops.fb.dump_vpr_wpr_info() accesses both VPR and WPR registers. Split this into two different HALs gops.fb.dump_vpr_info() and gops.fb.dump_wpr_info() Also unset HALs accessing VPR registers on dGPUs We don't support VPR on dGPUs Remove fb_mmu_vpr_info_r() register and all its accessors from dGPU headers Bug 2173122 Change-Id: I5b2712f8c5389e422a84c375a7e836add48bfd1c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1850947 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Update PMU ucode version.Deepak2018-09-28
| | | | | | | | | | | | | | | | | | | | | | | | PMU ucode is updated to use acrlib from t19xbringup branch. We are seeing build issues due to incompatibility with acrlib from tegra_acr branch. CTX_DMA aperture to be used for loading LS falcons needed update in the local acrlib. Bug 2400729. Change-Id: Iad00a332acfac307c389bde504893a87abaf7460 Signed-off-by: Deepak <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1849182 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: SEC2 RTOS support s/w initMahantesh Kumbar2018-09-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Created struct nvgpu_sec2 to hold members related to SEC2-RTOS ucode support in header file sec2.h -Created nvgpu_sec2 variable under struct gk20a. -Created NVGPU_SUPPORT_SEC2_RTOS enable flag to enable SEC2 RTOS support. -Defined method nvgpu_init_sec2_support() to init SEC2 RTOS support by performing s/w setup like mutex-init, sequence-init & add support for remove_support. -Defined method nvgpu_sec2_destroy() to deinit SEC2 RTOS support. -Added nvgpu_init_sec2_support()/nvgpu_sec2_destroy() as part gk20a_finalize_poweron()/gk20a_prepare_poweroff() sequence based on NVGPU_SUPPORT_SEC2_RTOS enable flag -Assigned g->sec2->flcn to point to g->sec2_flcn to access falcon. -Made Makefile changes to include sec2.c to build JIRA NVGPUT-80 Change-Id: Icdc8c25994e305427ad465a5a20e9ce533759a9e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1791955 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move FB reset to MC unitTerje Bergstrom2018-09-27
| | | | | | | | | | | | FB reset is done by accessing MC register. Move the code to MC unit. JIRA NVGPU-954 Change-Id: I1636887af805f016da5490af65e808f9ac015cde Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1823385 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add MC APIs for reset masksTerje Bergstrom2018-09-27
| | | | | | | | | | | | | | Add API for querying reset mask corresponding to a unit. The reset masks need to be read from MC HW header, and we do not want all units to access Mc HW headers themselves. JIRA NVGPU-954 Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1823384 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Standardize HAS_SYNCPOINTs checkAlex Waterman2018-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nvgpu uses many ways to check if sync points are enabled. The four ways used to be: platform->has_syncpoints g->has_syncpoints nvgpu_is_enabled(g, NVPGU_HAS_SYNCPOINTS) gk20a_platform_has_syncpoints() This patch standardizes all usage to now be nvgpu_has_syncpoints() which is based on gk20a_platform_has_syncpoints() - just renamed to be general to nvgpu. All usage of the other forms have now been consolidated. However, under the hood nvgpu_has_syncpoints() does check the is_enabled flag. This flag is now set where g->has_syncpoints used to be set based on the platform data. The basic dependency chain is this: nvgpu_has_syncpoints -> NVGPU_HAS_SYNCPOINTS -> platform->has_syncpoints However, note: there are several places where syncpoints can be disabled if some other driver initialization fails (for ex. host1x). Also note that nvgpu_has_syncpoints() also considers a disable variable set by debugfs. Bug 2327574 Change-Id: Ia2375a80f5f2e27285e6175568dd13e6bb25fd33 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803975 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add support to load dbg/prod mem_unlock ucodeMahantesh Kumbar2018-09-27
| | | | | | | | | | | | | | | | | | | -Add support to load dbg/prod mem_unlock ucode based on debug Signal SCP_CTL_STAT_DEBUG_MODE. -Defined MEM_UNLOCK_PROD_BIN & MEM_UNLOCK_DBG_BIN to hold dbg/prod ucode names. JIRA NVGPUT-76 Change-Id: Ie282a281fe502ada31a69e3b3c734e9a3a725395 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1842880 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 22:42:37 -0400