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* gpu: nvgpu: make cbc alloc os specificAparna Das2018-08-09
| | | | | | | | | | | | | | | | | | | | | CBC base needs to be aligned to 64KB. On Linux this is achieved making compbit backing size multiple of 64KB. However QNX nvmap alloc function does not allocate memory aligned to requested size and needs to overallocate to satisfy alignment requirement. Make cbc alloc function OS specific to be able to modify QNX code. Also align cbc base address to 64KB before writing to CBC BASE register. Bug 200426427 Change-Id: Ic867501403f2e2a4ba41ad5a8ed6f9c5c8ffa3f4 Signed-off-by: Aparna Das <aparnad@nvidia.com> (cherry picked from commit 3f1e1133a46ebfc9763c649d7b839d069cae5a36) Reviewed-on: https://git-master.nvidia.com/r/1786046 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add PMU rpc replyVaikundanathan S2018-08-09
| | | | | | | | | | | | | | | | | Add reply messages for Therm, clock and Perf. Bug 200428344 Change-Id: Ifb325d546a81f6810ac88b87cc10b718d279ac82 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1792825 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove clk_arb.h to gk20a.h circular dependencyDebarshi Dutta2018-08-08
| | | | | | | | | | | | | | | | | clk_arb.h and gk20a.h has circular dependencies to each other. This is removed by forward declaring struct gk20a in clk_arb.h and removing the header gk20a.h from clk_arb.h and similarly forward declaring struct nvgpu_clk_arb in gk20a.h and removing the header clk_arb.h from gk20a.h alongwith putting headers in every execution unit which calls clk_arb.h related methods. JIRA NVGPU-597 Change-Id: I7cedca17206c148b21d93e5d7f0d88c2f98b979a Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1790915 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move ce2.c to common codeSourab Gupta2018-08-08
| | | | | | | | | | | | | | | | | | | ce2.c is free of all Linux'isms and can be moved to the common code, so that it can be used by other OS'es. VQRM-3705 Change-Id: Id4644a24188e9af2ba5f6875d1b8bc58b4450519 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1792100 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Lakshmanan M <lm@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: common: Fix MISRA 15.6 violationsSrirangan2018-08-02
| | | | | | | | | | | | | | | | | | This fixes errors due to single statement loop bodies without braces, which is part of Rule 15.6 of MISRA. This patch covers in gpu/nvgpu/common/ JIRA NVGPU-989 Change-Id: Ic6a98a1cd04e4524dabf650e2f6e73c6b5a1db9d Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1786207 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon queue supportMahantesh Kumbar2018-07-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Renamed "struct pmu_queue" to "struct nvgpu_falcon_queue" & moved to falcon.h -Renamed pmu_queue_* functions to flcn_queue_* & moved to new file falcon_queue.c -Created ops for queue functions in struct nvgpu_falcon_queue to support different queue types like DMEM/FB-Q. -Created ops in nvgpu_falcon_engine_dependency_ops to add engine specific queue functionality & assigned correct HAL functions in hal*.c file. -Made changes in dependent functions as needed to replace struct pmu_queue & calling queue functions using nvgpu_falcon_queue data structure. -Replaced input param "struct nvgpu_pmu *pmu" with "struct gk20a *g" for pmu ops pmu_queue_head/pmu_queue_tail & also for functions gk20a_pmu_queue_head()/ gk20a_pmu_queue_tail(). -Made changes in nvgpu_pmu_queue_init() to use nvgpu_falcon_queue for PMU queue. -Modified Makefile to include falcon_queue.o -Modified Makefile.sources to include falcon_queue.c Change-Id: I956328f6631b7154267fd5a29eaa1826190d99d1 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1776070 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix MISRA Rule 11.6 issue with _THIS_IP_Scott Long2018-07-30
| | | | | | | | | | | | | | | | | | | | | | | | | The use of the _THIS_IP_ macro in nvgpu introduces two separate MISRA Rule 11.6 violations. The first is when when the label address (which gcc generates as a void *) is cast to an unsigned long and the second is when that unsigned long is cast back to a void * in the timer and kmem code that track the value. Skipping the intermediate use of unsigned long eliminates these violations. To do this, references to _THIS_IP_ are replaced with a new (compliant) _NVGPU_GET_IP_ macro. JIRA NVGPU-895 : MISRA Rule 11.6 violations Change-Id: I5ea999d8e2b467257fa190b485fa971adcbd0a2b Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774531 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gk20a: nvgpu: Remove io.h dependency from gk20a.hDebarshi Dutta2018-07-30
| | | | | | | | | | | | | | | | In the current code, gk20a.h includes io.h which gets directly included in a lot of other files. io.h contains methods which uses a struct gk20a as a parameter leading to a circular dependency between io.h and gk20a.h. This can be mitigated by removing io.h from gk20a.h as part of larger effort to moving gk20a.h to nvgpu/gk20a.h JIRA NVGPU-597 Change-Id: I93e504fa9371b88152737b342a75580c65e8f712 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1787316 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: shutdown nvlink in driver removeNitin Kumbhar2018-07-26
| | | | | | | | | | | | | During driver remove, if nvlink is set up, gracefully shut it down so that it can be enumerated again. Bug 1987855 Change-Id: Ibd83a5e29364b22264e689aa879569a9cccf0f79 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1746073 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Rearrange the static inline codeVinod G2018-07-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to avoid the circular dependencies, rearrange the static inline functions from gk20a.h file. Moved gk20a_gr_flush_channel_tlb function to gr_gk20a.c and removed the #include gr_gk20a.h from gk20a.h Added a helper function utils.h to move all generic static inline functions which have no reference to gpu related structures. ptimer related functions are moved to ptimer.h Implementations for as and pmu are moved to corresponding files. JIRA NVGPU-624 Change-Id: I4e956326e773ba037bf3a1696cc4c462085dbbe5 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1781941 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: do not access register in vidmem destroyAparna Das2018-07-20
| | | | | | | | | | | | | | | | | | | | Do vidmem destroy only if get_vidmem_size HAL op is set which will skip this for iGPU. Do not read vidmem size explicitly in vidmem destroy in shutdown path after prepare poweroff. Bug 200427479 Change-Id: Ic919b03d44b5505646b449fd74f9f5d3e9e0dfee Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1776388 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: disable fb fault buffer in prepare poweroffAparna Das2018-07-20
| | | | | | | | | | | | | | | FB fault buffer is enabled on finalize poweron. Disable the buffer in prepare poweroff. This also eliminates the need to disable the buffer in fault info mem destroy which otherwise accesses GPU registers after these are locked in prepare poweroff. Bug 200427479 Change-Id: I1ca3e6ed4417847731c09b887134f215a2ba331c Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1776387 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rework ecc structure and sysfsRichard Zhao2018-07-19
| | | | | | | | | | | | | | | | | | | | | - create common file common/ecc.c which include common functions for add ecc counters and remove counters. - common code will create a list of all counter which make it easier to iterate all counters. - Add chip specific file for adding ecc counters. - add linux specific file os/linux/ecc_sysfs.c to export counters to sysfs. - remove obsolete code - MISRA violation for using snprintf is not solved, tracking with jira NVGPU-859 Jira NVGPUT-115 Change-Id: I1905c43c5c9b2b131199807533dee8e63ddc12f4 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1763536 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "Revert: GV11B runlist preemption patches"Seema Khowala2018-07-19
| | | | | | | | | | | | | | | | | | | This reverts commit 0b02c8589dcc507865a8fd398431c45fbda2ba9c. Originally change was reverted as it was making ap_compute test on embedded-qnx-hv e3550-t194 fail. With fixes related to replacing tsg preempt with runlist preempt during teardown, preempt timeout set to 100 ms (earlier this was set to 1000ms for t194 and 3000ms for legacy chips) and not issuing preempt timeout recovery if preempt fails, helped resolve the issue. Bug 200426402 Change-Id: If9a68d028a155075444cc1bdf411057e3388d48e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1762563 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: remove device only if it is presentSeema Khowala2018-07-19
| | | | | | | | | | | | | | | nvlink can be disabled via DT. Check if nvlink device is present before calling nvlink specific functions to remove the device during shutdown. Change-Id: I33480425e2991c008f02dac989b56f21a54aa902 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1779381 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add L2 register read-backs following writesVinod G2018-07-14
| | | | | | | | | | | | | | | | | | | LTC register write is followed by a register read and if data doesn't match code will report the error. Renamed existing nvgpu_writel_check function as nvgpu_writel_loop as it loops until the write get success. nvgpu_writel_check function write and read back and compare the data. Bug 2039150 Change-Id: I0a49be36aad23936f2d58aa82872710827da1d32 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1762344 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move FB to commonTerje Bergstrom2018-07-12
| | | | | | | | | | | | Move all FB HAL implementations to common/fb. JIRA NVGPU-596 Change-Id: Id4ea09d608f5d6d1b245bddac09ecf1444b8ab30 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769724 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Simplify FB hub intr enableTerje Bergstrom2018-07-11
| | | | | | | | | | | | Hard code flags for enabling and disabling FB hub interrupts. JIRA NVGPU-714 Change-Id: I806ef443cb9e27e221d407d633ca91d8fb40d075 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769853 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gcc 7.3 warning fixesStephen Warren2018-07-11
| | | | | | | | | | | | | | | | | | | gcc-7 warns about switch statements without a break statement unless a comment is present to indicate a deliberate fall through. Add such a comment to allow compilation with gcc-7.3. Bug 2224634 Change-Id: I27feec62100983e211ffd430f013d30ca56909b9 Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769564 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon code cleanupMahantesh Kumbar2018-07-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | -Created common falcon function nvgpu_flcn_bl_bootstrap() to bootstrap falcon bootloader -Created HAL gk20a_falcon_bl_bootstrap() which does actual bootloader bootstrap by fetching parameters and loading code/parameters as needed. -Created HAL ops bl_bootstrap under nvgpu_falcon_ops. -Created struct nvgpu_falcon_bl_info to hold info required for bootloader to pass to common function -Removed falcons bootstrap code in multiple file & made changes to fill struct nvgpu_falcon_bl_info & call nvgpu_flcn_bl_bootstrap(). Change-Id: Iee275233915ff11f9afb5207ac0c3338ca9dacc1 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1756104 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pmu: Fix pmu_state state updateDeepak Bhosale2018-07-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Commit c61e21c868246faf7a9ffc812590941fc362af17 fixed race codition in PMU state transition. - The race condition is such that PMU response(intr callback for messages) can run faster than kthread posting commands to PMU and thus PMU message callback may skip important pmu state change. - Commit c61e21c868246faf7a9ffc812590941fc362af17 introduced a fix where PMU state change was only updated from callback while other places can only update pmu_state variable - However, this commit introduced a regression as follows: - When PMU state is PMU_STATE_INIT_RECEIVED, we loop over every engine supported by GPU --> If state = PMU_STATE_INIT_RECEIVED, change the state to PMU_STATE_ELPG_BOOTING and init ELPG else If state != PMU_STATE_INIT_RECEIVED throw an error saying "PMU INIT not received" - Now, if GPU supports multiple engines, first engine will check that pmu_state is PMU_STATE_INIT_RECEIVED and change it to PMU_STATE_ELPG_BOOTING However, from second engine onwards, since state is already changed to PMU_STATE_ELPG_BOOTING, all engines except first engine start throwing error "PMU INIT not received" - This patch fixes the issue by changing pmu state from PMU_STATE_INIT_RECEIVED to PMU_STATE_ELPG_BOOTING only once. Bug 200372838 JIRA EVLR-2164 Change-Id: Ic8c954d14acb1d6ec3adcbc4bcf4d4745542d9f0 Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769814 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-by: Aparna Das <aparnad@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move can_railgate to enabled.hKonsta Holtta2018-07-04
| | | | | | | | | | | | | The g->can_railgate flag is a global constant-ish property like the rest of the flags behind nvgpu_is_enabled() API, so move it there. Bug 200327089 Change-Id: Id1f2f16ea1975a03fb56f10c2f3c8c705574e341 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1764266 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: reject submits when usermode is onKonsta Holtta2018-07-03
| | | | | | | | | | | | | | | | | Kernel mode submits conflict with user submits, so don't allow them if a channel user has asked for usermode submit support. Bug 200145225 Change-Id: I3a99222b09260a1b3e116c6aa86d8da5d380d903 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1767907 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: GPU_NEXT PMU ucode version updateMahantesh Kumbar2018-07-02
| | | | | | | | | | | | | | | | | - Enable ECC interrupt in Falcon interrupt source - Enable routing of ECC interrupt to HOST. code CL: https://git-master.nvidia.com/r/#/c/1758176/ p4 CL# 24408680 Change-Id: Ib43c80be64e29ccbc6b19168e67ac6f4d200b2d8 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1758175 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement common nvgpu_mem_rd* functionsTerje Bergstrom2018-07-02
| | | | | | | | | | | | | | | | | nvgpu_mem_rd*() functions were implemented per OS. They also used nvgpu_pramin_access_batched() and implemented a big portion of logic for using PRAMIN in OS specific code. Make the implementation for the functions generic. Move all PRAMIN logic to PRAMIN and simplify the interface provided by PRAMIN. Change-Id: I1acb9e8d7d424325dc73314d5738cb2c9ebf7692 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1753708 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move the unlock in nvgpu_vm_area_free againAlex Waterman2018-06-29
| | | | | | | | | | | | | | | | Move the lock release to cover the g->ops.mm.gmmu_unmap() call as well since this too must be called under the VM lock. Bug 2156667 Change-Id: I17d819d1341e211a3d0bd0ecb7cf09884eaca767 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1764598 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use explicit phys address for pci simulationDeepak Nibade2018-06-29
| | | | | | | | | | | | | | | | | | | | nvgpu_mem_get_addr() gets virtual/phys address depending on the platform. But we need to explicitly use physical addresses to configure PCI simulation support since simulator expects physical address only Hence use nvgpu_mem_get_phys_addr() explicitly to configure msg/send/recv buffers needed for pci simulation support Jira NVGPUT-41 Change-Id: I6870feef35fe81d43189fa048dc2f7052926bcc4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1756843 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Keep lock while unreffing mappingsAlex Waterman2018-06-28
| | | | | | | | | | | | | | | | | | In the vm_area free code, when unreffing the mappings owned by the vm_area, we need to continue holding the VM lock. Also add a comment specifying this requirement in the VM code. Bug 2156667 Change-Id: If0b430f045e4c585fcba2d3176163e5b19be8326 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1763235 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove nvgpu_mem_{begin,end}()Konsta Holtta2018-06-28
| | | | | | | | | | | | | | | The NVGPU_DMA_NO_KERNEL_MAPPING flag is going away, and these functions are no longer used. Delete them. Change-Id: I0084d64c92783dd65306871e5cf6bd6366087caf Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761581 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: don't nvgpu_mem_{begin,end}() sim bufsKonsta Holtta2018-06-28
| | | | | | | | | | | | | | | nvgpu_dma_alloc_sys() gives cpu-mapped memory by default. Remove the explicit calls to map and unmap the sim buffers. Change-Id: Icf71961c16a8b2f5dae24382cc927c7a802a769a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761580 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove {map,unmap}_gmmu_pages()Konsta Holtta2018-06-28
| | | | | | | | | | | | | | | The GPU page tables are always mapped to the CPU now, so they don't need the nvgpu_mem_{begin,end}() calls. Change-Id: Ic48eeed3a6f002c78f89ef07922cddf835337de3 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761579 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move submit code to commonKonsta Holtta2018-06-27
| | | | | | | | | | | | | | | | To finish OS unification of the submit path, move the gk20a_submit_channel_gpfifo* functions to a file that's accessible also outside Linux code. Also change the prefix of the submit functions from gk20a_ to nvgpu_. Jira NVGPU-705 Change-Id: I8ca355d1eb69771fb016c7a21fc7f102ca7967d7 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1760421 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: posix: Fix ffs() and fls() impl in POSIXAlex Waterman2018-06-27
| | | | | | | | | | | | | | | | | The GCC builtins act slightly differently than the Linux versions of these functions. This patch adds the necessary glue to emulate the Linux versions identically. JIRA NVGPU-525 Change-Id: Idadbecdfd516c68f3d3eb20eca495dc1eaa02c5b Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741951 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* PMU: t19x: PMU ucode update.Deepak Goyal2018-06-27
| | | | | | | | | | | | | | | | | | | | | | | Remove Gr engine reset during ELPG entry. Engine reset is causing clock gating logic to get reset thus clock gating gets disabled during ELPG entry sequence. It leads to higher power numbers observed at light graphics. Removing GR reset during ELPG entry helped save power. Bug 2180198 Change-Id: I957951eb93f9d044f4d9a908f2b56a4903dfbfad Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1757695 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: fix fb flush issueseshendra Gadagottu2018-06-25
| | | | | | | | | | | | | | | | | | | | | membar.sys does synchronization with the whole system (GPU and CPU), membar.gl does synchronization within the GPU. In gv11b, fb flush is generating membar.gl instead of membar.sys, which is an issue. To fix this issue. following WAR is used: 1. Use bar1 engine id and bind it to a particular pdb, 2. Then instead of a fb_flush, issue a tlb invalidate of the bar1 pdb. Now allocation of vm for bar1 instance block and bar1 binding is done without check for bar1 support. Only bar1 register mapping is done based on bar1 support enabled. Bug 2112790 Change-Id: I76f43f1178a68f10823d48bc9da55d2bd686dd52 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1750257 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add nvgpu_dma_alloc_vid_at()Terje Bergstrom2018-06-22
| | | | | | | | | | | | | | Add a wrapper function nvgpu_dma_alloc_vid_at() for performing vidmem allocation at a specific address without needing to pass any flags. Change-Id: Ib7a21a4fd33120749cf7b79750c3a382ba08b470 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1753710 Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update __get_pte_size() to check IOMMU-abilityAlex Waterman2018-06-22
| | | | | | | | | | | | | | | | | | | | When generating the PTE size for a given mapping the code must consider whether the GPU is being IOMMU'ed. The presence and usage of an IOMMU implies the buffers will appear contiguous to the GPU. Without an IOMMU we cannot assume that and therefor must use small pages regardless of the size of the buffer to be mapped. Bug 2011640 Change-Id: I6c64cbcd8844a7ed855116754b795d949a3003af Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1697891 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add API to print process nameKonsta Holtta2018-06-19
| | | | | | | | | | | | | | Add an OS-abstracted API for printing the name of the current process into a log message and convert the single occurrence of current->comm in submit path power failure to use it. Jira NVGPU-705 Change-Id: I1a509dcc5aecc3c89ce4582733888081b3e38f1f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1749833 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move Linux files away from commonTerje Bergstrom2018-06-15
| | | | | | | | | | | | | | | Move all Linux source code files to drivers/gpu/nvgpu/os/linux from drivers/gpu/nvgpu/common/linux. This changes the meaning of common to be OS independent. JIRA NVGPU-598 JIRA NVGPU-601 Change-Id: Ib7f2a43d3688bb0d0b7dcc48469a6783fd988ce9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1747714 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: disable watchdog for in-kernel CDE channelsKonsta Holtta2018-06-15
| | | | | | | | | | | | | | | | | | The watchdog tracks wall clock time. If the GPU's runlist is heavily congested, other work can last long enough to trigger the watchdog for trusted kernel channels too. We don't expect the CDE work to ever get stuck, so disable wdt there. Bug 200311892 Change-Id: I58c7d23891bc73aaeea0ccfcead567b3c6c13a52 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1493814 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: update ecc sysfs node handlingNitin Kumbhar2018-06-15
| | | | | | | | | | | | | | | | | | | | | | | | | | Make ecc sysfs hash table per GPU by adding it as part of nvgpu_os_linux. Using a single hash table might give incorrect results as GPUs have same filenames and a filename is used as a key for a lookup. Add device_attribute as part of struct gk20a_ecc_stat. Using a single array of pointers of device attribute for an ecc_stat results in memory leak and incorrect stats if multiple GPUs are present on the system. This array of pointers will always hold info for GPU which created sysfs nodes last. Fix this by making device attribute array per ecc stat per GPU. Fix ecc stat removal to consider zero sub-units for a given number of hwunits. The multiplication with zero results in not removing any sysfs node at all. Bug 1987855 Change-Id: Ifcacc5623cede8decfe228c02d72786337cd0876 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move ecc sysfs funcs to a common fileNitin Kumbhar2018-06-15
| | | | | | | | | | | | | | | | To make ecc sysfs related code reusable, move it to a seprate file. This allows possible optimizations with localized changes. There is no change in the code. Bug 1987855 Change-Id: I69aefb649df628d0c8dad529de6dde07ab4e6009 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735988 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add remove_gr_sysfs gpu opNitin Kumbhar2018-06-15
| | | | | | | | | | | | | | | | | | | | | Add remove_gr_sys() op to gpu_ops to reverse steps done in create_gr_sysfs(). Make gv11b_tegra_remove() specific to gv11b instead to properly remove sysfs nodes. This also helps in having gv11b specific remove steps. Also, update platform remove function of dGPU i.e. nvgpu_pci_tegra_remove() to remove sysfs nodes. This adds parity with iGPU platform remove. Bug 1987855 Change-Id: Ibbaffac5c24346709347f86444a951461894354d Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735987 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add support for PCI device 0x1ebaDeepak Nibade2018-06-15
| | | | | | | | | | | | | | | | | Add support for PCI device with ID 0x1eba Add corresponding platform data Change-Id: I2e5fe25666d4c00a6d4d27f0124fa02639f7aebd Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1746579 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: Unified CSS VGPU HALAntony Clince Alex2018-06-15
| | | | | | | | | | | | | | | | | - defined platform agnostic wrapper for mempool mapping and unmapping. - used platform agnositc wrapper for device tree parsing. - modified css_gr_gk20a to include special handling incase of rm-server JIRA: VQRM:3699 Change-Id: I08fd26052edfa1edf45a67be57f7d27c38ad106a Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1733576 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: abstract dt functionsRichard Zhao2018-06-15
| | | | | | | | | | | | Added nvgpu_dt_read_u32_index() for now. Jira VFND-4870 Change-Id: I3e51c408dfba3864372c515ba5d2c77708a489c8 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683008 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Cosmetic changes to busTerje Bergstrom2018-06-14
| | | | | | | | | | | | | | | | | | A few review comments got lost in the review of moving bus code to common/bus. This takes care of renaming the header file protection define, deletes the unnecessary description of the file in header, and updates copyright years. Change-Id: Ib7dfe3d8fdf31ff3ea1fbf96fc41f9e454486dd1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741824 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10x PMU f/w version updateVaikundanathan S2018-06-14
| | | | | | | | | | | | | | -gp10x f/w version update for ucode https://git-master.nvidia.com/r/#/c/1748070/ Change-Id: Ie6f40fc931a24162497ef62778069814fd668c20 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1748071 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: warn if cde fails to find addr to patchKonsta Holtta2018-06-14
| | | | | | | | | | | | | | | | Print the surface address for which we fail to resolve an iova address when patcing cde parameters. This appears to happen extremely rarely for yet unknown reasons. Bug 2038362 Change-Id: I5ca300ea9b2f8c8867b7b43e37f51a50836129b7 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1748455 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: populate vsm mapping based on nonpes_aware_tpcseshendra Gadagottu2018-06-14
| | | | | | | | | | | | | | For gv1xx, kernel smid configuration programming is done based on nonpes aware tpc. For user space to be in sync with hw populate vsm mapping based on nonpes_aware_tpcs. Bug 200405202 Change-Id: Id89291ca64c2118915dc6f18f62e17f411d467b0 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1744304 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-24 02:04:37 -0400