| Commit message (Collapse) | Author | Age |
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Fixed build failure that occurred when disabling FECS ctxsw
tracing using CONFIG_GK20A_CTXSW_TRACE.
JIRA EVLR-2162
Change-Id: I751eba835c5f3f527571167e8b05fadb9687c64d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1617557
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Dennis Kou <dkou@nvidia.com>
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All channels should be wrapped in TSGs so that bare channel support
can be dropped. Bind all CE channels to TSGs.
Bug 1842197
Change-Id: Ia55748d5b53750d860f7764b532ef9eeb6f214b8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1616693
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nvgpu_get_nvhost_dev will not return error if host1x field within
gv11b device tree is not present. It will just set has_syncpoints
in gk20a struct to false. syncpt_unit_interface* should be called
only if g->has_syncpoints is set to true.
Change-Id: Id1eb94aba4cff1942ad519f528ebdb8291963971
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1615973
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All channels should be wrapped in TSGs so that bare channel support
can be dropped. Bind all CDE channels to TSGs.
Bug 1842197
Change-Id: I20b68c81b47e0d742e5922e7b85ac5cba75984b0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1616698
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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All channels need to now be wrapped in TSGs. Disallow use of bare
channels by preventing creation of GPFIFO for them.
Bug 1842197
Change-Id: Id0ebee4c590804b96c09f8951e35ba2680b596e7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612697
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vgpu doesn't care about pmu. pmu is managed by RM server.
It also fixed the dump caused by reading fuse register.
Jira EVLR-1934
Change-Id: I779964950783ccf699cd99473fb30e811c5c2ed6
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612774
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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Adding support for ISR handling of ECC parity errors for PMU unit and setting
the initial IRQDST mask to deliver ECC interrupts to host in the non-stall
PMU irq path
JIRA: GPUT19X-83
Change-Id: I8efae6777811893ecce79d0e32ba81b62c27b1ef
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1611625
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device_is_iommuable() is defined only in Tegra kernel. There is no
explicit config option to check for its existance, so skip building
that code when Tegra iGPU is not supported.
Change-Id: I50dc47070fa416181d458beabf5a2f2373931331
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612649
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debug_fifo.c uses vzalloc(), but frees the allocation with
nvgpu_vfree(). Change the vzalloc() into nvgpu_vzalloc() for
consistency.
Change-Id: I86facf81752def3dd10fd0cf4cd30e652099f8a5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612647
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gv11b needs tsg release callback to release CE method buffer.
Bug 2022929
Change-Id: I32e27a5fa49eb61b9c2fc72ea32034191a9be48e
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1611631
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Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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SZ_4G is not defined in mainline Linux. Use SZ_1G*4 instead.
Change-Id: I6d226d49da59e4e7b47ccef364b03b82c5758f57
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612648
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GR IDLE timeout is defined as Kconfig. Instead of that introduce a
new header file defaults.h which encapsulates any generic defaults
we use in nvgpu, and move the definition there.
Change-Id: I78ff1d2790d7ee3dff6df42bbd11cf683a85bf79
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612650
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Use nvgpu specific list APIs nvgpu_list_for_each_entry() instead of calling
Linux specific list APIs list_for_each_entry()
Jira NVGPU-444
Change-Id: I3c1fd495ed9e8bebab1f23b6769944373b46059b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612442
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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The current code does not properly calculate the indexes within the PDE
to access the proper entry, and it has a bug in assignement of the big
page entries. This change fixes the issue by:
(1) Passing a pointer to the level structure and dereferencing the
index offset to the next level.
(2) Changing the format of the address.
(3) Ensuring big pages are only selected if their address is set.
Bug 200364599
Change-Id: I46e32560ee341d8cfc08c077282dcb5549d2a140
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1610562
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Bhosale <dbhosale@nvidia.com>
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Define __nvgpu_mem_create_from_phys only in systems with nvhost
enabled. The calling code is also built only when nvhost is enabled.
phys_to_page() also exists only in arm64, so using it in non-arm64
platform causes a build failure.
Change-Id: Iee023b55bba863d46079796e1c49c19456c1d229
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1607581
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Per veid header mode is enabled for subcontext header.
Allocate only context header size for subcontext header.
Jira EVLR-2073
Change-Id: I2761dcac7e8e765acb6db22241e3a9214867f885
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1607627
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Increase the ctagline that is programmed in the page tables when the
buffer offset crosses the compression page boundaries. This fixes
compressible-kind fixed-address mapping with 4k pages when the GPU VA
is not aligned by the compression page size.
Bug 1995897
Bug 2011640
Bug 2011668
Change-Id: I1f1f9750635a20a916527c9d18fda7f8aa6b1b1f
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1608465
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Simulation does not model CPU caches, so remove extra CPU flushes.
The flushes are defined only in Tegra Linux kernel, so they cause
build errors on other kernels.
Change-Id: I5530a9ea8beac4b7c1ac30f32524afa418110daf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1607582
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Avoid using Tegra DVFS APIs when it is not built in. This is done by
protecting the code using Tegra DVFS with #ifdef.
Change-Id: Ia50b77aba8a085f436891e522514bb2b5b717c4d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1607583
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nvgpu_mem.c uses vmap(), which is defined in linux/vmalloc.h, but does not
include it. Add the missing #include.
Change-Id: I38a44083f08f91df50e372c7f1732e2ad27c6bb1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1607578
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ioctl.c defines file_operations structure for ctxsw tracing. The
definition is not protected by the build flag
CONFIG_GK20A_CTXSW_TRACE. Add the protection.
Change-Id: If82d6e2436d18d72b8eb43d490111c7d5ee0b41c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1607577
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We use SZ_* #defines in some parts of nvgpu, but we don't explicitly
include a header that defines it. Add include/nvgpu/sizes.h that in
Linux #includes linux/sizes.h.
Change-Id: I8f506d85c7eaa12e649f5874a87533e2f0fe9438
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Removed Linux dependent header
- Moved thermal alarm post from pmu_gk20a.c
to clk_arb.c
- Implemented nvgpu_clk_arb_send_thermal_alaram()
method to post
NVGPU_GPU_EVENT_ALARM_THERMAL_ABOVE_THRESHOLD
JIRA NVGPU-403
Change-Id: Ibf85c2f3a6e704fdcc0502745fab820f7ea428f4
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1608313
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Add an alignment check for compressible-kind fixed-address
mappings. If we're using page size smaller than the comptag line
coverage window, the GPU VA and the physical buffer offset must be
aligned in respect to that window.
Bug 1995897
Bug 2011640
Bug 2011668
Change-Id: If68043ee2828d54b9398d77553d10d35cc319236
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606439
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Add <nvgpu/bug.h> to MM files that use any of the BUG, BUG_ON,
WARN, WARN_ON, etc, macros but do not yet include <nvgpu/bug.h>.
JIRA NVGPU-401
Change-Id: I538219683d2a52b15abf147ff4bcf6375b6cb8a0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599960
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The files sim_gk20a.c and sim_gk20a.h under common/linux/ are renamed
to sim.c and sim.h as the suffix gk20a is not needed.
JIRA NVGPU-386
Change-Id: I79bbb8e66c4b0cf53f2b1f98a7bed5f682106a0c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606975
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For gv11b, configured gfx preemption wfi timeout in usec.
Set timeout unit as usec in gr_gv11b_init_preemption_state.
Used default timeout as 1msec and this timeout value can
be modified through sysfs node:
/sys/devices/gpu.0/gfxp_wfi_timeout_count
For gp10b:
gfxp_wfi_timeout_count is in syclk cycles
For gv11b:
gfxp_wfi_timeout_count is in usec
Bug 2003668
Change-Id: I68d52ce996a83df90b8b3a8164debb07e5cb370f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
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clk_arb was moved to be Linux specific, but its license was left as
MIT. Change the license.
Change-Id: I204bace9c4cc8147428cecacc3c673e6987d95ab
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606422
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This patch removes linux dependencies from sim_gk20a.h under
gk20a/sim_gk20a.h. The following changes are made in this patch.
1) Created a linux based structure sim_gk20a_linux that contains a
common sim_gk20a struct inside it. The common struct sim_gk20a doesn't
contain any linux specific structs.
2) The common struct sim_gk20a contains an added function pointer which
is used to invoke gk20a_sim_esc_readl() method.
3) sim_gk20a.c is moved to nvgpu/common/linux along with a new header
sim_gk20a.h that contains the definition of struct sim_gk20a_linux.
4) struct gk20a now contains a pointer of sim_gk20a instead of the
entire object. The memory for this struct is allocated and initialized during
gk20a_init_support() and freed during invocation of
gk20_remove_support().
5) We first obtain the pointer for struct sim_gk20a_linux from the
pointer of sim_gk20a using the container_of method in order to work on
the struct.
JIRA NVGPU-386
Change-Id: Ic82b8702642377f82694577a53c3ca0b9c1bb2ab
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1603073
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With recent rework in nvgpu most of the <uapi/linux/nvgpu.h> includes
are not needed so remove them
Remove use of NVGPU_DBG_GPU_REG_OP_* in gk20a/gr_gk20a.c and use common
definition instead
Remove use of NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE in
gp10b/fifo_gp10b.c by defining new common flag
NVGPU_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE and then parsing it in API
nvgpu_gpfifo_user_flags_to_common_flags()
Jira NVGPU-363
Change-Id: I8e653275ea3f443f24be7284d54f2115636aba3f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606108
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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We use dma_buf pointer cyclestate_buffer_handler in common code
But since this is linux specific, we need to move this out of common code and
into linux specific code
Move dma_buf pointer cyclestate_buffer_handler from common channel code to
struct nvgpu_channel_linux
Fix all pointer accesses to this handle
Move gk20a_channel_free_cycle_stats_buffer() to ioctl_channel.c since it is
mostly linux specific
And since gk20a_channel_free_cycle_stats_buffer() needs to be called while
closing the channel, call it from nvgpu_channel_close_linux()
Jira NVGPU-397
Jira NVGPU-415
Change-Id: Ifb429e49b8f7a1c9e2bc757f3efdd50b28ceca1f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1603909
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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We right now store dmabuf fd and dma_buf pointer for gk20a_cs_snapshot_client
But since dma_buf and all related APIs are linux specific, we need to remove
them from common code and move them to linux specific code
Add new linux specific structure gk20a_cs_snapshot_client_linux which includes
struct gk20a_cs_snapshot_client and linux specific dma_buf pointer
In gk20a_attach_cycle_stats_snapshot(), we first handle all dma_buf related
operations and then call gr_gk20a_css_attach()
Move gk20a_channel_free_cycle_stats_snapshot() to ioctl_channel.c
In gk20a_channel_free_cycle_stats_snapshot(), we call gr_gk20a_css_detach()
and then free up dma_buf in linux specific code
We also need to call gk20a_channel_free_cycle_stats_snapshot() while closing
the channel, so call it from linux specific nvgpu_channel_close_linux()
Jira NVGPU-397
Jira NVGPU-415
Change-Id: Ida27240541f6adf31f28d7d7ee4f51651c6d3de2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1603908
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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We initialize gr->max_comptag_mem in common code and with a global variable
declared in <linux/mm.h>
Move this linux specific dependency to linux specific files i.e.
initialize gr->max_comptag_mem during linux specific probe functions
Jira NVGPU-414
Change-Id: I9415938bf1288b24950ba7ecc71abee3162dae64
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606195
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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All the linux specific error_notifier codes are defined in linux specific
header file <uapi/linux/nvgpu.h> and used in all the common driver
But since they are defined in linux specific file, we need to move all the
uses of those error_notifiers in linux specific code only
Hence define new error_notifiers in include/nvgpu/error_notifier.h and
use them in the common code
Add new API nvgpu_error_notifier_to_channel_notifier() to convert common
error_notifier of the form NVGPU_ERR_NOTIFIER_* to linux specific error
notifier of the form NVGPU_CHANNEL_*
Any future additions to error notifiers requires update to both the form
of error notifiers
Move all error notifier related metadata from channel_gk20a (common code)
to linux specific structure nvgpu_channel_linux
Update all accesses to this data from new structure instead of channel_gk20a
Move and rename below APIs to linux specific file and declare them
in error_notifier.h
nvgpu_set_error_notifier_locked()
nvgpu_set_error_notifier()
nvgpu_is_error_notifier_set()
Add below new API and use it in fifo_vgpu.c
nvgpu_set_error_notifier_if_empty()
Include <nvgpu/error_notifier.h> wherever new error_notifier codes are used
NVGPU-426
Change-Id: Iaa5bfc150e6e9ec17d797d445c2d6407afe9f4bd
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593361
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API to initialize os-specific features nvgpu_finalize_poweron_linux() does not
get called for VGPU
Add it to vgpu_pm_finalize_poweron()
Jira NVGPU-395
Change-Id: I5488853aad36606c18b64a4fbe4076909a6b23f9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1603913
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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For nvhost_sync_create_fence, num_pts corresponds to the number of
syncpoints in the array given to it, and the wrapper
nvgpu_nvhost_sync_create_fence only supports one syncpoint at a time.
Use 1 explicitly and make it impossible for the caller of this wrapper
to use something else by mistake.
Change-Id: I2497c1dd4fed0906e3bb07e8f5ddd3a9346cb381
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1604339
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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gv11b/platform_gv11b_tegra.c is mostly linux specific so move it to linux
specific directory
Change-Id: I3e10bafcf672967e35a7955038cd9285b8697a57
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1604283
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This patch removes the dependency on the header file "uapi/linux/nvgpu.h"
for regops_gk20a.c. The original structure and definitions in the
uapi/linux/nvgpu.h is maintained for userspace libnvrm_gpu.h. The
following changes are made in this patch.
1) Defined common versions of the NVGPU_DBG_GPU_REG_OP* definitions inside
regops_gk20a.h.
2) Defined common version of struct nvgpu_dbg_gpu_reg_op inside
regops_gk20a.h naming it struct nvgpu_dbg_reg_op.
3) Constructed APIs to convert the NVGPU_DBG_GPU_REG_OP* definitions from
linux versions to common and vice versa.
4) Constructed APIs to convert from struct nvgpu_dbg_gpu_reg_op to
struct nvgpu_dbg_reg_op and vice versa.
5) The ioctl handler nvgpu_ioctl_channel_reg_ops first copies from
userspace into a local storage based on struct nvgpu_dbg_gpu_reg_op which
is copied into the struct nvgpu_dbg_reg_op using the APIs above and
after executing the regops handler passes the data back into userspace
by copying back data from struct nvgpu_dbg_reg_op to struct
nvgpu_dbg_gpu_reg_opi.
JIRA NVGPU-417
Change-Id: I23bad48d2967a629a6308c7484f3741a89db6537
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596972
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Move the implementation for channel job update callbacks that is based
on Linux specific work_struct usage to Linux-specific code.
This requires a bit of extra work for allocating OS-specific priv data
for channels which is also done in this patch. The priv data will be
used more when more OS-specific features are moved.
Jira NVGPU-259
Change-Id: I24bc0148a827f375b56a1c96044685affc2d1e8c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1589321
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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If the associated buffer is not compressed, it would be invalid to call
the cde swizzler shader with zero lines. The fences in
PREPARE_COMPRESSIBLE_READ still need to be managed, so just do a dummy
submit with zero entries when lines is zero for the buffer.
Bug 1856088
Change-Id: Ia68c2ffff21e5e8077d5c550b0ca44090f88bf80
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1590055
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-New fuse ops is added to set NVGPU_SEC_PRIVSECURITY
and NVGPU_SEC_SECUREGPCCS bits in g->enabled_flags
during hal initialization
-For igpu non simulation platforms, fuses are read
to decide if gpu should be allowed to boot or not.
--Do not boot gpu if priv_sec_en is set but wpr_enabled
is not set to 1 or vpr_auto_fetch_disable is not set to 0
--With priv_sec_en set, all falcons have to boot
in LS mode and this needs wpr_enabled set to 1
AND vpr_auto_fetch_disable set to 0. In this case
gmmu tries to pull wpr and vpr settings from tegra mc
Bug 2018223
Change-Id: Iceaa1b0b3214e9a3d6cef5d77a82e034302f748b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595454
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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TEGRA_ACR config is supposed to be enabled maxwell
onwards. Since gk20a support is no longer supported,
delete code that is not under TEGRA_ACR config
Change-Id: Id52485680bca1ceaadcb94f9603c0898c2002e02
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595437
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-Added nvgpu_flcn_mem_scrub_wait() to
falcon interface layer to poll imem/dmem
scrubbing status complete check for 1msec
with status check interval of 10usec.
-Called nvgpu_flcn_mem_scrub_wait() in
falcon reset interface to check scrubbing
status upon falcon/engine reset.
-Replaced mem scrubbing wait check code in
pmu_enable_hw() by calling
nvgpu_flcn_mem_scrub_wait()
Bug 200346134
Change-Id: Iac68e24dea466f6dd5facc371947269db64d238d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1598644
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- Created nvgpu_kill_task_pg_init() method to set
pmu state to PMU_STATE_EXIT & make thread stop,
and poll to confirm thread stopped.
- Check for PMU/SEC2 ACR secure boot completion
status & initiate pg init thread kill if ACR boot
exits with error, which fails to validate &
boot LS-PMU.
- Set pmu state to PMU_STATE_OFF after thread kill
during ACR boot failure.
Issue: pg init task blocks if PMU boot fails &
cause kernel to show message "task nvgpu_pg_init_g:2120
blocked for more than 120 seconds"
Bug 200346134
Change-Id: I5270426080dcd628ccca4df798005294c19767a0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1582593
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Remove separation of t18x specific code and fields and the associated
ifdefs. We can build T18x code in always.
Change-Id: I4e8eae9c30335632a2da48b418c6138193831b4f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595431
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Add a translation layer to convert from the NVGPU_AS_* flags to
to new set of NVGPU_VM_MAP_* and NVGPU_VM_AREA_ALLOC_* flags.
This allows the common MM code to not depend on the UAPI header
defined for Linux.
In addition to this change a couple of other small changes were
made:
1. Deprecate, print a warning, and ignore usage of the
NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS flag.
2. Move the t19x IO coherence flag from the t19x UAPI header
to the regular UAPI header.
JIRA NVGPU-293
Change-Id: I146402b0e8617294374e63e78f8826c57cd3b291
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599802
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Most of VGPU code is linux specific but lies in common code
So until VGPU code is properly abstracted and made os-independent,
move all of VGPU code to linux specific directory
Handle corresponding Makefile changes
Update all #includes to reflect new paths
Add GPL license to newly added linux files
Jira NVGPU-387
Change-Id: Ic133e4c80e570bcc273f0dacf45283fefd678923
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599472
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Commit 81868a187fa3b217368206f17b19309846e8e7fb updated barrier
usage to use the nvgpu wrappers and in doing so downgraded many
plain barriers {mb(), wmb(), rmb()} to the SMP versions of these
barriers.
The SMP version of the barriers in question are only issued
when running on an SMP machine. In most of the cases mentioned
above this is fine since the barriers are present to faciliate
proper ordering across CPUs. A single CPU is always coherent
with itself, so on a non-SMP case we don't need those barriers.
However, there are a few places where the barriers in use (GMMU
page table programming, IO accessors, userd) where the barrier
usage is for communicating and establishing ordering for the
GPU. We need these barriers for both SMP machines and non-SMP
machines. Therefor we must use the plain barrier versions.
Change-Id: I376129840b7dc64af8f3f23f88057e4e81360f89
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599744
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nvgpu_pde_phys_addr() is only used in gmmu.c and as such can be
marked static.
JIRA NVGPU-402
Change-Id: I7adba6f54ebd4e06d176f23b9a959c04a8770338
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599040
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Always allocate explicitly zeroed DMA memory and remove the
unnecessary memset() from the alloc path for memory with a
kernel mapping.
JIRA NVGPU-418
Change-Id: I5a3df6e6969e2586df41b72325d1bff1e40206e6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1598933
Reviewed-by: Automatic_Commit_Validation_User
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