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* gpu: nvgpu: vgpu: move t19x specific code to general codeRichard Zhao2018-01-12
| | | | | | | | | | | | | | - remove vgpu_t19x.h and tegra_vgpu_t19x.h - merge t19x specific ivc commands to the big enum - move TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT to constants Jira EVLR-2293 Change-Id: I34344bffa03bb69e1282b1f19382e3199f9ba105 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1636128 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Combine gk20a and gp10b free_gr_ctxTerje Bergstrom2018-01-12
| | | | | | | | | | | | | | gp10b version of free_gr_ctx was created to keep gp10b source code changes out from the mainline. gp10b was merged back to mainline a while ago, so this separation is no longer needed. Merge the two variants. Change-Id: I954b3b677e98e4248f95641ea22e0def4e583c66 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1635127 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: Delete gm20b supportTerje Bergstrom2018-01-12
| | | | | | | | | | | | Delete gm20b vgpu support. It has not been supported for a long time and keeping it up-to-date is extra work. Change-Id: I3c06d29a79cb83d53a25d2242247b4eeabeab310 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1635126 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: get virtual SMs mappingThomas Fleury2018-01-10
| | | | | | | | | | | | | | | On gv11b we can have multiple SMs per TPC. Add sm_per_tpc in vgpu constants to properly dimension the virtual SM to TPC/GPC mapping in virtualization case. Use TEGRA_VGPU_CMD_GET_SMS_MAPPING to query current mapping. Bug 2039676 Change-Id: I817be18f9a28cfb9bd8af207d7d6341a2ec3994b Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631203 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Free enabled flags on driver unloadAlex Waterman2018-01-10
| | | | | | | | | | | | Make sure the enabled flags are freed before the driver unloads. Bug 200369180 Change-Id: Ibac9ee61ca99bdfda03d76e393c7cd6cb6cc299a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1632752 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b PMU ucode F/W version updateMahantesh Kumbar2018-01-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - F/W version update for gv11b PMU ucode of CL https://git-master.nvidia.com/r/#/c/1628288/ Current CL has PMU F/W version for ucode bin of P4 CL# 23378914 P4 CL# & its changes. - 23378914 - Don't post "PMU_PG_EVENT_IDLE_SNAP" event in method pgConvertPgInterrupts_GP10X() - 23355380 - Remove debug code included by mistake in P4 change list #23354716 - 23354716 - Made change to point CONVERT_PG_INTERRUPTS of gv11b to _GP10x - pgConvertPgInterrupts_GP10X() - Removed PMU halt upon FIFO preempt timeout in _fifoPreemptRunlist_GP10X() Bug 2039371 Bug 200377983 Change-Id: I8ce7cb926203b329308944235a06933768ed2a5f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1628380 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allocate from coherent poolDavid Nieto2018-01-08
| | | | | | | | | | | | | | | | | | | | Maps memory coherently on devices that are connected to a coherent bus. (1) Add code to be able to get the platform device node. (2) Create a new flag to mark if the device is connected to a coherent bus (3) Map memory coherently on coherent devices. bug 2040331 Change-Id: Ide83a9261acdbbc6e9fef4fc5f38d6f9d0e5ab5b Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1633985 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: init ch_wdt_timeout_msSeema Khowala2018-01-08
| | | | | | | | | | | | | This is needed for watchdog to work. Change-Id: Ic1e197e5f6701fafd8b614cd43bb610bdc8518ae Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1632230 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* DNI: gpu: nvgpu: Increase GV100 ctxsw timeoutsDavid Nieto2018-01-05
| | | | | | | | | | | | | | | During bringup and before nvlink is up GV100 on the DDPX platform operates with a very, very slow sysmem link. In order to get sysmem test to pass it is neccesary to significantly increase most timeouts by an order the magnitude. Bug 2040544 Change-Id: I26858afde4ae80c70f86b47cfff674b6b00b5bf8 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627417 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: no hv support for write_sm_error_statePeter Daifuku2018-01-04
| | | | | | | | | | | | | | | | | There is no current need for a virtualized version of nvgpu_dbg_gpu_ioctl_write_single_sm_error_state, so return -ENOSYS when virtual. Bug 200331110 Change-Id: I223a6298eb4c891859f1c8252049f9a83d84ccb5 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631270 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Do not disable ELPG when committing buffersTerje Bergstrom2018-01-04
| | | | | | | | | | | | | Committing buffer addresses only writes to the memory. There's no need to disable ELPG for the duration, so drop the ELPG protection. Change-Id: I8d8d08506387197e4737e0311df4a20085496056 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631149 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix erroneous gk20a_put() callDeepak Nibade2018-01-04
| | | | | | | | | | | | | | | | | | | | | | | With a recent rework we moved gk20a_get() call to nvgpu_ioctl_tsg_open(), but corresponding gk20a_put() call remained in gk20a_tsg_release() So if a TSG is opened and released from within kernel with APIs gk20a_tsg_open()/gk20a_tsg_release() we mistakenly drop extra refcount through gk20a_put() Fix this by moving gk20a_put() call to nvgpu_ioctl_tsg_release() which balances gk20a_get() call in nvgpu_ioctl_tsg_open() Bug 200374011 Change-Id: Id0cec0426e6231309dc530ab5c934dacaba9f8da Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1630969 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: return error if TSG allocation failsDeepak Nibade2018-01-04
| | | | | | | | | | | | | | | | | | In gk20a_cde_load(), if TSG allocation fails we bail out the function without setting the error code and caller of this functions assumes CDE load is successful Fix this by setting explicit error code if TSG allocation fails Bug 200374011 Change-Id: I6e7bcb325fb0062605fa2f696da4abdeb34e241a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627117 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix TSG leak from CDE codeDeepak Nibade2018-01-04
| | | | | | | | | | | | | | | | | | | | | | | | In gk20a_cde_remove_ctx(), we unbind the channel from TSG and close the channel. But we do not drop the TSG refcount leaking the TSG reference After allocating sufficient contexts, we see TSG creation fails as below nvgpu: 17000000.gp10b: gk20a_cde_load:1286 [ERR] cde: could not create TSG Fix this by explicitly dropping TSG refcount Also, do not explicitly unbind the channel from TSG gk20a_channel_close() will internally unbind the channel from TSG Bug 200374011 Change-Id: If6d75b20d5e03d710c0597d7a320d1157206a2a5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627116 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set low_hole to 64K for bar1 vmSourab Gupta2018-01-04
| | | | | | | | | | | | | The patch sets low_hole value to 64K for bar1 vm to align to potential 64KB native page size. JIRA NVGPU-454 Change-Id: I994dfd6824d3a2e8a09433798bb101af88ecb5ca Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1617173 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add guest_managed field in vm_gk20aSourab Gupta2018-01-04
| | | | | | | | | | | | | | | | | | | Add a field in vm_gk20a to identify guest managed VM, with the corresponding checks to ensure that there's no kernel section for guest managed VMs. Also make the __nvgpu_vm_init function available globally, so that the vm can be allocated elsewhere, requisite fields set, and passed to the function to initialize the vm. Change-Id: Iad841d1b8ff9c894fe9d350dc43d74247e9c5512 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1617171 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Enable secure alloc for GV11bSami Kiminki2018-01-03
| | | | | | | | | | | | | | | Kernel needs to be able to allocate VPR memory for buffers for protected contexts. So, let's call gk20a_tegra_init_secure_alloc and enable VPR for GV11B. Bug 2039456 Bug 2040513 Change-Id: Ie27d8f04b1a414c36b42516ce3147d38d8472d54 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1628566 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove bare channel schedulingTerje Bergstrom2018-01-02
| | | | | | | | | | | | | | | | Remove scheduling IOCTL implementations for bare channels. Also removes code that constructs bare channels in runlist. Bug 1842197 Change-Id: I6e833b38e24a2f2c45c7993edf939d365eaf41f0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627326 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove TSG required flagTerje Bergstrom2018-01-02
| | | | | | | | | | | | | | | | | | Remove nvgpu internal flag indicating that TSGs are required. We now require TSGs always. This also fixes a regression where CE channels were back to using bare channels on gp106. Bug 1842197 Change-Id: Id359e5a455fb324278636bb8994b583936490ffd Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1628481 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add io coherency supportAparna Das2017-12-30
| | | | | | | | | | | | | Modify command message parameter to support io coherency. Jira EVLR-2025 Change-Id: I38b21c72d85f559555c4d97dab73d0f715ecc655 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1614388 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement abstraction for finding TIDTerje Bergstrom2017-12-28
| | | | | | | | | | | | | Implement abstraction for finding the thread ID of thread currently being run. This is tracked for context switch tracing. In Linux kernel this is implemented by returning PID. Change-Id: Id46a318894f9a2ff3c85d2c8ef0b02c52783f122 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627239 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add support for GV100 SKU 250David Nieto2017-12-28
| | | | | | | | | | | | Bug 2040925 Change-Id: Ied06b199fd87411847b9987496c56276f8ebf89c Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1623709 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Report LTC errors per sliceDavid Nieto2017-12-28
| | | | | | | | | | | | | | | | | | | | | Add support to report ltc ecc errors per slice (1) use new logic to detect subunits (2) store size of array and check before comparison to prevent out of bounds derefencing (3) use new hashing to prevent collisions or entries with permuted names bug 2037425 Change-Id: I63b9f0df43b9dceddc1bae17924c4723072f569e Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1620854 GVS: Gerrit_Virtual_Submit Reviewed-by: Chris Dragan <kdragan@nvidia.com> Tested-by: Chris Dragan <kdragan@nvidia.com> Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove support for channel eventsTerje Bergstrom2017-12-28
| | | | | | | | | | | | | | Remove support for events for bare channels. All users have already moved to TSGs and TSG events. Bug 1842197 Change-Id: Ib3ff68134ad9515ee761d0f0e19a3150a0b744ab Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1618906 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove support for bare channelsTerje Bergstrom2017-12-28
| | | | | | | | | | | | | | | Remove remaining support for bare channels. All users of bare channels have already moved to TSGs. Bug 1842197 Change-Id: I1ff12677253b160dac9bebe6925ad0839ea07cfc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1618905 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix crash on read fail of mc_boot_0_rSupriya2017-12-28
| | | | | | | | | | | | | | | | | | | | | This CL handles - erroneous use of boot_0 function pointer before being assigned in __nvgpu_check_gpu_state - And proper handling of error returned from gk20a_readl in gk20a_mc_boot_0 With these fixes crash is not seen in case mc_boot_0 read returns 0 in gk20a_mc_boot_0 - And also this handles the recursion caused by mc.boot_0() calling nvgpu_readl and nvgpu_readl in turn calling mc.boot_0 in case of read failure Bug 2010966 Change-Id: Ia087811c67d88948b7fc5fff35e0fabc6ea91989 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616274 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement abstraction for finding TGIDTerje Bergstrom2017-12-27
| | | | | | | | | | | | | | | Implement abstraction for finding the process ID of thread currently being run. This is tracked for context switch tracing. In Linux kernel this is implemented by returning TGID. Change-Id: Ia6bcbd92c8cc25467694a35476e5d5f717194105 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1615985 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Update PMU ucode version.dgoyal@nvidia.com2017-12-27
| | | | | | | | | | | | | | | | | | - Enabled ECC interrupt to host. - Fix to ignore IDLE_SNAP during ELPG_ENTRY. - Production signatures. Change-Id: Ie9e549a123b3fbdcde69fa1d4d2ea3ac20e3fa64 Signed-off-by: y <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1620059 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: remove cde supportSeema Khowala2017-12-26
| | | | | | | | | | | Change-Id: I04df795b20413a2d07a252d77b3eba853890fcae Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1624087 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: host1x probed only if syncpoints supportedSeema Khowala2017-12-26
| | | | | | | | | | | Change-Id: I645f272f8fc3fffda95a82716558c081e323aed0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1624097 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix non-IOMMU mappingsDeepak Nibade2017-12-21
| | | | | | | | | | | | | | | | | | | | | | | | | In __nvgpu_gmmu_do_update_page_table(), and in case of non-IOMMU mappings, we call nvgpu_sgt_get_phys() to get physical address But this API ignores mapping attributes including l3_alloc attribute specified by user space, and this breaks L3 cache allocations Fix this by using g->ops.mm.gpu_phys_addr() which also considers the mapping attributes and returns appropriate physical address Jira GPUT19X-10 Bug 200279508 Change-Id: Ibc0d29f7cb576a9d6893a97b1912d9ff4bc78e02 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1621245 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: allow disabling of ctxsw tracingThomas Fleury2017-12-14
| | | | | | | | | | | | | | | | | | | Fixed build failure that occurred when disabling FECS ctxsw tracing using CONFIG_GK20A_CTXSW_TRACE. JIRA EVLR-2162 Change-Id: I751eba835c5f3f527571167e8b05fadb9687c64d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1617557 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Aparna Das <aparnad@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Dennis Kou <dkou@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Require TSGs for CE alwaysTerje Bergstrom2017-12-14
| | | | | | | | | | | All channels should be wrapped in TSGs so that bare channel support can be dropped. Bind all CE channels to TSGs. Bug 1842197 Change-Id: Ia55748d5b53750d860f7764b532ef9eeb6f214b8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616693
* gpu: nvgpu: gv11b: get syncpt aperture only if host1x is presentSeema Khowala2017-12-14
| | | | | | | | | | | | | nvgpu_get_nvhost_dev will not return error if host1x field within gv11b device tree is not present. It will just set has_syncpoints in gk20a struct to false. syncpt_unit_interface* should be called only if g->has_syncpoints is set to true. Change-Id: Id1eb94aba4cff1942ad519f528ebdb8291963971 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1615973 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use TSG for CDE channelsTerje Bergstrom2017-12-13
| | | | | | | | | | | | | | All channels should be wrapped in TSGs so that bare channel support can be dropped. Bind all CDE channels to TSGs. Bug 1842197 Change-Id: I20b68c81b47e0d742e5922e7b85ac5cba75984b0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616698 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Disallow use of bare channelsTerje Bergstrom2017-12-12
| | | | | | | | | | | | | All channels need to now be wrapped in TSGs. Disallow use of bare channels by preventing creation of GPFIFO for them. Bug 1842197 Change-Id: Id0ebee4c590804b96c09f8951e35ba2680b596e7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612697 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: remove PMU setup in gv11b halRichard Zhao2017-12-11
| | | | | | | | | | | | | | | | | vgpu doesn't care about pmu. pmu is managed by RM server. It also fixed the dump caused by reading fuse register. Jira EVLR-1934 Change-Id: I779964950783ccf699cd99473fb30e811c5c2ed6 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612774 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: PMU parity HWW ECC supportDavid Nieto2017-12-11
| | | | | | | | | | | | | | | Adding support for ISR handling of ECC parity errors for PMU unit and setting the initial IRQDST mask to deliver ECC interrupts to host in the non-stall PMU irq path JIRA: GPUT19X-83 Change-Id: I8efae6777811893ecce79d0e32ba81b62c27b1ef Signed-off-by: David Nieto <dmartineznie@nvidia.com> Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1611625 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use device_is_iommuable() only for iGPUTerje Bergstrom2017-12-11
| | | | | | | | | | | | | | device_is_iommuable() is defined only in Tegra kernel. There is no explicit config option to check for its existance, so skip building that code when Tegra iGPU is not supported. Change-Id: I50dc47070fa416181d458beabf5a2f2373931331 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612649 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use nvgpu_vzalloc() instead of vzalloc()Terje Bergstrom2017-12-11
| | | | | | | | | | | | | | debug_fifo.c uses vzalloc(), but frees the allocation with nvgpu_vfree(). Change the vzalloc() into nvgpu_vzalloc() for consistency. Change-Id: I86facf81752def3dd10fd0cf4cd30e652099f8a5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612647 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add tsg release commandRichard Zhao2017-12-10
| | | | | | | | | | | | | | | | gv11b needs tsg release callback to release CE method buffer. Bug 2022929 Change-Id: I32e27a5fa49eb61b9c2fc72ea32034191a9be48e Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1611631 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Aparna Das <aparnad@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use only standard size definesTerje Bergstrom2017-12-09
| | | | | | | | | | | | | SZ_4G is not defined in mainline Linux. Use SZ_1G*4 instead. Change-Id: I6d226d49da59e4e7b47ccef364b03b82c5758f57 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612648 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvpgu: Move GR IDLE timeout definition to headerTerje Bergstrom2017-12-08
| | | | | | | | | | | | | GR IDLE timeout is defined as Kconfig. Instead of that introduce a new header file defaults.h which encapsulates any generic defaults we use in nvgpu, and move the definition there. Change-Id: I78ff1d2790d7ee3dff6df42bbd11cf683a85bf79 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612650 GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu list APIs instead of linux APIsDeepak Nibade2017-12-08
| | | | | | | | | | | | | | | | | Use nvgpu specific list APIs nvgpu_list_for_each_entry() instead of calling Linux specific list APIs list_for_each_entry() Jira NVGPU-444 Change-Id: I3c1fd495ed9e8bebab1f23b6769944373b46059b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612442 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix indexing in locate pte functionDavid Nieto2017-12-05
| | | | | | | | | | | | | | | | | | | The current code does not properly calculate the indexes within the PDE to access the proper entry, and it has a bug in assignement of the big page entries. This change fixes the issue by: (1) Passing a pointer to the level structure and dereferencing the index offset to the next level. (2) Changing the format of the address. (3) Ensuring big pages are only selected if their address is set. Bug 200364599 Change-Id: I46e32560ee341d8cfc08c077282dcb5549d2a140 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1610562 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Bhosale <dbhosale@nvidia.com>
* gpu: nvgpu: Define create_from_phys when nvhost enabledTerje Bergstrom2017-12-01
| | | | | | | | | | | | | | Define __nvgpu_mem_create_from_phys only in systems with nvhost enabled. The calling code is also built only when nvhost is enabled. phys_to_page() also exists only in arm64, so using it in non-arm64 platform causes a build failure. Change-Id: Iee023b55bba863d46079796e1c49c19456c1d229 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1607581 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: modify subcontext header sizeAparna Das2017-12-01
| | | | | | | | | | | | | | | | | Per veid header mode is enabled for subcontext header. Allocate only context header size for subcontext header. Jira EVLR-2073 Change-Id: I2761dcac7e8e765acb6db22241e3a9214867f885 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1607627 Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Increase programmed ctagline at compr page boundariesSami Kiminki2017-12-01
| | | | | | | | | | | | | | | | | Increase the ctagline that is programmed in the page tables when the buffer offset crosses the compression page boundaries. This fixes compressible-kind fixed-address mapping with 4k pages when the GPU VA is not aligned by the compression page size. Bug 1995897 Bug 2011640 Bug 2011668 Change-Id: I1f1f9750635a20a916527c9d18fda7f8aa6b1b1f Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1608465 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove extra CPU flushes in sim_gk20a.cTerje Bergstrom2017-12-01
| | | | | | | | | | | | | | Simulation does not model CPU caches, so remove extra CPU flushes. The flushes are defined only in Tegra Linux kernel, so they cause build errors on other kernels. Change-Id: I5530a9ea8beac4b7c1ac30f32524afa418110daf Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1607582 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix build with Tegra DVFS disabledTerje Bergstrom2017-12-01
| | | | | | | | | | | | | | Avoid using Tegra DVFS APIs when it is not built in. This is done by protecting the code using Tegra DVFS with #ifdef. Change-Id: Ia50b77aba8a085f436891e522514bb2b5b717c4d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1607583 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-24 08:58:18 -0400