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* gpu: nvgpu: created os-agnostic sim header.Antony Clince Alex2018-05-09
| | | | | | | | | | | | | | added a os-agnostic sim.h header which could be included in by any platform, moved out os specific headers to nvgpu/linux. JIRA VQRM-2368 Change-Id: I3861bfa75a6b8d2d909bc7223467fd68c208275b Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702816 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: os-agnostic segregation of sim/sim_pciAntony Clince Alex2018-05-09
| | | | | | | | | | | | | | | | | | segregated os-agnostic function from linux/sim.c and linux/sim_pci.c to sim.c and sim_pci.c, while retaining os-specific functions. renamed all gk20a_* api's to nvgpu_*. renamed hw_sim_gk20a.h to nvgpu/hw_sim.h moved hw_sim_pci.h to nvgpu/hw_sim_pci.h JIRA VQRM-2368 Change-Id: I040a6b12b19111a0b99280245808ea2b0f344cdd Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702425 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: refactored struct sim_gk20aAntony Clince Alex2018-05-09
| | | | | | | | | | | | | | | | | | moved sim buffer(send, recv and msg) from os-specific structure to OS agnostic structure. JIRA VQRM-2368 Change-Id: I10ff23fe24d86f2bd372f1bae0369cc45aadfb80 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702178 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: refectored sim_readl/sim_writelAntony Clince Alex2018-05-09
| | | | | | | | | | | | | | | | | | | | | refactored sim_readl and sim_writel to use os-agnostic structures. converted all sim buffers to the type nvgpu_mem and replaced all alloc_page and free_page calls with corresponding nvgpu_dma_alloc/nvgpu_dma_free calls. JIRA VQRM-2368 Change-Id: Ia9d29119d31f239ed16be932cfd16c334002c727 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702050 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink endpoint ops to common codeThomas Fleury2018-05-09
| | | | | | | | | | | | | Move nvlink endpoint operations to common code. These operations are invoked when handling nvlink core driver requests. Jira VQRM-3523 Change-Id: I93024bf88a8caa3765b33c1264dde452c1a85ee3 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1698686 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add LDIV slowdown factor in INIT cmd.Deepak Goyal2018-05-09
| | | | | | | | | | | | | | | | PMU ucode is updated to include LDIV slowdown factor in gr_init_param command. - Defined a new version gr_init_param_v2. - Updated the PMU FW version code. - Set the LDIV slowdown factor to 0x1e by default. - Added sysfs entry to program ldiv_slowdown factor at runtime. Bug 200391931 Change-Id: Ic66049588c3b20e934faff3f29283f66c30303e4 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1674208 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove the setting of nice values in gk20a_poweronDebarshi Dutta2018-05-08
| | | | | | | | | | | | | | | set_user_nice is no longer needed to improve the efficiency of gk20a_finalize_poweron and can be removed as suggested by Terje. Change-Id: I303bbee266b4624bb775ea793f843dbfc8f88c5d Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1692609 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: enable syncpt shim for nvlinkThomas Fleury2018-05-07
| | | | | | | | | | | | | | Get host1x node reference from c1_rp device tree node, and enable syncpoints shim in case of nvlink. JIRA EVLR-2441 JIRA EVLR-2585 Change-Id: Idbf1edf656557f2ed2d3bd27393c2f4d5d1ad75a Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1663360 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to handle nonstall interruptsDeepak Nibade2018-05-07
| | | | | | | | | | | | | | | | | | | | | Add new HAL gops.mc.isr_nonstall() to handle nonstall interrupts We already handle nonstall interrupts in nvgpu_intr_nonstall() But this API is completely in linux specific code Separate out os-independent code to handle nonstall interrupts in new API mc_gk20a_isr_nonstall() and set it to HAL gops.mc.isr_nonstall() for all existing chips Call this HAL from nvgpu_intr_nonstall() Jira NVGPUT-8 Change-Id: Iec6a56db03158a72a256f7eee8989a0a8a42ae2f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1706589 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add worker for clk arb work handlingSourab Gupta2018-05-07
| | | | | | | | | | | | | | | | | | | | | | | | Implement a worker thread to replace the workqueue based handling for clk arbiter update callbacks. The work items scheduled with the thread are of two types, update_vf_table and arb_update. Previously, there were two workqueues for handling these two work struct's separately. Now the single worker thread would process these two events. If a work item of a particular type is scheduled to be run on the worker, another instance of same type won't be scheduled, which mirrors the linux workqueue behavior. This also removes dependency on linux workqueues/work struct and makes code portable to be used by QNX also. Jira VQRM-3741 Change-Id: Ic27ce718c62c7d7c3f8820fbd1db386a159e28f2 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1706032 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu_list in clk arb codeSourab Gupta2018-05-07
| | | | | | | | | | | | | | | | | | clk arbiter code uses linux kernel specific 'list' handling. Use 'nvgpu_list' data structure and constructs instead. Also, remove other linux includes from clk_arb.c, while at it. Jira VQRM-3741 Change-Id: I89bf73a62537447dc23726a43e1f6ad96589ae34 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1705962 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove rcu locks in clk arbiterSourab Gupta2018-05-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RCU's are available only in (linux) kernel. Though they are able to achieve lockless access in some specific scenarios, they are heavily dependent on the kernel for their functionality. E.g. synchronize_rcu(), which depends on the kernel in order to delimit read side critical sections. As such it is very difficult to implement constructs analogous to RCUs in userspace code. As a result the code which depends on RCU's for synchronization is not portable between OS'es, especially if one of them is in userspace, viz. QNX. Also, if the code is not in performance critical path, we can do with non-RCU constructs. For clk arbiter code here, RCU's are replaced by the traditional spinlocks, so that the code could be used by QNX down the line. Jira VQRM-3741 Change-Id: I178e5958788c8fd998303a6a94d8f2f328201508 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1705535 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add conversion function for poll masksSourab Gupta2018-05-07
| | | | | | | | | | | | | | | | | | | | In order to enable the movement of clk arbitrator to common code, we need to remove the linux specific POLL* defines and instead use NVGPU defines. Add a conversion function for the same. Also remove debugfs include, while at it. Jira VQRM-3741 Change-Id: I3c367625f9fa5fb8480d01bdaf6233df8cc2c722 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704885 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add conversion function for gpu alarm eventsSourab Gupta2018-05-07
| | | | | | | | | | | | | | | | | | | | | In order to enable the movement of clk arbitrator to common code, we need to remove the NVGPU_GPU_EVENT_* defines (which are present in uapi) and instead use the common code defines. Add a conversion function for the same. With this the uapi header is no longer required to be included inside clk_arb.c Jira VQRM-3741 Change-Id: If01614b01733876046f98b97e70285c52bc33e45 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699241 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu logging in clk arbiterSourab Gupta2018-05-07
| | | | | | | | | | | | | | Clk arbiter uses the legacy gk20a_dbg_fn logging APIs. Use nvgpu logging instead, while also defining a new log mask for clk arbiter. Jira VQRM-3741 Change-Id: I86feb4fa434b404705cc3fba1e854180d4df508d Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1707394 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Userspace POSIX supportAlex Waterman2018-05-07
| | | | | | | | | | | | | | | | | | | | | | Add support for compiling nvgpu in a POSIX compliant userspace. This code adds all of the necessary abstraction interfaces (mostly stubbed) to enabled extremely limited and basic functionality in nvgpu. The goal of this code is to facilitate unit testing of the nvgpu common core. By doing this in userspace it is much easier to write tests that rely on very particular states within nvgpu since a user can very precisely control the state of nvgpu. JIRA NVGPU-525 Change-Id: I30e95016df14997d951075777e0585f912dc5960 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683914 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fixups for tmake buildAlex Waterman2018-05-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly just including necessary includes to make sure that global function declarations actually match their implementations. Also work around pointer munging warning: /build/ddpx/linux/kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/pmu.c: In function 'nvgpu_pmu_process_init_msg': /build/ddpx/linux/kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/pmu.c:348:4: error: dereferencing type-punned pointer will break strict-aliasing rules [-Werror=strict-aliasing] (*(u32 *)gid_data.signature == PMU_SHA1_GID_SIGNATURE); Work around this warning by simply moving the type punning. This code is certainly dangerous - it assumes the endianness of the header data is the same as the machine this code is running on. Apparently it works, though, so this ignores the warning. JIRA NVGPU-525 Change-Id: Id704bae7805440bebfad51c8c8365e6d2b7a39eb Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1692454 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu : nvgpu: gp106 pmu f/w version updateMahantesh Kumbar2018-05-04
| | | | | | | | | | | | | | | | | | | | | | | | - gp106 f/w version update for ucode https://git-master.nvidia.com/r/1702217 - APP_VERSION_GP10X 23913597 to 24008084 - nvgpu clk_vin interface as per chips_a_23609936 CL https://git-master.nvidia.com/r/#/c/1687591/ p4 CL # 24069912 Bug 200399373 Change-Id: If16566aaf42dfc2460d426f18927eab08309dfcf Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702218 Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com> Tested-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update clk_vin interface as per chips_aVaikundanathan S2018-05-04
| | | | | | | | | | | | | | | | clk_vin data structures updated as new calibration type (v20) is added. GP106 header does not have vin calibration type. Assuming V10 if calibration type is not V20. Add fuse calibration for V20 type. Bug 200399373 Change-Id: I9449de1ecb0d0873f3bc16f46660f93fab5b9eac Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1687591 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Invalidate rpc bufferVaikundanathan S2018-05-04
| | | | | | | | | | | | | | | | | Set rpc buffer to 0xFF instead of 0x0 to handle fucntions with rpc id 0 Change-Id: Ife692d9fd19008e225975e41bb13e53522283a54 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702133 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix per-GPU DMA allocation trackingDeepak Bhosale2018-04-27
| | | | | | | | | | | | | | | | | | | | | | - total DMA memory allocation is currently tracked by adding page aligned size of nvgpu_mem - The sequence is roughly as follows: - total dma memory used += mem->aligned_size - mem->aligned_size = PAGE_ALIGN(size) - In above sequence, nvgpu_mem structure is initially zero when it is added to total dma memory used after which it is assigned page aligned value - This patch fixes total dma memory usage tracking. Change-Id: Ibb879c8d38ae9077c3d198d9bb008a72e9208b4d Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1685312 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add NULL check for simSeema Khowala2018-04-26
| | | | | | | | | | | | | | | | | sim pointer is not init for non simulation platforms. Change-Id: Ia30e66efbb009293b4e1151c2f1e4ac5d08c3d78 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1701681 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Tested-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: split clk arb codeSourab Gupta2018-04-26
| | | | | | | | | | | | | | | | | Clk arbiter code contains two significant portions - the one which interacts with userspace and is OS specific, and the other which does the heavylifting work which can be moved to the common OS agnostic code. Split the code into two files in prep towards refactoring the clk arbiter. Jira VQRM-3741 Change-Id: I47e2c5b18d86949d02d6963c69c2e2ad161626f7 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699240 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move parameter of .vm_bind_channel from as_share to vmRichard Zhao2018-04-25
| | | | | | | | | | | | | | as_share is more os specific and not yet used on other OSes. Jira VQRM-2344 Change-Id: Ie2ed007125400484352fbab602c37a198e8a64ae Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699842 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move mss nvlink credit init to os specific codeRichard Zhao2018-04-25
| | | | | | | | | | | | | | | | | | The code uses ioremap, readl_relaxed/writel_relaxed, which only exists on linux. So move them to linux folder. Also fix build errors on qnx. Jira VQRM-2344 Change-Id: Ide1176d0bf954a804187aa842a6bbfdecbdb0286 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1698973 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: GP106 PMU ucode version updateMahantesh Kumbar2018-04-25
| | | | | | | | | | | | | | | | | | - gp106 f/w version update for ucode https://git-master.nvidia.com/r/#/c/1693596/ - APP_VERSION_GP10X 23732390 to 23913597 Change-Id: Id3ae28325fda8a66b833245113e7010c76ed2750 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1693616 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com> Tested-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Check for all sysmem apertures in GMMUAlex Waterman2018-04-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow a potential IOMMU'ed GMMU mapping for all SYSMEM buffers inlcuding coherent sysmem. Typically this won't actually happen since IO coherent mappings will also often be accessed over NVLINK which is physically addressed. Also update the comments surrounding this code to take into account the new NVLINK nuances. Since NVLINK buffers are directly mapped even when the IOMMU is enabled this is very deserving of a comment explaining what's going on. Lastly add some simple functions for checking if an nvgpu_mem (or a particular aperture field) is a sysmem aperture. Currently this includes SYSMEM and SYSMEM_COH. JIRA EVLR-2333 Change-Id: I992d3c25d433778eaad9eef338aa5aa42afe597e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1665185 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: cache gpu clk rateArun Kannan2018-04-23
| | | | | | | | | | | | | | | | | | | | | | | | | Cache the rate used in clk_set_rate(). Return that cached rate on clk_get_rate(), don't read from hardware. This cached rate is used to avoid duplicate requests to clk_set_rate(). Motivation is to support multiple governors for gpu clk. Reading clock from hardware is unreliable in multi-governor situation. Relying on hardware clock value could mislead the kernel gpu governor in its scaling calculations. Bug 2051688 Change-Id: I43fc056eea6f69fe0889c45640fcb892b658071c Signed-off-by: Arun Kannan <akannan@nvidia.com> (cherry picked from commit 7f819a9ba707e6e905168b00b0f3bf6348e86188) Reviewed-on: https://git-master.nvidia.com/r/1662759 Reviewed-on: https://git-master.nvidia.com/r/1668919 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add multiple nvlink recovery modesAdeel Raza2018-04-23
| | | | | | | | | | | | | | | | | | | | Previously all nvlink recovery modes were being grouped under 1 enum. Create an enum for each recovery mode, so the link can go into specific recovery modes. Bug 2090322 Change-Id: I5c2aea758f77b0286e3538424684ddceca98a873 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1698799 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com> Tested-by: Petlozu Pravareshwar <petlozup@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: err if powergate is enabled before hwpm ctxsw mode writeSeema Khowala2018-04-23
| | | | | | | | | | | | | | | If the power gating mode is not disabled before hwpm context switch mode register write, return error. Bug 200379815 Bug 2053656 Bug 2092996 Change-Id: I656f5c38616a4250830779d2bca5e207ff28f3a9 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1688219 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: sync_framework cleanupsDebarshi Dutta2018-04-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch deals with cleanups meant to make things simpler for the upcoming os abstraction patches for the sync framework. This patch causes some substantial changes which are listed out as follows. 1) sync_timeline is moved out of gk20a_fence into struct nvgpu_channel_linux. New function pointers are created to facilitate os independent methods for enabling/disabling timeline and are now named as os_fence_framework. These function pointers are located in the struct os_channel under struct gk20a. 2) construction of the channel_sync require nvgpu_finalize_poweron_linux() to be invoked before invocations to nvgpu_init_mm_ce_context(). Hence, these methods are now moved away from gk20a_finalize_poweron() and invoked after nvgpu_finalize_poweron_linux(). 3) sync_fence creation is now delinked from fence construction and move to the channel_sync_gk20a's channel_incr methods. These sync_fences are mainly associated with post_fences. 4) In case userspace requires the sync_fences to be constructed, we try to obtain an fd before the gk20a_channel_submit_gpfifo() instead of trying to do that later. This is used to avoid potential after effects of duplicate work submission due to failure to obtain an unused fd. JIRA NVGPU-66 Change-Id: I42a3e4e2e692a113b1b36d2b48ab107ae4444dfa Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1678400 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement dGPU simulation supportTerje Bergstrom2018-04-22
| | | | | | | | | | | | | Implement support for dGPU fmodel. The message protocol is slightly different and accessed via BAR0 aperture. JIRA NVGPUT-41 Change-Id: Ide3c52a751530f520854965c1eba19fa8339a315 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694963 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support PCI device 0x1e3fDeepak Nibade2018-04-22
| | | | | | | | | | | | | | | | Add PCI device ID for 0x1e3f and also add gk20a_platform data for same Jira NVGPUT-42 Change-Id: I3a6fb8ac4378d45add09795134da8fd3b174ac56 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699311 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: post dbg session event from os specific codeSourab Gupta2018-04-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of debug session unification following changes are required. -Including bug.h header file to fix the compilation issue on QNX - The mechanism of posting debug events is OS specific. In Linux this works through poll fd, wherein we can make use of nvgpu_cond variables to poll and trigger the corresponding wait_queue via nvgpu_cond_broadcast_interruptible() call. The post event functionality on QNX doesn't work on poll though. It uses iofunc_notify_trigger to post the debug events to calling process. As such QNX can't work with nvgpu_cond's. To overcome this issue, it is proposed to create a OS specific interface for posting debugger events. Linux can call nvgpu_cond_broadcast_interruptible() in its implementation, which makes sense since these are already initialized and poll'ed in the Linux specific code only. QNX can implement this interface to call iofunc_notify_* functions, as per its need Jira VQRM-2363 Change-Id: I0abdc0787f771040b8aff5384290d7e6549f81fb Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Signed-off-by: Prateek Sethi <prsethi@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1696368 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: assume 1:1 IPA to PA mapping for syncptThomas Fleury2018-04-19
| | | | | | | | | | | | | | | | | | | | | Currently, hyp_read_ipa_pa_info() only translates IPA for RAM mappings. It fails for MMIO mappings. In particular, it will fail when attempting to translate addresses in the syncpoint shim aperture. As a workaround, assume 1:1 IPA to PA mapping when hyp_read_ipa_pa_info fails, and address is in syncpt shim aperture. Bug 2096877 Change-Id: I5267f0a8febf065157910ad3408374cacd398731 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1687796 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix map buffer overflow handling.Ashutosh Jain2018-04-17
| | | | | | | | | | | | | | | | | | | | Currently in case of overflow in buffer mapping the dma buf fd reference is not freed which causes the handle to remain allocated forever. Bug 200398767 Change-Id: Id3bf88636b927d75595f8a8b9f240b6717bf3b57 Signed-off-by: Ashutosh Jain <ashutoshj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694864 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pass pid/tid from os specific code to common codeRichard Zhao2018-04-16
| | | | | | | | | | | | | | | | | | linux driver runs in user's process but qnx driver has dedicate driver process, so they have different way to get user pid. nvgpu common code expect calls from os specific code pass pid/tid. ce/cde open channel for internal use, we use driver pid. Jira VQRM-3534 Change-Id: I892372ac5f1dc4d25f9928d16992bcc659d12a56 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694145 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: enable elcg, blcg, slcgSeema Khowala2018-04-12
| | | | | | | | | | | | | | Bug 200399393 Change-Id: I60b2704ba447e45c330f2dc133cb2fa17e107f1c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683105 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp106 f/w version updateMahantesh Kumbar2018-04-12
| | | | | | | | | | | | | - gp106 f/w version update for ucode https://git-master.nvidia.com/r/#/c/1684238/ - APP_VERSION_GP10X "23647537" updated to "23732390" Change-Id: Id534b041e4ae90e82b2a8259bb0372689500e871 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1684250 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update clk_fll interface as per chips_aTejal Kudav2018-04-12
| | | | | | | | | | | | | | | | | | | Two new members added to fll struct and code modified to support GV100 VBIOS NAFLL tables Add g->ops for getting vbios clk domains JIRA NVGPUGV100-39 Change-Id: Iaabea893d55d44a272e2bce2b1d525b122cd36f5 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594289 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove uapi include from ce2Sourab Gupta2018-04-11
| | | | | | | | | | | | | | | | | Remove the include of a uapi header from ce2.c since this file no longer makes use of any uapi definition. VQRM-3465 Change-Id: Ib9ba7090021f5fc21734adca80be8a0ea224bf90 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691980 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add conversion function for uapi submit gpfifo flagsSourab Gupta2018-04-11
| | | | | | | | | | | | | | | | | | The submit gpfifo flags are splattered everywhere inside the nvgpu code. Though the usage is inside nvgpu Linux code only, still it needs to be gotten rid of and replaced with the defines present in common code. VQRM-3465 Change-Id: I901b33565b01fa3e1f9ba6698a323c16547a8d3e Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691979 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove usage of nvgpu_gpfifoSourab Gupta2018-04-11
| | | | | | | | | | | | | | | | | | | Remove the usage of nvgpu_gpfifo splattered across nvgpu, and replace with a struct defined in common code. The usage is still inside Linux, but this helps the subsequent unification efforts, e.g. to unify the submit path. VQRM-3465 Change-Id: I9e5ac697a0c7f85239ddba319085c09481d20d6b Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691978 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove usage of nvgpu_fenceSourab Gupta2018-04-11
| | | | | | | | | | | | | | | | | | | Remove the usage of nvgpu_fence splattered across nvgpu, and replace with a struct defined in common code. The usage is still inside Linux, but this helps the subsequent unification efforts, e.g. to unify the submit path. VQRM-3465 Change-Id: Ic3737450123dfc5e1c40ca5b6b8d8f6b3070aa0d Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691977 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix misc issue for dgpu code on QNX buildShashank Singh2018-04-10
| | | | | | | | | | | | | | | | - QNX is pulling dgpu code from linux which has multiple build failure on QNX. Like QNX needs explicit declaration for all non-static functions. Some linux specific headers need to be put under __KERNEL__ flag. Change-Id: I15af1a1f6a069c82f9a81449f4f7c7d48612de42 Signed-off-by: Shashank Singh <shashsingh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1665752 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check null before accessing nvgpu_firmware.Debarshi Dutta2018-04-10
| | | | | | | | | | | | | | | | | | | check for null value of nvgpu_firmware before accessing them in nvgpu_firmware_release(). Coverity defect id: 2983427, 2983428 Bug 200291879 Change-Id: I946cb448351441ee820aa3e5d8db649943d20d16 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683505 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use tegra_alloc_fd() only on Tegra kernelTerje Bergstrom2018-04-06
| | | | | | | | | | | | | | | | tegra_alloc_fd() exists only in Tegra kernel. Use get_unused_fd_flags() in other platforms. JIRA NVGPU-4 Change-Id: I12b16957263f6cea771314a9da229384c865e65f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1689538 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100 temperature read supportMahantesh Kumbar2018-04-06
| | | | | | | | | | | | | | | | | | | | | | - Enabled internal temperature sensor read for gv100 dgpu. - Added check to temperature read support before proceeding to read temperature from H/W - Assigned GP106 temperature HAL's for GV100 as no changes between GP106 & GV100 H/W registers. Bug 200352328 Change-Id: I86b5a1859b87ace49a07d0ff3749bb5b085bba91 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673347 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: De-linuxify pmgr codeAlex Waterman2018-04-05
| | | | | | | | | | | | | | | | | | | | The pmgr code is in theory common code. However there were uses of Linux stuff within this code. This patch cleans that up by deleting the unnecessary os_linux.h includes, usage of kfree() and adds several platform fields to the gk20a struct. The platform data is copied to the gk20a struct in the platform initialization code so that this common code can access said data without requiring any knowledge of the OS platform data. JIRA NVGPU-525 Change-Id: Ic4bb6021f60b0a0778779ab5f3e15b7e5ca98306 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673825 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pass alloc_gpfifo args to gk20a_channel_alloc_gpfifoSourab Gupta2018-04-05
| | | | | | | | | | | | | | | | The patch defines 'struct nvgpu_gpfifo_args' to be filled by alloc_gpfifo(_ex) ioctls and passed to the gk20a_channel_alloc_gpfifo function. This is required as a prep towards having the usermode submission support in the core channel core. Change-Id: I72acc00cc5558dd3623604da7d716bf849f0152c Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683391 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 02:22:42 -0400