| Commit message (Collapse) | Author | Age |
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Add characteristic flag NVGPU_GPU_FLAGS_SUPPORT_SYNCPOINT_ADDRESS to indicate if
platform supports semaphore GPU_VA address for a syncpoint
Define NVGPU_SUPPORT_SYNCPOINT_ADDRESS for core driver book keeping
Set this flag for both GV100 and GV11B since Xavier SoC supports a semaphore
GPU_VA address for a syncpoint through syncpoint SHIM
Bug 200327559
Change-Id: I1f31673c9fd59f493d0b35a80d23151fc063ae06
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1649364
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Indicated support for Simultaneous Compute and Graphics(SCG)
in gpu characteristics for gv11b.
Bug 2053932
Change-Id: I788e22242083dff775dd4cc5b9aa73c938028536
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1649805
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The GPU has multiple different operating modes in respect to IOMMU'ability.
As such there needs to be a clean way to tell the driver whether it is
IOMMU'able or not. This state also does not always reflect what is possible:
all becasue the GPU can generate IOMMU'ed memory requests doesn't mean it
wants to.
The nvgpu_iommuable() API has now existed for a little while which is a
useful way to convey whether nvgpu should consider the GPU as IOMMU'able.
However, there is also the g->mm.bypass_smmu flag which used to be able to
override what the GPU decided it should do. Typically it was assigned
the same value as nvgpu_iommuable() but that was not necessarily a
requirment.
This patch removes all the usages of g->mm.bypass_smmu and instead uses the
nvgpu_iommuable() function. All places where the check against
g->mm.bypass_smmu have been replaced with nvgpu_iommuable(). The code
should now be much cleaner.
Subsequently other checks can also be placed in the nvgpu_iommuable()
function. For example, when NVLINK comes online and the GPU should no
longer consider DMA addresses and instead use scatter-gather lists
directly the ngpu_iommuable() function will be able to check the state of
NVLINK and then act accordingly.
Change-Id: I0da6262386de15709decac89d63d3eecfec20cd7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1648332
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nvlink core library no longer exposes the set_init_state()
interface as it wishes to block init_state changes from
endpoint drivers.
Now, the core driver is responsible for initializing init_state
variables using set_init_state() interface. Hence, we remove
this redundant code.
Change-Id: I81c4922cf48f7918e69795579b39b7fa0c299644
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1646437
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Set the DMA mask to 34 bits so that large DMA allocs can be done.
Currently the DMA mask is left unset which limits the size of the
maximum DMA allocation to 32 bits.
The 34 bit mask was chosen because it works for all chips (even
gm20b supports 34 bit physical addresses). However, newer chips
could use larger masks in the future if they desire.
Bug 200377221
Change-Id: Iaa0543f77ff4e2bd6616f38e4464240375bb37b6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1641762
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After moving devfreq enable to end of finalize power on,
intermittent issues related to gpu booting with devfreq
enabled are fixed.
Enabled devfreq for gv11b by enabling ""nvhost_podgov"
governor in platform data.
Reused scaling functions from gp10b/gk20a.
Removed emc floor on railgate for power saving.
Added max emc frequency as floor in rail-ungate for
faster gpu boot.
Bug 2049965
Bug 2039013
Bug 200377508
Change-Id: Ia1dec278b663b9f7ed859dd953a60f3eae7ef9a0
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644702
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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VM and CDE code assumes that dma_buf_attachment is stored as a pointer
in the private dma_buf_drvdata, so it is not tracked. In Linux trees
without dma_buf_*_drvdata() support this is not true, so change the
code to explicitly track dma_buf_attachment.
JIRA NVGPU-4
Change-Id: I692f05a19a6469195d5444a7e5ff6e92f77ae272
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1648004
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The IOCTL was introduced for making efficient query of buffer
identity and size. It was never taken into use, and it adds a
dependency to Tegra specific dma_buf API, so remove it.
JIRA NVGPU-4
Change-Id: I194d7bb1f54997900a3be8d39c93331befa225c7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1648001
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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gpu frequency scaling is available only on silicon
platforms. Added check for silicon platform before
enabling scaling init.
Bug 2049965
Bug 2039013
Bug 200377508
Change-Id: Ie780147cee904137e4618e17162e5cedba4987ee
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1642529
Reviewed-by: Automatic_Commit_Validation_User
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Enabling gpu scaling driver after finalize poweron,
will make gpu booting happen at initially set
frequency(1GHz).
Also doing platform specific init scale after enabling
scaling driver.
Bug 2049965
Bug 2039013
Bug 200377508
Change-Id: I633f8f5a25d9de18cbb3a022913b8b725ccd87e5
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644703
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Stream ID for gp10b is retrieved directly from DT headers in common
code. Introduce instead a variable to store the stream ID and move the
query to platform_gp10b_tegra.c.
JIRA NVGPU-4
Change-Id: I123024e13e470283bb691883f8f963eb72c997d8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1648013
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gr_ctx->tsgid needs to be set to ensure that the GR ctx
free sequence will target the correct TSG's GR ctx.
Bug 200341631
Change-Id: I83c57597f10ce3af572f114d28312376cea55c2a
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1646790
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Enable ELCG, BLCG and SLCG features.
Bug 2051863
Change-Id: Id2c67c94c7b2dd0517d4ee4b0280aeb19f3fe35a
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1646302
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tegra_gr_comm_* are wrapped as vgpu_ivc_*, which helps make vgpu code
more common.
Jira EVLR-2364
Change-Id: Id49462ed6c176c73ceee8c6bc41104447748e187
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1645656
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
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The message to tell RM server to unbind channel has to be sent after
client unbinds the channel and before client calls tsg release. The
channel has to belong to a tsg on RM server before client submit a
runlist to remove the channel. Or there's a bare channel problem.
By moving .tsg_unbind_channl one layer lower, gk20a_tsg_unbind_channel()
will be common functions for all chip, and it'll call tsg release after
call .tsg_unbind_channel. So vgpu won't need to worry about tsg was
released before sending msg to RM server.
Bug 200382695
Bug 200382785
Change-Id: I32acc122f3f9d5d0628049ccf673225f9e90c87a
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1645383
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Patch 7240b3c2 enabled secure allocation for gv11b
But since we allocate secure buffers in poweron path, and secure allocation
needs GPU to be in off state, this results in deadlock in poweron path
To solve this, we already cause early VPR resize for older chips by calling
gk20a_tegra_secure_page_alloc() from late_probe
Implement same for gv11b.
Add late_probe callback and add a call to gk20a_tegra_secure_page_alloc()
Bug 2038249
Change-Id: I8c17b069962b26edbd0639a7c0d6c2fdaa352935
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1648831
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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queue index can already index the queues. It also help make the api more
common.
Jira EVLR-2364
Change-Id: I98a5014ba0510a2687fdf096a160c497bd1f6985
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1646197
Reviewed-by: Damian Halas <dhalas@nvidia.com>
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Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
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Simplify the copyengine code massively by storing the job post fence
pointers in an array of fences instead of mixing them up in the command
buffer memory. The post fences are used when the ring buffer of a
context gets full and we need to wait for the oldest slot to free up.
NVGPU-43
NVGPU-52
Change-Id: I36969e19676bec0f38de9a6357767a8d5cbcd329
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1646037
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Delete the gk20a_fence_in argument in gk20a_ce_execute_ops. It has never
been used and is in the way of some upcoming code cleanup.
NVGPU-43
Change-Id: Ie61e1a2f4945b1e34d64880044c265d26fa822d7
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1646036
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Enable NVGPU_SUPPORT_IO_COHERENCE characteristics for dGPUs which support
DMA_COHERENCE e.g. GV100
Bug 200383034
Change-Id: If12d2ef6c642f7c4cce83dbf05f492100ee1c7e0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644277
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Adds the skeleton and integration of the GV100 endpoint driver to NVGPU
(1) Adds a OS abstraction layer for the internal nvlink structure.
(2) Adds linux specific integration with Nvlink core driver.
(3) Adds function pointers for nvlink api, initialization and isr process.
(4) Adds initial support for minion.
(5) Adds new GPU enable properties to handle NVLINK presence
(6) Adds new GPU enable properties for SG_PHY bypass (required for NVLINK over
PCI)
(7) Adds parsing of nvlink vbios structures.
(8) Adds logging defines for NVGPU
JIRA: EVLR-2328
Change-Id: I0720a165a15c7187892c8c1a0662ec598354ac06
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644708
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Data can be speculatively loaded from memory and stay in cache even
when bound check fails. This can lead to unintended information
disclosure via side-channel analysis.
To mitigate this problem insert a speculation barrier.
bug 2039126
CVE-2017-5753
Change-Id: Iec23eb75ce2a9251c8a5c8cbdd21a32910e1a71a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640502
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Data can be speculatively loaded from memory and stay in cache even
when bound check fails. This can lead to unintended information
disclosure via side-channel analysis.
To mitigate this problem insert a speculation barrier.
bug 2039126
CVE-2017-5753
Change-Id: I982225e754cc5d430c19f4cc542302e52243bd38
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640501
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Data can be speculatively loaded from memory and stay in cache even
when bound check fails. This can lead to unintended information
disclosure via side-channel analysis.
To mitigate this problem insert a speculation barrier.
bug 2039126
CVE-2017-5753
Change-Id: Idf09b8d64dbdc2b0e4b504d4d7ea0197d38157d3
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640499
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Data can be speculatively loaded from memory and stay in cache even
when bound check fails. This can lead to unintended information
disclosure via side-channel analysis.
To mitigate this problem insert a speculation barrier.
bug 2039126
CVE-2017-5753
Change-Id: I6b8af794ea2156f0342ea6cc925051f49dbb1d6e
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640498
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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These '\n' were leftover from the previous debugging macro usage
which did no add the '\n' automagically. However, once swapped over
to the nvgpu logging system the '\n' is added and no longer needs
to be present in the code.
This did require one extra modification though to keep things
consistent. The __alloc_pstat() macro, used for sending output
either to a seq_file or the terminal, needed to add the '\n' for
seq_printf() calls and the '\n' had to be deleted in the C files.
Change-Id: I4d56317fe2a87bd00033cfe79d06ffc048d91049
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1613641
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Created nv_pmu_rpc_struct_acr_bootstrap_gr_falcons struct
- gv100_load_falcon_ucode() function to bootstrap GR
flacons using RPC, wait for INIT_WPR_REGION before
creating & executing BOOTSTRAP_GR_FALCONS RPC.
- Added code to handle BOOTSTRAP_GR_FALCONS ack in
RPC handler
Change-Id: If70dc75bb2789970382853fb001d970a346b2915
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1613316
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Created nv_pmu_rpc_struct_acr_init_wpr_region struct
- Function gv100_pmu_init_acr() to create & execute
INIT_WPR_REGION using RPC.
- Updated gv100 HAL .init_wpr_region to point
to gv100_pmu_init_acr()
- Added code to handle INIT_WPR_REGION ack in
RPC handler.
Change-Id: I699fa945790689e5f24ad5d3de022efb458662e0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1613290
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-Added new version of pmu init msg "pmu_init_msg_pmu_v5"
-created methods to support new pmu init message parameter
read based on f/w version for below ops.
.get_pmu_msg_pmu_init_msg_ptr
.get_pmu_init_msg_pmu_sw_mg_off
.get_pmu_init_msg_pmu_sw_mg_size
-Corrected PMU_DMEM_ALLOC_ALIGNMENT value to 32 bit
to allocate PMU DMEM space for nvgpu
-Updated PMU version of GV100/APP_VERSION_BIGGPU
to 23440730 & PMU ucode CL is
https://git-master.nvidia.com/r/#/c/1642432/
Change-Id: Ib1e0197b5f3a229a601e810c9c0d93f05b9d69e7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1642229
Reviewed-by: Automatic_Commit_Validation_User
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In the nvgpu_big_free() function the passed in address is checked
to see what type of address it is: kmalloc or vmalloc. This change
uses the is_vmalloc_addr() instead since this is a much clearer and
easier way to determine if a virtual address should be vfree()ed.
Anything not a vmalloc address is then assumed to be a kmalloc()
address.
Bug 2049449
Change-Id: I2bd9441d3c5fc455f03ec2075d012c607280ad5f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644802
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Arun Kannan <akannan@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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It has to be set to detach snapshot. We missed it somehow.
Jira VFND-4703
Change-Id: Ia5842494f86fb2d788d72ba372ee8870977a2f67
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640668
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com>
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This reverts commit 4021d42cbb37c6d7cd30bd132d1d08d004422917.
Original change was reverted since that was suspected to have caused
opengles test faulure on QNX, but it turned out that the original change
was actually not causing the failure. Hence original change is restored.
Change-Id: I64796f1a3b1f700f294c259d4426c493f2f1ad85
Signed-off-by: Inamdar Sharif <isharif@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1643309
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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This reverts commit 968d8cd3e543b951714d9a86373bd721d08c8482.
Bug 2049965
Bug 2039013
Bug 200377508
Change-Id: I813947417740f8d3a0c9bea82784df1dd4a5f1ac
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644224
Reviewed-by: David Pu <dpu@nvidia.com>
Tested-by: David Pu <dpu@nvidia.com>
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-removed unsupported PMU f/w version defines &
corrected naming specific to chip
-removed unsupported PMU f/w version methods
which are not useful for existing ucode.
-removed unsupported PMU interface which are not
useful for existing ucode
Change-Id: I17933ff656f48a888e049d680f108b2ef7537439
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1643399
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Lots of code paths were split to T19x specific code paths and structs
due to split repository. Now that repositories are merged, fold all of
them back to main code paths and structs and remove the T19x specific
Kconfig flag.
Change-Id: Id0d17a5f0610fc0b49f51ab6664e716dc8b222b6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640606
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Added sw method support for SET_BES_CROP_DEBUG4.
In this sw method:
CLAMP_FP_BLEND_TO_MAXVAL forces overflow and
CLAMP_FP_BLEND_TO_INF blend results to clamp to FP maxval.
Added support for this sw method in gp10b/gp106/gv11b
and gv100.
Bug 2046636
Change-Id: I3a9e97587aca76718f7f504ea3b853f87409092a
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1641529
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Fix a race condition where we'd still be booting up the gpu and/or
initializing the driver but elsewhere assume that all is done already.
Some userspace APIs to make sure that we're ready by testing
g->gr.sw_ready, but this flag is set in the middle of bootup; there are
other things after gr initialization. Add a new flag that is enabled
after bootup is fully complete at the end of finalize_poweron, and
change the checks in user API paths to test the new flag only.
These checks are only in the ioctl paths for ctrl, dbg and tsg, and in
the ctrl device's opening path.
The gr.sw_ready flag is still left there to signify whether just gr has
had its bookkeeping initialized.
Bug 200370011
Change-Id: I2995500e06de46430d9b835de1e9d60b3f01744e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640124
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This reverts commit c713934675b32b30f3939f3ab4dd7466eb96a523.
since this change is causing ap_opengles_screen to fail on
embedded-qnx-hv
Change-Id: I812d3483df961def492fb49c14911f6bcca36da4
Signed-off-by: Inamdar Sharif <isharif@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1642759
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In the buddy allocator use the actual size of the PDE to determine
the pte_blk_order field which is used to determine what page size a
buddy has (or doesn't). Previously this was just set as the large
page size times 1024 which would over allocate PDE ranges for Pascal+
chips. This caused userspace, which was using the real PDE size, to
sometime allocate small and large pages in what the buddy allocator
mistakenly thought was one PDE.
Bug 200105199
Change-Id: I7ab7db7962015fc268bad61b558a18704133e1cb
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639731
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The mm_gk20a.c function that returns number of bits that a PDE covers
is very useful for determing PDE size for all chips. Copy this into
the common VM code since this applies to all chips/platforms.
Bug 200105199
Change-Id: I437da4781be2fa7c540abe52b20f4c4321f6c649
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639730
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Syncpoints can longer be disabled/enabled during run time as
NVGPU_HAS_SYNCPOINTS flag is set based on has_syncpoints
value in platform data during probe. Based on this, either
of syncpoint or semaphore pool is initialized.
Bug 2040115
Change-Id: Ib256e1a6ec8b1584799adb6f183fd567aebfaf13
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640380
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Enable devfreq for gv11b by enabling ""nvhost_podgov"
governor in platform data.
Reuse scaling functions from gp10b/gk20a.
Remove emc floor on railgate for power saving and make
max emc frequency as floor in rail-ungate for faster gpu boot.
Bug 2039013
Bug 200377508
Change-Id: I65ee7735202e3decbe3451157f7fc1f1f273c3ff
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639752
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Rename gb10b_init_bar2_vm*() to gp10b_init_bar2_vm*().
Bug 200378257
Change-Id: I9f8a9ef42c82923200d7053c61bab2652b58cbc2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639757
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t19x PMU ucode uses RPC mechanism for
PERFMON commands.
- Declared "pmu_init_perfmon",
"pmu_perfmon_start_sampling",
"pmu_perfmon_stop_sampling" and
"pmu_perfmon_get_samples" in pmu ops
to differenciate for chips using RPC & legacy
cmd/msg mechanism.
- Defined and used PERFMON RPC commands for t19x
- INIT
- START
- STOP
- QUERY
- Adds RPC handler for PERFMON RPC commands.
- For guerying GPU utilization/load, we need to send PERFMON_QUERY
RPC command for gv11b.
- Enables perfmon for gv11b.
Bug 2039013
Change-Id: Ic32326f81d48f11bc772afb8fee2dee6e427a699
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1614114
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Created nv_pmu_rpc_cmd & nv_pmu_rpc_msg struct, &
added member rpc under pmu_cmd & pmu_msg
- Created RPC header interface
- Created RPC desc struct & added as member to pmu payload
- Defined PMU_RPC_EXECUTE() to convert different RPC
request to make generic RPC call.
- nvgpu_pmu_rpc_execute() function to execute RPC request
by creating required RPC payload & send request to PMU
to execute.
- nvgpu_pmu_rpc_execute() function as default callback handler
for RPC if caller not provided callback
- Modified nvgpu_pmu_rpc_execute() function to include check
of RPC payload parameter.
- Modified nvgpu_pmu_cmd_post() function to handle RPC
payload request.
JIRA GPUT19X-137
Change-Id: Iac140eb6b98d6bae06a089e71c96f15068fe7e7b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1613266
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Add cleanup to the gk20a_probe() function since it will often fail
due to probe deferal. These "failures" cause this function to be
called multiple times and potentially allocate many resources over
and over again, leaking the old allocations.
Bug 200369627
Change-Id: Ic0bba0ae6542485135d9cb7393086e4460cd271d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640628
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Avoid railgating platform, if it is already in railgated state.
This is right thing to do and it also avoids ref counting issues
related to fuse clock disable.
Bug 200381275
Change-Id: Id745f9b878be129bf9b0cc972fadcfc102c8ddc2
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640548
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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bypass_smmu is set based on whether device_is_iommuable
or not during probe. It cannot be changed during runtime.
Change-Id: I69fd29c87ea3873652a4eb95764f52dc40abf483
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640381
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Move graphics context ownership to TSG instead of channel. Combine
channel_ctx_gk20a and gr_ctx_desc to one structure, because the split
between them was arbitrary. Move context header to be property of
channel.
Bug 1842197
Change-Id: I410e3262f80b318d8528bcbec270b63a2d8d2ff9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639532
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Modify rpc command parameter to support l3 cache
allocation.
Jira EVLR-1752
Change-Id: I1be00e04ee01c0763f46c0d0da6a112316cc7e1d
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1616566
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