| Commit message (Collapse) | Author | Age |
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- ZBC save/restore registers are removed in GP10B PMU ucode.
- These registers are saved/restored from CTXSW ucode during
ELPG entry/exit.
- Accessing the ZBC registers will cause PMU EXTERR error.
- To resolve this, ZBC functionality is removed from GP10B
feature list in PMU ucode.
- From NvGPU driver, set NVGPU_PMU_ZBC_SAVE bit to false
for GP10B
- Updated the GP10B PMU app version for the ucode:
https://git-master.nvidia.com/r/c/tegra/kernel-firmware-t18x/+/2476260
P4 CL link related to this PMU ucode change:
https://p4sw-swarm.nvidia.com/changes/29594520
Bug 3233071
Bug 200696431
Change-Id: If3f1707b79699e7e2e65367418b25ac71b09cf0b
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2476259
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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blcg is always enabled by default and there is no need for disabling
this during gr init or gr reset.
Bug 2866010
Change-Id: Iaf17b7fdf05ad04fe435e1a1fda758deedc6484c
Signed-off-by: ddutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2303114
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This patch help resolve the boot time failures happening with
pmu_exterr for porg. cg_enable can race with pmu_init thread,
cg_enable is moved post pmu init thread to avoid the above race.
Bug 200565050
Change-Id: I2192053eff8767847ea012ca20b3607d2f6cd26f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2239959
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Typically, the PMU init thread will finish up long
before the golden context image has been initialized,
which means that ELPG hasn't truly been enabled at that
point.
Create a new function, nvgpu_pmu_reenable_pg(), which
checks if elpg had been enabled (non-zero refcnt), and
if so, disables then re-enables it.
Call this function from gk20a_alloc_obj_ctx() after
the golden context image has been initialized to ensure
that elpg is truly enabled.
Manually ported from dev-main
Bug 200543218
Change-Id: I0e7c4f64434c5e356829581950edce61cc88882a
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2245768
(cherry picked from commit 077b6712b5a40340ece818416002ac8431dc4138)
Reviewed-on: https://git-master.nvidia.com/r/2250091
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A call to exit the PMU state machine/kthread must
be prioritized over any other state change.
It was possible to set the state as PMU_STATE_EXIT,
signal the kthread and overwrite the state before
the kthread has had the chance to exit its loop.
This may lead to a "lost" signal, resulting in
indefinite wait during the destroy sequence.
Faulting sequence:
1. pmu_state = PMU_STATE_EXIT in nvgpu_pmu_destroy()
2. cond_signal()
3. pmu_state = PMU_STATE_LOADING_PG_BUF
4. PMU kthread wakes up
5. PMU kthread processes PMU_STATE_LOADING_PG_BUF
6. PMU kthread sleeps
7. nvgpu_pmu_destroy() waits indefinitely
This patch adds a sticky flag to indicate PMU_STATE_EXIT,
irrespective of any subsequent changes to pmu_state.
The PMU PG init kthread may wait on a call to
NVGPU_COND_WAIT_INTERRUPTIBLE, which requires a
corresponding call to nvgpu_cond_signal_interruptible()
as the core kernel code requires this task mask to
wake-up an interruptible task.
Bug 2658750
Bug 200532122
Change-Id: I61beae80673486f83bf60c703a8af88b066a1c36
Signed-off-by: Abhiroop Kaginalkar <akaginalkar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2177112
(cherry picked from commit afa49fb073a324c49a820e142aaaf80e4656dcc6)
Reviewed-on: https://git-master.nvidia.com/r/2190733
Tested-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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This is to prevent GPU (and thus EMC) frequency from being boosted
from time to time when system is completely idle. It's caused by max
GPU load being incorrectly reported by perfmon. When the issue
happens, it can be observed that max load is reported but busy_cycles
read from PMU is actually zero.
Even though busy and total cycles returned by PMU may not be
completely accurate when counter overflows, the counters
accumulated so far still have some value that we shouldn't ignore.
OTOH, returning max load could be the least accurate approximation in
such cases. So let's just clear the interrupt status and let rest of
the code handle the exception cases.
Bug 200545546
Change-Id: I6882ae265029e881f5417fb2b82005b0112b0fda
Signed-off-by: Leon Yu <leoyu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180771
Reviewed-by: Peng Liu <pengliu@nvidia.com>
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Add new power/clock gating functions that can be called by
other units.
New clock_gating functions will reside in cg.c under
common/power_features/cg unit.
New power gating functions will reside in pg.c under
common/power_features/pg unit.
Use nvgpu_pg_elpg_disable and nvgpu_pg_elpg_enable to disable/enable
elpg and also in gr_gk20a_elpg_protected macro to access gr registers.
Add cg_pg_lock to make elpg_enabled, elcg_enabled, blcg_enabled
and slcg_enabled thread safe.
JIRA NVGPU-2014
Change-Id: I00d124c2ee16242c9a3ef82e7620fbb7f1297aff
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2025493
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
(cherry-picked from c90585856567a547173a8b207365b3a4a3ccdd57 in
dev-kernel)
Reviewed-on: https://git-master.nvidia.com/r/2108406
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PMU counters #0 and #4 are used to count total cycles and busy cycles.
These counts are used by podgov to estimate GPU load.
PMU idle intr status register is used to monitor overflow. Overflow
rarely occurs because frequency governor reads and resets the counters
at a high cadence. When overflow occurs, 100% work load is reported to
frequency governor.
Bug 1963732
Change-Id: I046480ebde162e6eda24577932b96cfd91b77c69
Signed-off-by: Peng Liu <pengliu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1939547
(cherry picked from commit 34df0035194e0203f68f679acdd84e5533a48149)
Reviewed-on: https://git-master.nvidia.com/r/1979495
Reviewed-by: Aaron Tian <atian@nvidia.com>
Tested-by: Aaron Tian <atian@nvidia.com>
Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
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In nvgpu_kill_task_pg_init(), call nvgpu_thread_join()
if the init thread is no longer running in order to
reclaim thread resources.
Bug 2452799
JIRA ESRM-437
Change-Id: Id9c67f689027f00039ac2df226ee9c28ad89dd1d
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1967983
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Reviewed-by: Rahul Jain (SW-TEGRA) <rahuljain@nvidia.com>
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While tearing down PMU state during power off, nvgpu doesn't disable
the PMU interrupts. Disable them unconditionally.
Bug 200457485
Change-Id: Ia2462d879c1e7bbb4b5e8295ce211c38567c13e5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1939025
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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PMU ucode is updated to use acrlib from t19xbringup
branch.
We are seeing build issues due to incompatibility
with acrlib from tegra_acr branch.
CTX_DMA aperture to be used for loading LS falcons
needed update in the local acrlib.
Bug 2400729.
Change-Id: Iad00a332acfac307c389bde504893a87abaf7460
Signed-off-by: Deepak <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1849182
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-Removed _dmem postfix to some functions which
can be common for DMEM & EMEM queue, and
made changes as needed.
-Defined flcn_queue_push_emem() &
flcn_queue_pop_emem() functions to
to read/write queue data to/from EMEM
-Defined flcn_queue_init_emem_queue()
function to assign EMEM specific functions
to support EMEM queue type.
-Defined QUEUE_TYPE_DMEM to support
DMEM based queue.
-Defined QUEUE_TYPE_EMEM to support
EMEM based queue.
-Modified nvgpu_flcn_queue_init() to call queue
type flcn_queue_init_dmem/emem_queue()
function to assign its ops.
JIRA NVGPU-1161
Change-Id: I06333fa318b7ca4137c977ad63f5a857e7b36cc8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1841084
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PMU version update for ucode CL
https://git-master.nvidia.com/r/1844810
JIRA NVGPUT-85
Change-Id: I87ca4d06fdae0fb6977e7aaf3cba7ded00d23ac1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1844863
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Move all files under perf/* to pmu_perf/* since pmu_perf is logically
appropriate name for PMU's perf unit
Rename perf.c to pmu_perf.c
Also rename the HAL from gops.perf to gops.pmu_perf
Jira NVGPU-1102
Change-Id: I79e73b8b102ddf6b49783c2f38d861cd43b0b4c6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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Update header path of gk20a.h in files present in common/
to <nvgpu/gk20a.h>
Jira NVGPU-597
Change-Id: I3431dae93ada9bd561454c89a0b99c5292ab4a8d
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832024
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-Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c
method nvgpu_init_pmu_support()
-Modified nvgpu_init_pmu_support() to init required interface
for PMU RTOS & does start PMU RTOS in secure & non-secure
based on NVGPU_SEC_PRIVSECURITY flag.
-Created secured_pmu_start ops under PMU ops to start PMU
falcon in low secure mode.
-Updated PMU ops update_lspmu_cmdline_args, setup_apertures &
secured_pmu_start assignment for gp106 & gv100 to support
modified PMU init sequence.
-Removed duplicate PMU non-secure bootstrap code from multiple
files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method
to handle non secure PMU bootstrap, reused this method
for need chips.
JIRA NVGPU-1146
Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1818099
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- Removed ACR support code from PMU module
- Deleted ACR related ops from pmu ops
- Deleted assigning of ACR related ops
using pmu ops during HAL init
-Removed code related to ACR bootstrap &
dependent code for all chips.
JIRA NVGPU-1147
Change-Id: I47a851a6b67a9aacde863685537c34566f97dc8d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1817990
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There was a race condition between pmu_rpc_handler and
nvgpu_pmu_rpc_execute. The later could free the buffer before
pmu_rpc_handler could access related data.
Added explicit field in rpc_payload, so that nvgpu_pmu_rpc_execute
can wait until pmu_rpc_handler completes.
Bug 2331655
Change-Id: Ic2653524159eff10504b9c2625b5241610b5f5f0
Reviewed-on: https://git-master.nvidia.com/r/1811299
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1817582
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In case of VFE update, schedule work to set P0 clocks.
Added function nvgpu_clk_set_fll_clk_gv10x to update P0 clocks on perf event.
Fixed MISRA issues caused by this excluding external functions and MACROs
Bug 2331655
Change-Id: Id96c473092ee7f0b651413aefdd4b6f2f59e0b12
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808014
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Fix violations where a variable of type non-boolean is used as a
boolean in gpu/nvgpu/common.
JIRA NVGPU-646
Change-Id: I9773d863b715f83ae1772b75d5373f77244bc8ca
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807132
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In nvgpu repository, we have multiple accesses to methods in
pmu_gk20a.h which have register accesses. Instead of directly invoking
these methods, these are now called via HALs. Some common methods such
as pmu_wait_message_cond which donot have any register accesses
are moved to pmu_ipc.c and the method declarations are moved
to pmu.h. Also, changed gm20b_pmu_dbg to
nvgpu_dbg_pmu all across the code base. This would remove all
indirect dependencies via gk20a.h into pmu_gk20a.h. As a result
pmu_gk20a.h is now removed from gk20a.h
JIRA-597
Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804283
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Added support for below multiple therm sensor device & defined macros
GPC_TSOSC
GPC SCI
HBM2_SITE
HBM2_COMBINED
- Added PMU interface for listed therm sensor device
- Added nvgpu interface for listed therm sensor device
- Added construct boardobj support for listed therm sensor device
& called to update nvgpu interface.
- Updated devinit_get_therm_device_table() to read sensor info from
therm device table from vbios table & construct respective
therm device boardobj using construct_therm_device_*()
based on class_id param read from vbios table.
- Updated RPC handler to handle THERM ack request
- Updated gv100 therm ops "get_internal_sensor_limits"
to point to gp106_get_internal_sensor_limits()
Change-Id: I4b4ed501d0625cb8fc7b300c820622e40ae59fe6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676785
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com>
Tested-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fix violations where an arithmetic operation is performed on
signed and unsigned int types.
Jira NVGPU-992
Change-Id: Iab512139a025e035ec82a9dd74245bcf1f3869fb
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1789425
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.
JIRA NVGPU-671
Change-Id: I497fbdb07bb2ec5a404046f06db3c713b3859e8e
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1799525
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This fixes PMU halt caused due to IMEM miss exception
when calling apCtrlEnable/apCtrlDisable.
IMEM miss exception occurs as overlay containing these
functions is not loaded in the PMU's IMEM. This version
loads the overlays before calling these functions.
Bug 2167968.
Change-Id: I37c75c59b1b545571d2bf94f07a7ecb3a814af54
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801250
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Removed the utils.h include from gk20a.h
utils.h is included in those files which
make use of the macros in utils.h
JIRA NVGPU-1005
Change-Id: Ifb41da58db6ff8682fa6b5dfdd8eda11a751fcac
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1785952
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add reply messages for Therm, clock and Perf.
Bug 200428344
Change-Id: Ifb325d546a81f6810ac88b87cc10b718d279ac82
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1792825
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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This fixes errors due to single statement loop bodies
without braces, which is part of Rule 15.6 of MISRA.
This patch covers in gpu/nvgpu/common/
JIRA NVGPU-989
Change-Id: Ic6a98a1cd04e4524dabf650e2f6e73c6b5a1db9d
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786207
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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-Renamed "struct pmu_queue" to "struct
nvgpu_falcon_queue" & moved to falcon.h
-Renamed pmu_queue_* functions to flcn_queue_* &
moved to new file falcon_queue.c
-Created ops for queue functions in struct
nvgpu_falcon_queue to support different queue
types like DMEM/FB-Q.
-Created ops in nvgpu_falcon_engine_dependency_ops
to add engine specific queue functionality & assigned
correct HAL functions in hal*.c file.
-Made changes in dependent functions as needed to replace
struct pmu_queue & calling queue functions using
nvgpu_falcon_queue data structure.
-Replaced input param "struct nvgpu_pmu *pmu" with
"struct gk20a *g" for pmu ops pmu_queue_head/pmu_queue_tail
& also for functions gk20a_pmu_queue_head()/
gk20a_pmu_queue_tail().
-Made changes in nvgpu_pmu_queue_init() to use nvgpu_falcon_queue
for PMU queue.
-Modified Makefile to include falcon_queue.o
-Modified Makefile.sources to include falcon_queue.c
Change-Id: I956328f6631b7154267fd5a29eaa1826190d99d1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776070
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In order to avoid the circular dependencies,
rearrange the static inline functions from
gk20a.h file.
Moved gk20a_gr_flush_channel_tlb function to
gr_gk20a.c and removed the #include gr_gk20a.h
from gk20a.h
Added a helper function utils.h to
move all generic static inline functions which
have no reference to gpu related structures.
ptimer related functions are moved to
ptimer.h
Implementations for as and pmu are moved to
corresponding files.
JIRA NVGPU-624
Change-Id: I4e956326e773ba037bf3a1696cc4c462085dbbe5
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1781941
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- Commit c61e21c868246faf7a9ffc812590941fc362af17 fixed race codition in PMU
state transition.
- The race condition is such that PMU response(intr callback for messages) can
run faster than kthread posting commands to PMU and thus PMU message callback
may skip important pmu state change.
- Commit c61e21c868246faf7a9ffc812590941fc362af17 introduced a fix where PMU
state change was only updated from callback while other places can only update
pmu_state variable
- However, this commit introduced a regression as follows:
- When PMU state is PMU_STATE_INIT_RECEIVED, we loop over every engine
supported by GPU --> If state = PMU_STATE_INIT_RECEIVED, change the state
to PMU_STATE_ELPG_BOOTING and init ELPG else If state != PMU_STATE_INIT_RECEIVED
throw an error saying "PMU INIT not received"
- Now, if GPU supports multiple engines, first engine will check that
pmu_state is PMU_STATE_INIT_RECEIVED and change it to PMU_STATE_ELPG_BOOTING
However, from second engine onwards, since state is already changed to
PMU_STATE_ELPG_BOOTING, all engines except first engine start throwing
error "PMU INIT not received"
- This patch fixes the issue by changing pmu state from
PMU_STATE_INIT_RECEIVED to PMU_STATE_ELPG_BOOTING only once.
Bug 200372838
JIRA EVLR-2164
Change-Id: Ic8c954d14acb1d6ec3adcbc4bcf4d4745542d9f0
Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1769814
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Enable ECC interrupt in Falcon interrupt source
- Enable routing of ECC interrupt to HOST.
code CL: https://git-master.nvidia.com/r/#/c/1758176/
p4 CL# 24408680
Change-Id: Ib43c80be64e29ccbc6b19168e67ac6f4d200b2d8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1758175
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Remove Gr engine reset during ELPG entry.
Engine reset is causing clock gating logic to get reset thus
clock gating gets disabled during ELPG entry sequence.
It leads to higher power numbers observed at light graphics.
Removing GR reset during ELPG entry helped save power.
Bug 2180198
Change-Id: I957951eb93f9d044f4d9a908f2b56a4903dfbfad
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1757695
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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-gp10x f/w version update for ucode
https://git-master.nvidia.com/r/#/c/1748070/
Change-Id: Ie6f40fc931a24162497ef62778069814fd668c20
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1748071
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- PMU version update for NEXT GPU
- Added condition to assign correct ops
for NEXT GPU.
P4 CL#: 24313845
Change-Id: Ia6ee5978d450c228b4f298382746e06da56056a5
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1745022
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- Set gv10x boot gpcclk to 952 MHz
- Created ops to set gv10x boot gpcclk instead
of using clk arbiter to set clocks
Bug 200399373
Change-Id: Ice5956f79d4a52abf455506a798cf7b914f3d3ed
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700788
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-gv100 f/w version update for ucode
https://git-master.nvidia.com/r/#/c/1708170/
Change-Id: I91b900dc3c2e702ec1341ac882b4abc7df875c4c
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1726913
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Add gops to choose vfe_load between GP and GV.
Bug 200399373
Change-Id: I73e0fbd2f1956e81c241f09639c69f33082e617b
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702143
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Removed PMU breakpoints if there is failure during
GR save/restore during ELPG entry/exit.
Bug 2108544
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Change-Id: I08c342f5f79b7484d31e2437ede1881c4dceb6d0
Reviewed-on: https://git-master.nvidia.com/r/1719659
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- gp106 f/w version update for ucode
https://git-master.nvidia.com/r/#/c/1708195/
- APP_VERSION_GP10X 24008084 to 24069912
- nvgpu driver cl's for current changes
https://git-master.nvidia.com/r/#/c/1694546/
https://git-master.nvidia.com/r/#/c/1700746/
p4 CL# 24076634
Change-Id: If15663983a8753a256e47451938be1cf0102fadb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1708199
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- Added vf change inject support for gv10x
- Updated clk_pmu_vf_inject() to fill required data
for pascal or volta vf change inject support
- Added new ctrl clk interface for gv10x clk domain list
- Added pmu interface for gv10x clk domain list &
vf change inject request
- Modified clk cmd, msg & RPC id's to match
with chips_a_23609936 branch
Bug 200399373
Change-Id: Ib9dc10073386f63bdfd92110c7ec3e09b1c484ce
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700746
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PMU ucode is updated to include LDIV slowdown factor in gr_init_param command.
- Defined a new version gr_init_param_v2.
- Updated the PMU FW version code.
- Set the LDIV slowdown factor to 0x1e by default.
- Added sysfs entry to program ldiv_slowdown factor at runtime.
Bug 200391931
Change-Id: Ic66049588c3b20e934faff3f29283f66c30303e4
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1674208
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Mostly just including necessary includes to make sure that
global function declarations actually match their implementations.
Also work around pointer munging warning:
/build/ddpx/linux/kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/pmu.c: In function 'nvgpu_pmu_process_init_msg':
/build/ddpx/linux/kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/pmu.c:348:4: error: dereferencing type-punned pointer will break strict-aliasing rules [-Werror=strict-aliasing]
(*(u32 *)gid_data.signature == PMU_SHA1_GID_SIGNATURE);
Work around this warning by simply moving the type punning.
This code is certainly dangerous - it assumes the endianness
of the header data is the same as the machine this code is
running on. Apparently it works, though, so this ignores
the warning.
JIRA NVGPU-525
Change-Id: Id704bae7805440bebfad51c8c8365e6d2b7a39eb
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1692454
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- gp106 f/w version update for ucode
https://git-master.nvidia.com/r/1702217
- APP_VERSION_GP10X 23913597 to 24008084
- nvgpu clk_vin interface as per chips_a_23609936 CL
https://git-master.nvidia.com/r/#/c/1687591/
p4 CL # 24069912
Bug 200399373
Change-Id: If16566aaf42dfc2460d426f18927eab08309dfcf
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702218
Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com>
Tested-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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clk_vin data structures updated as new calibration type (v20) is added.
GP106 header does not have vin calibration type.
Assuming V10 if calibration type is not V20.
Add fuse calibration for V20 type.
Bug 200399373
Change-Id: I9449de1ecb0d0873f3bc16f46660f93fab5b9eac
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1687591
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Set rpc buffer to 0xFF instead of 0x0 to handle fucntions with rpc id 0
Change-Id: Ife692d9fd19008e225975e41bb13e53522283a54
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702133
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- gp106 f/w version update for ucode
https://git-master.nvidia.com/r/#/c/1693596/
- APP_VERSION_GP10X 23732390 to 23913597
Change-Id: Id3ae28325fda8a66b833245113e7010c76ed2750
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1693616
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com>
Tested-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- gp106 f/w version update for ucode
https://git-master.nvidia.com/r/#/c/1684238/
- APP_VERSION_GP10X "23647537" updated
to "23732390"
Change-Id: Id534b041e4ae90e82b2a8259bb0372689500e871
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1684250
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Two new members added to fll struct and code modified to support
GV100 VBIOS NAFLL tables
Add g->ops for getting vbios clk domains
JIRA NVGPUGV100-39
Change-Id: Iaabea893d55d44a272e2bce2b1d525b122cd36f5
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594289
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Updating gp10x PMU f/w version for ucode
git cl : https://git-master.nvidia.com/r/#/c/1674816/
P4 CL# : 23732390
Change-Id: I4426f7fc96b52f342ac885199e7dd3e413af4a8e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1674857
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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