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path: root/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
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* gpu: nvgpu: stop ELPG init thread during unloadSagar Kamble2021-08-12
| | | | | | | | | | | | | | | | | | | | | | | ELPG initialization thread creation can fail when the process is killed. That leads to driver resume failure. That thread was stopped on suspend and re-created on resume. To avoid the issue above, don't stop the ELPG thread in suspend and let the first created thread handle the ELPG state transitions always. And stop the ELPG thread during unload. bug 3345977 bug 200685277 Change-Id: I8952edf8d1664ed258f238e265002e716d1bf5c2 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2573763 (cherry picked from commit f4571194b02094c7d447052bf0b411a44582ef09) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2574436 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove ZBC save/restore by PMUDivya Singhatwaria2021-03-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | - ZBC save/restore registers are removed in GP10B PMU ucode. - These registers are saved/restored from CTXSW ucode during ELPG entry/exit. - Accessing the ZBC registers will cause PMU EXTERR error. - To resolve this, ZBC functionality is removed from GP10B feature list in PMU ucode. - From NvGPU driver, set NVGPU_PMU_ZBC_SAVE bit to false for GP10B - Updated the GP10B PMU app version for the ucode: https://git-master.nvidia.com/r/c/tegra/kernel-firmware-t18x/+/2476260 P4 CL link related to this PMU ucode change: https://p4sw-swarm.nvidia.com/changes/29594520 Bug 3233071 Bug 200696431 Change-Id: If3f1707b79699e7e2e65367418b25ac71b09cf0b Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2476259 Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: Update PMU ucode version.Deepak2018-09-28
| | | | | | | | | | | | | | | | | | | | | | | | PMU ucode is updated to use acrlib from t19xbringup branch. We are seeing build issues due to incompatibility with acrlib from tegra_acr branch. CTX_DMA aperture to be used for loading LS falcons needed update in the local acrlib. Bug 2400729. Change-Id: Iad00a332acfac307c389bde504893a87abaf7460 Signed-off-by: Deepak <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1849182 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: GPU_NEXT pmu version updateMahantesh Kumbar2018-09-26
| | | | | | | | | | | | | | | | | | PMU version update for ucode CL https://git-master.nvidia.com/r/1844810 JIRA NVGPUT-85 Change-Id: I87ca4d06fdae0fb6977e7aaf3cba7ded00d23ac1 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1844863 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move header location of gk20a.hDebarshi Dutta2018-09-25
| | | | | | | | | | | | | Update header path of gk20a.h in files present in common/ to <nvgpu/gk20a.h> Jira NVGPU-597 Change-Id: I3431dae93ada9bd561454c89a0b99c5292ab4a8d Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1832024 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: PMU cleanup for ACRMahantesh Kumbar2018-09-24
| | | | | | | | | | | | | | | | | | | | | - Removed ACR support code from PMU module - Deleted ACR related ops from pmu ops - Deleted assigning of ACR related ops using pmu ops during HAL init -Removed code related to ACR bootstrap & dependent code for all chips. JIRA NVGPU-1147 Change-Id: I47a851a6b67a9aacde863685537c34566f97dc8d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817990 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Add GV10x perf eventVaikundanathan S2018-09-20
| | | | | | | | | | | | | | | In case of VFE update, schedule work to set P0 clocks. Added function nvgpu_clk_set_fll_clk_gv10x to update P0 clocks on perf event. Fixed MISRA issues caused by this excluding external functions and MACROs Bug 2331655 Change-Id: Id96c473092ee7f0b651413aefdd4b6f2f59e0b12 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808014 Reviewed-on: https://git-master.nvidia.com/r/1813881 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: common: MISRA 10.1 boolean fixesAmulya2018-09-19
| | | | | | | | | | | | | | | | Fix violations where a variable of type non-boolean is used as a boolean in gpu/nvgpu/common. JIRA NVGPU-646 Change-Id: I9773d863b715f83ae1772b75d5373f77244bc8ca Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807132 GVS: Gerrit_Virtual_Submit Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: common: fix MISRA 10.4 violationsSai Nikhil2018-08-22
| | | | | | | | | | | | | | | | | | | | | | | MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fix violations where an arithmetic operation is performed on signed and unsigned int types. Jira NVGPU-992 Change-Id: Iab512139a025e035ec82a9dd74245bcf1f3869fb Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1789425 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: common: pmu: Fix MISRA 15.6 violationsSrirangan2018-08-21
| | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I497fbdb07bb2ec5a404046f06db3c713b3859e8e Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1799525 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: t19x: Update pmu ucode version.Deepak Goyal2018-08-20
| | | | | | | | | | | | | | | | | | | | | This fixes PMU halt caused due to IMEM miss exception when calling apCtrlEnable/apCtrlDisable. IMEM miss exception occurs as overlay containing these functions is not loaded in the PMU's IMEM. This version loads the overlays before calling these functions. Bug 2167968. Change-Id: I37c75c59b1b545571d2bf94f07a7ecb3a814af54 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801250 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove utils.h from gk20a.hVinod G2018-08-10
| | | | | | | | | | | | | | | | Removed the utils.h include from gk20a.h utils.h is included in those files which make use of the macros in utils.h JIRA NVGPU-1005 Change-Id: Ifb41da58db6ff8682fa6b5dfdd8eda11a751fcac Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1785952 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: common: Fix MISRA 15.6 violationsSrirangan2018-08-02
| | | | | | | | | | | | | | | | | | This fixes errors due to single statement loop bodies without braces, which is part of Rule 15.6 of MISRA. This patch covers in gpu/nvgpu/common/ JIRA NVGPU-989 Change-Id: Ic6a98a1cd04e4524dabf650e2f6e73c6b5a1db9d Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1786207 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: falcon queue supportMahantesh Kumbar2018-07-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Renamed "struct pmu_queue" to "struct nvgpu_falcon_queue" & moved to falcon.h -Renamed pmu_queue_* functions to flcn_queue_* & moved to new file falcon_queue.c -Created ops for queue functions in struct nvgpu_falcon_queue to support different queue types like DMEM/FB-Q. -Created ops in nvgpu_falcon_engine_dependency_ops to add engine specific queue functionality & assigned correct HAL functions in hal*.c file. -Made changes in dependent functions as needed to replace struct pmu_queue & calling queue functions using nvgpu_falcon_queue data structure. -Replaced input param "struct nvgpu_pmu *pmu" with "struct gk20a *g" for pmu ops pmu_queue_head/pmu_queue_tail & also for functions gk20a_pmu_queue_head()/ gk20a_pmu_queue_tail(). -Made changes in nvgpu_pmu_queue_init() to use nvgpu_falcon_queue for PMU queue. -Modified Makefile to include falcon_queue.o -Modified Makefile.sources to include falcon_queue.c Change-Id: I956328f6631b7154267fd5a29eaa1826190d99d1 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1776070 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: GPU_NEXT PMU ucode version updateMahantesh Kumbar2018-07-02
| | | | | | | | | | | | | | | | | - Enable ECC interrupt in Falcon interrupt source - Enable routing of ECC interrupt to HOST. code CL: https://git-master.nvidia.com/r/#/c/1758176/ p4 CL# 24408680 Change-Id: Ib43c80be64e29ccbc6b19168e67ac6f4d200b2d8 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1758175 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* PMU: t19x: PMU ucode update.Deepak Goyal2018-06-27
| | | | | | | | | | | | | | | | | | | | | | | Remove Gr engine reset during ELPG entry. Engine reset is causing clock gating logic to get reset thus clock gating gets disabled during ELPG entry sequence. It leads to higher power numbers observed at light graphics. Removing GR reset during ELPG entry helped save power. Bug 2180198 Change-Id: I957951eb93f9d044f4d9a908f2b56a4903dfbfad Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1757695 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10x PMU f/w version updateVaikundanathan S2018-06-14
| | | | | | | | | | | | | | -gp10x f/w version update for ucode https://git-master.nvidia.com/r/#/c/1748070/ Change-Id: Ie6f40fc931a24162497ef62778069814fd668c20 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1748071 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: GPU NEXT PMU version updateMahantesh Kumbar2018-06-14
| | | | | | | | | | | | | | | | | | - PMU version update for NEXT GPU - Added condition to assign correct ops for NEXT GPU. P4 CL#: 24313845 Change-Id: Ia6ee5978d450c228b4f298382746e06da56056a5 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1745022 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set gv10x boot clockVaikundanathan S2018-06-14
| | | | | | | | | | | | | | | - Set gv10x boot gpcclk to 952 MHz - Created ops to set gv10x boot gpcclk instead of using clk arbiter to set clocks Bug 200399373 Change-Id: Ice5956f79d4a52abf455506a798cf7b914f3d3ed Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700788 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu : nvgpu: gv100 pmu f/w version updateVaikundanathan S2018-06-14
| | | | | | | | | | | | | | -gv100 f/w version update for ucode https://git-master.nvidia.com/r/#/c/1708170/ Change-Id: I91b900dc3c2e702ec1341ac882b4abc7df875c4c Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1726913 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Update vfe_load for GV100Vaikundanathan S2018-06-14
| | | | | | | | | | | | Add gops to choose vfe_load between GP and GV. Bug 200399373 Change-Id: I73e0fbd2f1956e81c241f09639c69f33082e617b Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702143 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update PMU firmware versionDeepak Goyal2018-05-17
| | | | | | | | | | | | | | | | | Removed PMU breakpoints if there is failure during GR save/restore during ELPG entry/exit. Bug 2108544 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Change-Id: I08c342f5f79b7484d31e2437ede1881c4dceb6d0 Reviewed-on: https://git-master.nvidia.com/r/1719659 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp106 pmu f/w version updateMahantesh Kumbar2018-05-14
| | | | | | | | | | | | | | | | | | | - gp106 f/w version update for ucode https://git-master.nvidia.com/r/#/c/1708195/ - APP_VERSION_GP10X 24008084 to 24069912 - nvgpu driver cl's for current changes https://git-master.nvidia.com/r/#/c/1694546/ https://git-master.nvidia.com/r/#/c/1700746/ p4 CL# 24076634 Change-Id: If15663983a8753a256e47451938be1cf0102fadb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1708199 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vf inject changesVaikundanathan S2018-05-14
| | | | | | | | | | | | | | | | | | | | - Added vf change inject support for gv10x - Updated clk_pmu_vf_inject() to fill required data for pascal or volta vf change inject support - Added new ctrl clk interface for gv10x clk domain list - Added pmu interface for gv10x clk domain list & vf change inject request - Modified clk cmd, msg & RPC id's to match with chips_a_23609936 branch Bug 200399373 Change-Id: Ib9dc10073386f63bdfd92110c7ec3e09b1c484ce Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700746 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add LDIV slowdown factor in INIT cmd.Deepak Goyal2018-05-09
| | | | | | | | | | | | | | | | PMU ucode is updated to include LDIV slowdown factor in gr_init_param command. - Defined a new version gr_init_param_v2. - Updated the PMU FW version code. - Set the LDIV slowdown factor to 0x1e by default. - Added sysfs entry to program ldiv_slowdown factor at runtime. Bug 200391931 Change-Id: Ic66049588c3b20e934faff3f29283f66c30303e4 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1674208 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu : nvgpu: gp106 pmu f/w version updateMahantesh Kumbar2018-05-04
| | | | | | | | | | | | | | | | | | | | | | | | - gp106 f/w version update for ucode https://git-master.nvidia.com/r/1702217 - APP_VERSION_GP10X 23913597 to 24008084 - nvgpu clk_vin interface as per chips_a_23609936 CL https://git-master.nvidia.com/r/#/c/1687591/ p4 CL # 24069912 Bug 200399373 Change-Id: If16566aaf42dfc2460d426f18927eab08309dfcf Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702218 Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com> Tested-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update clk_vin interface as per chips_aVaikundanathan S2018-05-04
| | | | | | | | | | | | | | | | clk_vin data structures updated as new calibration type (v20) is added. GP106 header does not have vin calibration type. Assuming V10 if calibration type is not V20. Add fuse calibration for V20 type. Bug 200399373 Change-Id: I9449de1ecb0d0873f3bc16f46660f93fab5b9eac Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1687591 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: GP106 PMU ucode version updateMahantesh Kumbar2018-04-25
| | | | | | | | | | | | | | | | | | - gp106 f/w version update for ucode https://git-master.nvidia.com/r/#/c/1693596/ - APP_VERSION_GP10X 23732390 to 23913597 Change-Id: Id3ae28325fda8a66b833245113e7010c76ed2750 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1693616 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com> Tested-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp106 f/w version updateMahantesh Kumbar2018-04-12
| | | | | | | | | | | | | - gp106 f/w version update for ucode https://git-master.nvidia.com/r/#/c/1684238/ - APP_VERSION_GP10X "23647537" updated to "23732390" Change-Id: Id534b041e4ae90e82b2a8259bb0372689500e871 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1684250 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update clk_fll interface as per chips_aTejal Kudav2018-04-12
| | | | | | | | | | | | | | | | | | | Two new members added to fll struct and code modified to support GV100 VBIOS NAFLL tables Add g->ops for getting vbios clk domains JIRA NVGPUGV100-39 Change-Id: Iaabea893d55d44a272e2bce2b1d525b122cd36f5 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594289 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10x PMU f/w version updateMahantesh Kumbar2018-03-15
| | | | | | | | | | | | | | | | | - Updating gp10x PMU f/w version for ucode git cl : https://git-master.nvidia.com/r/#/c/1674816/ P4 CL# : 23732390 Change-Id: I4426f7fc96b52f342ac885199e7dd3e413af4a8e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1674857 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv10x volt rail boardobj changesMahantesh Kumbar2018-03-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Created volt ops under pmu_ver to support volt_set_voltage, volt_get_voltage & volt_send_load_cmd_to_pmu. - Renamed volt load, set_voltage & get_voltage gp10x method names. - Added new volt load, set_voltage & get_voltage methods for gv10x using RPC & added code to handle ack in pmu_rpc_handler() along with struct rail_list changes. - Updated volt ops of gp106 & gv100 to point to respective methods. - Added member volt_dev_idx_ipc_vmin & volt_scale_exp_pwr_equ_idx to "struct nv_pmu_volt_volt_rail_boardobj_set" & "struct voltage_rail" made changes to update members as needed. - Added member volt_scale_exp_pwr_equ_idx to "struct vbios_voltage_rail_table_1x_entry" to read value from VBIOS table & update rail boardobj set interface. - Defines for volt RPC "NV_PMU_RPC_ID_VOLT_*" - Define struct's volt load, set_voltage & get_voltage to execute volt RPC. Change-Id: I4a41adcf7536468beaa8a73f551b1d608aabd161 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1659728 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PMU nv_pmu_boardobj & queue updateMahantesh Kumbar2018-03-13
| | | | | | | | | | | | | | | | | | | | | | | | | - Updated "struct nv_pmu_boardobj, nv_pmu_boardobj_query & nv_pmu_boardobjgrp_super" by adding new members as per gv10x PMU ucode boardobj interface. - Created "PMU_QUEUE_COUNT_FOR_V5 4" for gv10x PMU ucode - Created "PMU_QUEUE_MSG_IDX_FOR_V5 3" for gv10x PMU ucode - Deleted unused "PMU_QUEUE_MSG_IDX_FOR_4" - Updating "APP_VERSION_GV10X 23616379" for ucode git CL: https://git-master.nvidia.com/r/#/c/1662993/ P4 CL#: 23647491 - Updating "APP_VERSION_GP10X 22099494" for ucode git CL: https://git-master.nvidia.com/r/#/c/1662995/ P4 CL#: 23647537 Change-Id: I6e8e2b30e81422f8b529a2fad6d926f93bd73d3e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1656643 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: boardobj update for gv10x branchMahantesh Kumbar2018-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Created ops for below boardobj methods to support gp10x & gv10x branch boardobj changes, and defined methods for gv10x with postfix _v1 with below names boardobjgrp_pmucmd_construct_impl boardobjgrp_pmuset_impl boardobjgrp_pmugetstatus_impl is_boardobjgrp_pmucmd_id_valid - These ops are assigned based on PMU version to respective chip. - Modified BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT & BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT to support gp10x & gv10x branch changes - Updated struct boardobjgrp_pmu_cmd to include members needed for gv10x boardobj changes - Created "struct nv_pmu_rpc_struct_board_obj_grp_cmd" to execute BOARD_OBJ_GRP_CMD using RPC. - Defined method boardobjgrp_pmucmdsend_rpc() to send BOARD_OBJ_GRP_CMD to PMU. Change-Id: If2551bdda80e897e7b21d2966881586f3bbc7a9b Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1656511 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PMU super surface supportMahantesh Kumbar2018-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added ops "pmu.alloc_super_surface" to create memory space for pmu super surface - Defined method nvgpu_pmu_sysmem_surface_alloc() to allocate pmu super surface memory & assigned to "pmu.alloc_super_surface" for gv100 - "pmu.alloc_super_surface" set to NULL for gp106 - Memory space of size "struct nv_pmu_super_surface" is allocated during pmu sw init setup if "pmu.alloc_super_surface" is not NULL & free if error occur. - Added ops "pmu_ver.config_pmu_cmdline_args_super_surface" to describe PMU super surface details to PMU ucode as part of pmu command line args command if "pmu.alloc_super_surface" is not NULL. - Updated pmu_cmdline_args_v6 to include member "struct flcn_mem_desc_v0 super_surface" - Free allocated memory for PMU super surface in nvgpu_remove_pmu_support() method - Added "struct nvgpu_mem super_surface_buf" to "nvgpu_pmu" struct - Created header file "gpmu_super_surf_if.h" to include interface about pmu super surface, added "struct nv_pmu_super_surface" to hold super surface members along with rsvd[x] dummy space to sync members offset with PMU super surface members. Change-Id: I2b28912bf4d86a8cc72884e3b023f21c73fb3503 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1656571 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Update PMU firmware.Deepak Goyal2018-02-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | PMU ucode is updated to include engine ID in the PG messages sent from PMU to gpu driver. Right now we were getting random values from the PMU ucode as it uses ELPG msg structure without initializing. It further causes incorrect values of ELPG state variables maintained in the nvgpu driver. PMU ucode update: https://git-master.nvidia.com/r/1661642 Bug 2046561 Change-Id: Iec1ba87b8d0c0c7ac7423f782fd5a0333a4b5842 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1661653 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: PMU f/w updateMahantesh Kumbar2018-01-25
| | | | | | | | | | | | | | | | | | | | | | | | -Added new version of pmu init msg "pmu_init_msg_pmu_v5" -created methods to support new pmu init message parameter read based on f/w version for below ops. .get_pmu_msg_pmu_init_msg_ptr .get_pmu_init_msg_pmu_sw_mg_off .get_pmu_init_msg_pmu_sw_mg_size -Corrected PMU_DMEM_ALLOC_ALIGNMENT value to 32 bit to allocate PMU DMEM space for nvgpu -Updated PMU version of GV100/APP_VERSION_BIGGPU to 23440730 & PMU ucode CL is https://git-master.nvidia.com/r/#/c/1642432/ Change-Id: Ib1e0197b5f3a229a601e810c9c0d93f05b9d69e7 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1642229 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PMU code cleanupMahantesh Kumbar2018-01-23
| | | | | | | | | | | | | | | | | | | | -removed unsupported PMU f/w version defines & corrected naming specific to chip -removed unsupported PMU f/w version methods which are not useful for existing ucode. -removed unsupported PMU interface which are not useful for existing ucode Change-Id: I17933ff656f48a888e049d680f108b2ef7537439 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1643399 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b PMU ucode F/W version updateMahantesh Kumbar2018-01-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - F/W version update for gv11b PMU ucode of CL https://git-master.nvidia.com/r/#/c/1628288/ Current CL has PMU F/W version for ucode bin of P4 CL# 23378914 P4 CL# & its changes. - 23378914 - Don't post "PMU_PG_EVENT_IDLE_SNAP" event in method pgConvertPgInterrupts_GP10X() - 23355380 - Remove debug code included by mistake in P4 change list #23354716 - 23354716 - Made change to point CONVERT_PG_INTERRUPTS of gv11b to _GP10x - pgConvertPgInterrupts_GP10X() - Removed PMU halt upon FIFO preempt timeout in _fifoPreemptRunlist_GP10X() Bug 2039371 Bug 200377983 Change-Id: I8ce7cb926203b329308944235a06933768ed2a5f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1628380 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Update PMU ucode version.dgoyal@nvidia.com2017-12-27
| | | | | | | | | | | | | | | | | | - Enabled ECC interrupt to host. - Fix to ignore IDLE_SNAP during ELPG_ENTRY. - Production signatures. Change-Id: Ie9e549a123b3fbdcde69fa1d4d2ea3ac20e3fa64 Signed-off-by: y <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1620059 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: call destructor for boardobj and boardobjgrpThomas Fleury2017-11-06
| | | | | | | | | | | | | | | | | | Maintain a list of boardobj and boardobjgrp, so that we can free related objects when removing pmu support. A flag is added in boardobj so that the destructor can determine if it should free the object. This 'allocated' flag is false when the object is embedded into another structure, which should be freed through other means. JIRA EVLR-1959 Bug 200352099 Change-Id: I6a3ff3c57f7428dd145deacf98f2992a9be9796d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586596 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix dma memory leak in remove pmu supportThomas Fleury2017-11-06
| | | | | | | | | | | | | | | | | | | Add missing unmap and free for seq_buf and ucode (acr & hsbl). JIRA EVLR-1959 Bug 200352009 Change-Id: I3e422ce07228b59554ab1407c29e45c70479134d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586576 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix kernel memory leak in pmu remove supportThomas Fleury2017-11-06
| | | | | | | | | | | | | | | When unbinding the driver, secure pmu firmware was not freed in nvgpu_remove_pmu_support(). Free related firmware if previously allocated. JIRA EVLR-1959 Bug 200352099 Change-Id: If9e431964837b3233ec25931b2ab61da920e5540 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1582909 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Change license for common files to MITTerje Bergstrom2017-09-26
| | | | | | | | | | | | Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I1474065f4b552112786974a16cdf076c5179540e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1565880 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: prevent crash during unbindDavid Nieto2017-09-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change solves crashes during bind that were introduced in the driver during the OS unification refactoring due to lack of coverage of the remove() function. The fixes during remove are: (1) Prevent NULL dereference on GPUs with secure boot (2) Prevent NULL dereferences when fecs_trace is not enabled (3) Added PRAMIN blocker during driver removal if HW is no longer accesible (4) Prevent double free of debugfs nodes as they are handled on the debugfs_remove_recursive() call (5) quiesce() can now be called without checking is HW accesible flag is set (6) added function to free irq so no IRQ association is left on the driver after it is removed (7) prevent NULL dereference on nvgpu_thread_stop() if the thread is already stopped JIRA: EVLR-1739 Change-Id: I787d38f202d5267a6b34815f23e1bc88110e8455 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1563005 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu : nvgpu: PG503 PMU app version updateMahantesh Kumbar2017-09-13
| | | | | | | | | | | | JIRA NVGPUGV100-7 Change-Id: I4ee55248d6b0e27a4245c1b798853c463c34066d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1559002 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu : nvgpu: PG503 PMU ucode supportMahantesh Kumbar2017-09-12
| | | | | | | | | | | | | | | | | - Added PMU app version - Added method to init queue - P4 CL# 22754073 JIRA NVGPUGV100-7 Change-Id: I095ee5d0ad59693ee7d9eb3035f85f63f1b033d3 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1549418 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move non-fp pmu members from gpu_opsSunny He2017-08-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move non-function pointer members out of the pmu and pmu_ver substructs of gpu_ops. Ideally gpu_ops will have only function ponters, better matching its intended purpose and improving readability. - g.ops.pmu_ver.cmd_id_zbc_table_update has been changed to g.pmu_ver_cmd_id_zbc_table_update - g.ops.pmu.lspmuwprinitdone has been changed to g.pmu_lsf_pmu_wpr_init_done - g.ops.pmu.lsfloadedfalconid has been changed to g.pmu_lsf_loaded_falcon_id Boolean flags have been implemented using the enabled.h API - g.ops.pmu_ver.is_pmu_zbc_save_supported moved to common flag NVGPU_PMU_ZBC_SAVE - g.ops.pmu.fecsbootstrapdone moved to common flag NVGPU_PMU_FECS_BOOTSTRAP_DONE Jira NVGPU-74 Change-Id: I08fb20f8f382277f2c579f06d561914c000ea6e0 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530981 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: reorganize PMU F/W supportMahantesh Kumbar2017-06-13
- Moved pmu f/w related support from pmu_gk20a.c to "drivers/gpu/nvgpu/common/pmu/pmu_fw.c" file - Prepended with nvgpu_ for global functions & replaced wherever used - Moved below list related to PMU f/w init/remove, PMU version specific ops, non-secure ucode blob prepare, JIRA NVGPU-56 Change-Id: Ifdad8c560bd233e98728717d5868119e9d8e8d90 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1480636 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 22:44:50 -0400