| Commit message (Collapse) | Author | Age |
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MISRA 21.2 states that we may not use reserved identifiers; since
all identifiers beginning with '_' are reserved by libc, the usage
of '__' as a prefix is disallowed.
This fixes places in the public allocator APIs. This consists of
the various init routines which are used to create an allocator
and the debug macro used within the allocator code.
The buddy allocator was handled by collapsing the internal
'__' prepended version with the non-prefixed version. The only
required change was in the page_allocator code which now had to
pass in a NULL vm pointer (since the VM is not needed for managing
VIDMEM).
JIRA NVGPU-1029
Change-Id: I484a144e61789bf594c525c1ca307b96d120830f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813578
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Debug page was allocated and programmed to HUB MMU in GR code. This
introduces a dependency from GR to FB and is anyway the wrong place.
Move the code to allocate memory to generic MM code, and the code
to program the addresses to FB.
Change-Id: Ib6d3c96efde6794cf5e8cd4c908525c85b57c233
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801423
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Vidmem size query was in mm_xxx.c. It involves reading a register from
FB, so move the query to FB HAL.
JIRA NVGPU-1063
Change-Id: I30dfd2c4fdcdd6c841f85aaab7431d52473759bd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801425
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The issues are:
1. Non-fixed allocs must take into account explicit PTE size
requests. Previously the PTE size was determines from the
allocation size which was incorect. To do this, the PTE size
is now plumbed through all GPU VA allocations. This is what
the new alloc_pte() op does.
2. Fix buddy PTE size assignment. This changes a '<=' into a
'<' in the buddy allocation logic. Effectively this is now
leaving the PTE size for buddy blocks equal to the PDE block
size as 'ANY'.
This prevents a buddy block of PDE size which has yet to be
allocated from having a specific PDE size. Without this its
possible to do a fixed alloc that fails unexpectedly due to
mismatching PDE sizes.
Consider two PDE block sized fixed allocs that are contained
in one buddy twice the size of a PDE block. Let's call these
fixed allocs S and B (small and big). Let's assume that two
fixed allocs are done, each targeting S and B, in that order.
With the current logic the first alloc, when we create the
two buddies S and B, causes both S and B to have a PTE size of
SMALL. Now when the second alloc happens we attempt to find
a buddy B with a PTE size of either BIG or ANY. But we cannot
becasue B already has size SMALL. This casues us to appear
like we have a conflicting fixed alloc despite this not being
the case.
3. Misc cleanups & bug fixes:
- Clean up some MISRA issues
- Delete an extraneous unlock that could have caused a
deadlock.
Bug 200105199
Change-Id: Ib5447ec6705a5a289ac0cf3d5e90c79b5d67582d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1768582
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We use bootstrap vidmem allocator for all the vidmem allocations that happen
boot time
And we need to program physical address for all the potential vidmem buffers
that we program into h/w and are needed during boot
So force the allocator to allocate contigous memory
We otherwise see a warning dump when we program physical address of memory which
is allocated in multiple pages
Bug 2180284
Jira NVGPUT-12
Change-Id: Ib9c2d42ea463bc424c2cb4da8ffd8ebae436e0f6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805467
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We right now have a bootstrap carveout in vidmem of size 16M and having base
address at {total_vidmem_size - 256M}
So this design divides rest of the vidmem into two chunks
And the size of bootstrap carveout is also small and insufficient for vidmem
allocations during boot
Hence increase the bootstrap vidmem carevout to 256M and move it to the end
of entire vidmem
Rename the carevout name for wpr_co to bootstrap_co as it is more appropriate
Also update __nvgpu_vidmem_do_clear_all() to clear only one chunk of vidmem
instead of two
Bug 2180284
Jira NVGPUT-12
Change-Id: I9c8d62bcd705c7112385df3d4f714e0190b48e17
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805466
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If gk20a_comptaglines_alloc() is called with an uninitialized comptag allocator
we right now see a kernel panic like this
[ 445.097931] [<ffffff8008fdd650>] __mutex_lock_slowpath+0xe0/0x188
[ 445.104275] [<ffffff8008fdd748>] mutex_lock+0x50/0x68
[ 445.109773] [<ffffff80012ef340>] gk20a_comptaglines_alloc+0x30/0x98 [nvgpu]
[ 445.117169] [<ffffff80012e0fdc>] gk20a_alloc_or_get_comptags+0xe4/0x140 [nvgpu]
[ 445.124910] [<ffffff80012ee1cc>] nvgpu_vm_map+0x414/0x7b8 [nvgpu]
[ 445.131433] [<ffffff80012dd754>] nvgpu_vm_map_linux+0x114/0x1e8 [nvgpu]
[ 445.138475] [<ffffff80012dd978>] nvgpu_vm_map_buffer+0x150/0x238 [nvgpu]
[ 445.145605] [<ffffff80012d2834>] gk20a_as_dev_ioctl+0x30c/0xa78 [nvgpu]
[ 445.152473] [<ffffff8008262154>] do_vfs_ioctl+0xc4/0x8f8
Fix this by checking explicitly that comptag allocator is initialized in
gk20a_comptaglines_alloc() and gk20a_comptaglines_free()
Bug 2171567
Change-Id: Iaac6d77e40a8aaa01f2bacbe0cb54ec447100075
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805170
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MISRA 21.2 states that we may not use reserved identifiers; since
all identifiers beginning with '_' are reserved by libc, the usage
of '__' as a prefix is disallowed.
This change fixes uses of '__' prepended to static functions defined
in page_allocator.c. Since these funcitons were static and had no
naming conflicts the '__' was simply removed. For free_pages() this
also needed to have a nvgpu specific prefix since free_pages()
conflicts with a Linux kernel function name.
JIRA NVGPU-1029
Change-Id: I8b96e55244bd2de166f7dcc64d2b30427757ea8f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812826
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for calls to nvgpu_mutex_init and
improves related error handling.
JIRA NVGPU-677
Change-Id: I609fa138520cc7ccfdd5aa0e7fd28c8ca0b3a21c
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805598
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This migrates the common DMA code (os agnostic) to the
common directory. This new unit will be the common DMA
allocator that lets users allocate SYSMEM, VIDMEM, or
either. Other units will be responsible for actually
handling the mechanics of allocating VIDMEM or SYSMEM.
Also update the names of the DMA related files so that
tmake doesn't complain about duplicate C file names. To
do this call the common DMA file dma.c and prepend the
OS to the other DMA files. So now we have:
common/mm/dma.c
os/posix/posix-dma.c
os/linux/linux-dma.c
JIRA NVGPU-990
Change-Id: I22d2d41803ad89be7d9c28f87864ce4fedf10836
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1799807
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__nvgpu_gmmu_map() does not currently have a mechanism for returning an
error code if something goes wrong; it just returns zero on error, or a
nonzero address when mapping was successful. Change it to return 0
instead of -ENOMEM if the creation of nvgpu_sgt from mem fails. Out of
memory is the only meaningful failure case anyway, and this -ENOMEM
would just look like a (huge) memory address.
Change-Id: If176e165b1f9a8fa84a1bdf3080c9059a193081f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812491
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fix violations where an arithmetic operation is performed on
signed and unsigned int types.
In balloc_get_order_list() the argument "int order" has been changed to
a u64 because all callers of this function pass a u64 argument.
JIRA NVGPU-992
Change-Id: Ie2964f9f1dfb2865a9bd6e6cdd65e7cda6c1f638
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1784419
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Many files used declarations from timers.h implicitly via another header
file(s). Add several #includes explicitly to their users.
Jira NVGPU-967
Change-Id: I88b515061db87c69bd85e3655b74d0271a80d9bf
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804611
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Remove a few unnecessary includes from channel_gk20a.h and add them to c
files where needed.
Jira NVGPU-967
Change-Id: Ic38132c776a56b6966424806faab7871575b6c10
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804609
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MISRA 21.2 states that we may not use reserved identifiers; since
all identifiers beginning with '_' are reserved by libc, the usage
of '__' as a prefix is disallowed.
This change removes the usage of the '__a' argument scattered
throughout the nvgpu allocator code.
JIRA NVGPU-1029
Change-Id: I553a66a3d7d2c6bb21ba0a45e29a1d01f7b89f49
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803353
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
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MISRA 21.2 states that we may not use reserved identifiers; since
all identifiers beginning with '_' are reserved by libc, the usage
of '__' as a prefix is disallowed.
This change removes the usage of the '__a' argument scattered
throughout the nvgpu allocator code.
JIRA NVGPU-1029
Change-Id: Ic39213ab800e92c6815ce5b9deb22520aa6d0630
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803352
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA 21.2 states that we may not use reserved identifiers; since
all identifiers beginning with '_' are reserved by libc, the usage
of '__' as a prefix is disallowed.
This change removes the usage of the '__a' argument scattered
throughout the nvgpu allocator code.
JIRA NVGPU-1029
Change-Id: I5a9b8a3e0602ba4d519ca19080951402b6f3287d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803351
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Changed the enum gmmu_pgsz_gk20a into macros and changed all the
instances of it.
The enum gmmu_pgsz_gk20a was being used in for loops, where it was
compared with an integer. This violates MISRA rule 10.4, which only
allows arithmetic operations on operands of the same essential type
category. Changing this enum into macro will fix this violation.
JIRA NVGPU-993
Change-Id: I6f18b08bc7548093d99e8229378415bcdec749e3
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795593
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Add a WAR for gm20b that allows us to force the PMU VM to use
128K large pages. For some reason setting the small page size
to 64K breaks the PMU boot. Unclear why. Bug needs to be filed
and fixed. Once fixed this patch can and should be reverted.
Bug 200105199
Change-Id: I2b4c9e214e2a6dff33bea18bd2359c33364ba03f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1782769
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Fix violations where the conversion is from a non-enum type to enum
type or vice-versa.
JIRA NVGPU-659
Change-Id: I45f43c907b810cc86b2a4480809d0c6757ed3486
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1802322
GVS: Gerrit_Virtual_Submit
Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com>
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MISRA Rule 10.3 states that the value of an expression shall not be
assigned to an object with a narrower essential type or of a
different essential type category.
We have cases where we are converting to/from char and non char types
and this fix 10.3 violations resulting from these conversions.
This also fix violations in conversions between s8 and non-s8 types
as s8 can be typedefed as char.
Jira NVGPU-1010
Change-Id: I150dd633eb7575de9ea2bedd598b7af74d1fcbd9
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801613
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.
JIRA NVGPU-671
Change-Id: Ieeecf719dca9acc1a116d2893637bf770caf4f5b
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794241
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.
JIRA NVGPU-671
Change-Id: I129cc170d27c7f1f2e193b326b95ebbe3c75ebab
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795600
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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This flag - has_physical_mode - doesn't seem to do much other than
force the PTE/PDE and inst block addresses to be physical instead
of potentially IOMMUed.
There is a reason to do this on volta (nvlink not being IOMMU'able
being the primary reason) but this flag is too general it seems.
The flag was being enabled on all native platforms. The problem is
that some page tables (the maxwell small page directories) could
be larger than 4KB which meant that the allocation used for them
could be potentially discontiguous. Discontiguous page directories
obviously is incorrect.
This patch deletes the has_physical_mode flag and instead replaces
the places where it's checked with a check for nvlink being
enabled. Since we _do_ want to program phyiscal PDEs and PTEs for
NVLINK devices (regardless of IOMMU status they always access
memory by physical address) we need a check for NVLINK state.
Bug 200414723
Change-Id: I09ad86b12d8aabcf9648a22503f4747fd63514dd
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1792163
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When built with -Wmissing-braces, compiler complains about the missing
braces in nvgpu_mem_rd_n, nvgpu_mem_wr_n and nvgpu_memset. Add the
braces to satisfy compiler and to fix related MISRA C violations.
Change-Id: Ibe3606dc59317f8230cea57cfea8d0fe5af641d6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796238
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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This fixes errors due to single statement loop bodies
without braces, which is part of Rule 15.6 of MISRA.
This patch covers in gpu/nvgpu/common/
JIRA NVGPU-989
Change-Id: Ic6a98a1cd04e4524dabf650e2f6e73c6b5a1db9d
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786207
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Do vidmem destroy only if get_vidmem_size HAL op is
set which will skip this for iGPU. Do not read vidmem
size explicitly in vidmem destroy in shutdown path after
prepare poweroff.
Bug 200427479
Change-Id: Ic919b03d44b5505646b449fd74f9f5d3e9e0dfee
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776388
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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FB fault buffer is enabled on finalize poweron. Disable the buffer
in prepare poweroff. This also eliminates the need to disable
the buffer in fault info mem destroy which otherwise accesses
GPU registers after these are locked in prepare poweroff.
Bug 200427479
Change-Id: I1ca3e6ed4417847731c09b887134f215a2ba331c
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776387
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Hard code flags for enabling and disabling FB hub interrupts.
JIRA NVGPU-714
Change-Id: I806ef443cb9e27e221d407d633ca91d8fb40d075
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1769853
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nvgpu_mem_rd*() functions were implemented per OS. They also used
nvgpu_pramin_access_batched() and implemented a big portion of logic
for using PRAMIN in OS specific code.
Make the implementation for the functions generic. Move all PRAMIN
logic to PRAMIN and simplify the interface provided by PRAMIN.
Change-Id: I1acb9e8d7d424325dc73314d5738cb2c9ebf7692
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1753708
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Move the lock release to cover the g->ops.mm.gmmu_unmap() call
as well since this too must be called under the VM lock.
Bug 2156667
Change-Id: I17d819d1341e211a3d0bd0ecb7cf09884eaca767
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1764598
GVS: Gerrit_Virtual_Submit
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In the vm_area free code, when unreffing the mappings owned by
the vm_area, we need to continue holding the VM lock.
Also add a comment specifying this requirement in the VM code.
Bug 2156667
Change-Id: If0b430f045e4c585fcba2d3176163e5b19be8326
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1763235
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The GPU page tables are always mapped to the CPU now, so they don't need
the nvgpu_mem_{begin,end}() calls.
Change-Id: Ic48eeed3a6f002c78f89ef07922cddf835337de3
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1761579
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membar.sys does synchronization with the whole system (GPU and CPU),
membar.gl does synchronization within the GPU.
In gv11b, fb flush is generating membar.gl instead of membar.sys, which
is an issue. To fix this issue. following WAR is used:
1. Use bar1 engine id and bind it to a particular pdb,
2. Then instead of a fb_flush, issue a tlb invalidate of the bar1 pdb.
Now allocation of vm for bar1 instance block and bar1 binding is done
without check for bar1 support. Only bar1 register mapping is done
based on bar1 support enabled.
Bug 2112790
Change-Id: I76f43f1178a68f10823d48bc9da55d2bd686dd52
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1750257
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When generating the PTE size for a given mapping the code must
consider whether the GPU is being IOMMU'ed. The presence and
usage of an IOMMU implies the buffers will appear contiguous
to the GPU. Without an IOMMU we cannot assume that and therefor
must use small pages regardless of the size of the buffer to
be mapped.
Bug 2011640
Change-Id: I6c64cbcd8844a7ed855116754b795d949a3003af
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1697891
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The vidmem shall be destroyed only if it has been
initialized. If not skipped, it accesses mutexes
which are in invalid state. This results in BUG like:
BUG: spinlock bad magic on CPU#0, rmmod/1560
Also, destroy vidmem bootstrap allocator which is
set up in nvgpu_vidmem_init().
Bug 1987855
Change-Id: I68e91422a54b40feeb9071158b797828e2391303
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730535
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These macros are sometimes defined by the std library headers.
So when they are defined #undef them and use our own version.
Also explicitly include types.h from gmmu.c since it uses the min
and max macros.
JIRA NVGPU-525
Change-Id: I905ff23ef7a4a96467be59c4a124cb09b63f1f96
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1721015
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Switch all logging to nvgpu_log*(). gk20a_dbg* macros are
intentionally left there because of use from other repositories.
Because the new functions do not work without a pointer to struct
gk20a, and piping it just for logging is excessive, some log messages
are deleted.
Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704148
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Allow a potential IOMMU'ed GMMU mapping for all SYSMEM buffers
inlcuding coherent sysmem. Typically this won't actually happen
since IO coherent mappings will also often be accessed over
NVLINK which is physically addressed.
Also update the comments surrounding this code to take into
account the new NVLINK nuances. Since NVLINK buffers are
directly mapped even when the IOMMU is enabled this is very
deserving of a comment explaining what's going on.
Lastly add some simple functions for checking if an nvgpu_mem
(or a particular aperture field) is a sysmem aperture. Currently
this includes SYSMEM and SYSMEM_COH.
JIRA EVLR-2333
Change-Id: I992d3c25d433778eaad9eef338aa5aa42afe597e
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665185
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- QNX is pulling dgpu code from linux which has
multiple build failure on QNX. Like QNX needs
explicit declaration for all non-static functions.
Some linux specific headers need to be put under
__KERNEL__ flag.
Change-Id: I15af1a1f6a069c82f9a81449f4f7c7d48612de42
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665752
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nvgpu_semaphore_pool_alloc() returns an ERR_PTR instead of NULL which
the caller checks on failure. Common code should not use ERR_PTRs
though, so modify nvgpu_semaphore_pool_alloc() to return error code
separately and fix nvgpu_init_sema_pool() to consider this.
Jira NVGPU-513
Change-Id: I435c0d2794d226774ed4c6b3bcbdde1e741854d8
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1673458
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When nvgpu maps an nvgpu_mem struct the nvgpu driver has a choice of
either using a fixed or non-fixed mapping. For non-fixed mappings the
GMMU APIs allocate a VA space for the caller. In that case the GMMU
APIs must also free that VA range when nvgpu unmaps the nvgpu_mem.
For fixed mappings the GMMU APIs must instead not manage the life
time of the VA space. To support these two possibilities add a field
to nvgpu_mem that specifies whether the GMMU APIs must or must not
free the GPU VA range during the GMMU unmap operation.
Also fix a case in the nvgpu vm_area code that would double free a
VA allocation in some cases (sparse allocs).
Change-Id: Idc32dbb8208fa7c1c05823e67b54707fea51c6b7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1669920
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Add __nvgpu_sgl_phys function that can be used to implement IPA
to PA translation in a subsequent change.
Adapt existing function prototypes to add pointer to gpu context,
as we will need to check if IPA to PA translation is needed.
JIRA EVLR-2442
Bug 200392719
Change-Id: I5a734c958c8277d1bf673c020dafb31263f142d6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
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Userspace can and should retry vidmem allocations if there are pending
clears still to be executed by the GPU. But this requires the -EAGAIN
to properly propagate back to userspace.
Bug 200378648
Change-Id: Ib930711270439843e043d65c2e87b60612a76239
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1669099
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This reverts commit 848af2ce6de6140323a6ffe3075bf8021e119434.
This is a revert of a revert, etc, etc. It re-enables IO coherence again.
JIRA EVLR-2333
Change-Id: Ibf97dce2f892e48a1200a06cd38a1c5d9603be04
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1669722
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This reverts commit 89fbf39a05483917c0a9f3453fd94c724bc37375.
Bug 2075315
Change-Id: Id34a0376be5160b164931926ec600f77edf69667
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1668487
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This reverts commit 5a35a95654d561fce09a3b9abf6b82bb7a29d74b.
JIRA EVLR-2333
Change-Id: I923c32496c343d39d34f6d406c38a9f6ce7dc6e0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1667167
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The operations in struct nvgpu_sgt_ops have a scatter-gather list (sgl)
argument which is a void pointer. Change the type signatures to take
struct nvgpu_sgl * which is an opaque marker type that makes it more
difficult to pass around wrong arguments, as anything goes for void *.
Explicit types add also self-documentation to the code.
For some added safety, some explicit type casts are now required in
implementors of the nvgpu_sgt_ops interface when converting between the
general nvgpu_sgl type and implementation-specific types. This is not
purely a bad thing because the casts explain clearly where type
conversions are happening.
Jira NVGPU-30
Jira NVGPU-52
Jira NVGPU-305
Change-Id: Ic64eed6d2d39ca5786e62b172ddb7133af16817a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1643555
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Also revert other changes related to IO coherence. This may be the
culprit in a recent dev-kernel lockdown.
Bug 2070609
Change-Id: Ida178aef161fadbc6db9512521ea51c702c1564b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665914
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When using a coherent DMA API wee must make sure to program
any aperture fields with the coherent aperture setting. To
do this the nvgpu_aperture_mask() function was modified to
take a third aperture mask argument, a coherent setting, so
that code can use this function to generate coherent aperture
settings.
The aperture choice is some what tricky: the default version
of this function uses the state of the DMA API to determine
what aperture to use for SYSMEM: either coherent or
non-coherent internally. Thus a kernel user need only specify
the normal nvgpu_mem struct and the correct mask should be
chosen. Due to many uses of nvgpu_mem structs not created
directly from the DMA API wrapper it's easier to translate
SYSMEM to SYSMEM_COH after creation.
However, the GMMU mapping code, will encounter buffers from
userspace with difference coerency attributes than the DMA
API. Thus the __nvgpu_aperture_mask() really respects the
aperture setting passed in regardless of the DMA API state.
This aperture setting is pulled from NVGPU_VM_MAP_IO_COHERENT
since this is either passed in from userspace or set by the
kernel when using coherent DMA. The aperture field in attrs
is upgraded to coh if this flag is set.
This change also adds a coherent sysmem mask everywhere that
it can. There's a couple places that do not have a coherent
register field defined yet. These need to eventually be
defined and added.
Lastly the aperture mask code has been mvoed from the Linux
vm.c code to the general vm.c code since this function has
no Linux dependencies.
Note: depends on https://git-master.nvidia.com/r/1664536 for
new register fields.
JIRA EVLR-2333
Change-Id: I4b347911ecb7c511738563fe6c34d0e6aa380d71
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1655220
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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