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path: root/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c
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* gpu: nvgpu: Move Linux files away from commonTerje Bergstrom2018-06-15
| | | | | | | | | | | | | | | Move all Linux source code files to drivers/gpu/nvgpu/os/linux from drivers/gpu/nvgpu/common/linux. This changes the meaning of common to be OS independent. JIRA NVGPU-598 JIRA NVGPU-601 Change-Id: Ib7f2a43d3688bb0d0b7dcc48469a6783fd988ce9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1747714 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: update ecc sysfs node handlingNitin Kumbhar2018-06-15
| | | | | | | | | | | | | | | | | | | | | | | | | | Make ecc sysfs hash table per GPU by adding it as part of nvgpu_os_linux. Using a single hash table might give incorrect results as GPUs have same filenames and a filename is used as a key for a lookup. Add device_attribute as part of struct gk20a_ecc_stat. Using a single array of pointers of device attribute for an ecc_stat results in memory leak and incorrect stats if multiple GPUs are present on the system. This array of pointers will always hold info for GPU which created sysfs nodes last. Fix this by making device attribute array per ecc stat per GPU. Fix ecc stat removal to consider zero sub-units for a given number of hwunits. The multiplication with zero results in not removing any sysfs node at all. Bug 1987855 Change-Id: Ifcacc5623cede8decfe228c02d72786337cd0876 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add remove_gr_sysfs gpu opNitin Kumbhar2018-06-15
| | | | | | | | | | | | | | | | | | | | | Add remove_gr_sys() op to gpu_ops to reverse steps done in create_gr_sysfs(). Make gv11b_tegra_remove() specific to gv11b instead to properly remove sysfs nodes. This also helps in having gv11b specific remove steps. Also, update platform remove function of dGPU i.e. nvgpu_pci_tegra_remove() to remove sysfs nodes. This adds parity with iGPU platform remove. Bug 1987855 Change-Id: Ibbaffac5c24346709347f86444a951461894354d Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735987 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gr: remove only created sysfs nodesNitin Kumbhar2018-06-14
| | | | | | | | | | | | | | | | Sysfs nodes for GR stats are created on GR init. If nvgpu module is removed without any ops, then it tries to remove sysfs nodes which do not exist resulting in kernel panic. Fix this issue by removing sysfs nodes only if ecc counters are initialized. Bug 1987855 Change-Id: I3f967ee92ec02ad19ffbd9bfa8bace5bfd229dd2 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730536 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Set DMA mask on a per-platform basisAlex Waterman2018-06-14
| | | | | | | | | | | | | | | | | | | | Each GPU platform has different DMA limitations. For older chips the maximum size of a DMA buffer was more limited than newer SoCs (read: Xavier) and discrete GPUs. This patch adds support to set the DMA mask for a GPU on a per platform basis by adding a platform field that is populated with the maximum allowed DMA mask. That mask is programmed by the driver common code. If no mask is specified then the default mask size is 16GB (34 bits). Bug 2043276 Change-Id: I9c3c76c86bac6c485eb1197326e662516fbcaa41 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700980 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: enable syncpt shim for nvlinkThomas Fleury2018-05-07
| | | | | | | | | | | | | | Get host1x node reference from c1_rp device tree node, and enable syncpoints shim in case of nvlink. JIRA EVLR-2441 JIRA EVLR-2585 Change-Id: Idbf1edf656557f2ed2d3bd27393c2f4d5d1ad75a Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1663360 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: enable rail gatingseshendra Gadagottu2018-04-03
| | | | | | | | | | | | | | | | | | Enable gpu rail gating with idle delay of 500msec. Bug 2051863 Change-Id: I1bdfc1b3db38dff871cd5d62542dd51efbd07496 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640557 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Enable aELPG.Deepak Goyal2018-03-06
| | | | | | | | | | | | | | | Bug 2046561 Change-Id: I625db1797d699f6e74374535a836ab1c1b0a19ce Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1657214 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Allow disabling CDE functionalityTerje Bergstrom2018-02-15
| | | | | | | | | | | | | CDE is a Tegra SoC specific feature. Add new config option CONFIG_NVGPU_SUPPORT_CDE and #ifdef all CDE specific code with it. JIRA NVGPU-4 Change-Id: I6f0b0047d6ba2b5c36c2eb9b8a1514776741f5b5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1648002 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use preallocated VPR bufferTerje Bergstrom2018-02-15
| | | | | | | | | | | | To prevent deadlock while allocating VPR in nvgpu, allocate all the needed VPR memory at probe time and use an internal allocator to hand out space for VPR buffers. Change-Id: I584b9a0f746d5d1dec021cdfbd6f26b4b92e4412 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1655324 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: enable elpgseshendra Gadagottu2018-02-13
| | | | | | | | | | | | | | | | Enabled Engine Level Power Gating for gv11b. Bug 2051863 Change-Id: I59a51dbe8fa9f13e4b8be03f02e1571093fdaeb0 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1646322 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Cleanup usage of bypass_smmuAlex Waterman2018-02-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPU has multiple different operating modes in respect to IOMMU'ability. As such there needs to be a clean way to tell the driver whether it is IOMMU'able or not. This state also does not always reflect what is possible: all becasue the GPU can generate IOMMU'ed memory requests doesn't mean it wants to. The nvgpu_iommuable() API has now existed for a little while which is a useful way to convey whether nvgpu should consider the GPU as IOMMU'able. However, there is also the g->mm.bypass_smmu flag which used to be able to override what the GPU decided it should do. Typically it was assigned the same value as nvgpu_iommuable() but that was not necessarily a requirment. This patch removes all the usages of g->mm.bypass_smmu and instead uses the nvgpu_iommuable() function. All places where the check against g->mm.bypass_smmu have been replaced with nvgpu_iommuable(). The code should now be much cleaner. Subsequently other checks can also be placed in the nvgpu_iommuable() function. For example, when NVLINK comes online and the GPU should no longer consider DMA addresses and instead use scatter-gather lists directly the ngpu_iommuable() function will be able to check the state of NVLINK and then act accordingly. Change-Id: I0da6262386de15709decac89d63d3eecfec20cd7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1648332 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: enable devfreqseshendra Gadagottu2018-02-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | After moving devfreq enable to end of finalize power on, intermittent issues related to gpu booting with devfreq enabled are fixed. Enabled devfreq for gv11b by enabling ""nvhost_podgov" governor in platform data. Reused scaling functions from gp10b/gk20a. Removed emc floor on railgate for power saving. Added max emc frequency as floor in rail-ungate for faster gpu boot. Bug 2049965 Bug 2039013 Bug 200377508 Change-Id: Ia1dec278b663b9f7ed859dd953a60f3eae7ef9a0 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1644702 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: enable clock gating featuresseshendra Gadagottu2018-01-31
| | | | | | | | | | | | | | | Enable ELCG, BLCG and SLCG features. Bug 2051863 Change-Id: Id2c67c94c7b2dd0517d4ee4b0280aeb19f3fe35a Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1646302 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: cause early VPR resize for gv11bDeepak Nibade2018-01-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | Patch 7240b3c2 enabled secure allocation for gv11b But since we allocate secure buffers in poweron path, and secure allocation needs GPU to be in off state, this results in deadlock in poweron path To solve this, we already cause early VPR resize for older chips by calling gk20a_tegra_secure_page_alloc() from late_probe Implement same for gv11b. Add late_probe callback and add a call to gk20a_tegra_secure_page_alloc() Bug 2038249 Change-Id: I8c17b069962b26edbd0639a7c0d6c2fdaa352935 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1648831 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala <seemaj@nvidia.com>
* Revert "gpu: nvgpu: gv11b: enable devfreq"Konsta Holtta2018-01-23
| | | | | | | | | | | | | | | This reverts commit 968d8cd3e543b951714d9a86373bd721d08c8482. Bug 2049965 Bug 2039013 Bug 200377508 Change-Id: I813947417740f8d3a0c9bea82784df1dd4a5f1ac Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1644224 Reviewed-by: David Pu <dpu@nvidia.com> Tested-by: David Pu <dpu@nvidia.com>
* gpu: nvgpu: Fold T19x code back to main code pathsTerje Bergstrom2018-01-23
| | | | | | | | | | | | | Lots of code paths were split to T19x specific code paths and structs due to split repository. Now that repositories are merged, fold all of them back to main code paths and structs and remove the T19x specific Kconfig flag. Change-Id: Id0d17a5f0610fc0b49f51ab6664e716dc8b222b6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640606 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: enable devfreqseshendra Gadagottu2018-01-19
| | | | | | | | | | | | | | | | | | | | | | Enable devfreq for gv11b by enabling ""nvhost_podgov" governor in platform data. Reuse scaling functions from gp10b/gk20a. Remove emc floor on railgate for power saving and make max emc frequency as floor in rail-ungate for faster gpu boot. Bug 2039013 Bug 200377508 Change-Id: I65ee7735202e3decbe3451157f7fc1f1f273c3ff Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639752 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Enable perfmon.Deepak Goyal2018-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | t19x PMU ucode uses RPC mechanism for PERFMON commands. - Declared "pmu_init_perfmon", "pmu_perfmon_start_sampling", "pmu_perfmon_stop_sampling" and "pmu_perfmon_get_samples" in pmu ops to differenciate for chips using RPC & legacy cmd/msg mechanism. - Defined and used PERFMON RPC commands for t19x - INIT - START - STOP - QUERY - Adds RPC handler for PERFMON RPC commands. - For guerying GPU utilization/load, we need to send PERFMON_QUERY RPC command for gv11b. - Enables perfmon for gv11b. Bug 2039013 Change-Id: Ic32326f81d48f11bc772afb8fee2dee6e427a699 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1614114 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: init ch_wdt_timeout_msSeema Khowala2018-01-08
| | | | | | | | | | | | | This is needed for watchdog to work. Change-Id: Ic1e197e5f6701fafd8b614cd43bb610bdc8518ae Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1632230 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Enable secure alloc for GV11bSami Kiminki2018-01-03
| | | | | | | | | | | | | | | Kernel needs to be able to allocate VPR memory for buffers for protected contexts. So, let's call gk20a_tegra_init_secure_alloc and enable VPR for GV11B. Bug 2039456 Bug 2040513 Change-Id: Ie27d8f04b1a414c36b42516ce3147d38d8472d54 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1628566 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove TSG required flagTerje Bergstrom2018-01-02
| | | | | | | | | | | | | | | | | | Remove nvgpu internal flag indicating that TSGs are required. We now require TSGs always. This also fixes a regression where CE channels were back to using bare channels on gp106. Bug 1842197 Change-Id: Id359e5a455fb324278636bb8994b583936490ffd Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1628481 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Report LTC errors per sliceDavid Nieto2017-12-28
| | | | | | | | | | | | | | | | | | | | | Add support to report ltc ecc errors per slice (1) use new logic to detect subunits (2) store size of array and check before comparison to prevent out of bounds derefencing (3) use new hashing to prevent collisions or entries with permuted names bug 2037425 Change-Id: I63b9f0df43b9dceddc1bae17924c4723072f569e Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1620854 GVS: Gerrit_Virtual_Submit Reviewed-by: Chris Dragan <kdragan@nvidia.com> Tested-by: Chris Dragan <kdragan@nvidia.com> Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: remove cde supportSeema Khowala2017-12-26
| | | | | | | | | | | Change-Id: I04df795b20413a2d07a252d77b3eba853890fcae Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1624087 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: host1x probed only if syncpoints supportedSeema Khowala2017-12-26
| | | | | | | | | | | Change-Id: I645f272f8fc3fffda95a82716558c081e323aed0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1624097 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Require TSGs for CE alwaysTerje Bergstrom2017-12-14
| | | | | | | | | | | All channels should be wrapped in TSGs so that bare channel support can be dropped. Bind all CE channels to TSGs. Bug 1842197 Change-Id: Ia55748d5b53750d860f7764b532ef9eeb6f214b8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616693
* gpu: nvgpu: gv11b: get syncpt aperture only if host1x is presentSeema Khowala2017-12-14
| | | | | | | | | | | | | nvgpu_get_nvhost_dev will not return error if host1x field within gv11b device tree is not present. It will just set has_syncpoints in gk20a struct to false. syncpt_unit_interface* should be called only if g->has_syncpoints is set to true. Change-Id: Id1eb94aba4cff1942ad519f528ebdb8291963971 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1615973 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: PMU parity HWW ECC supportDavid Nieto2017-12-11
| | | | | | | | | | | | | | | Adding support for ISR handling of ECC parity errors for PMU unit and setting the initial IRQDST mask to deliver ECC interrupts to host in the non-stall PMU irq path JIRA: GPUT19X-83 Change-Id: I8efae6777811893ecce79d0e32ba81b62c27b1ef Signed-off-by: David Nieto <dmartineznie@nvidia.com> Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1611625 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move gv11b platform specific file to linuxDeepak Nibade2017-11-27
gv11b/platform_gv11b_tegra.c is mostly linux specific so move it to linux specific directory Change-Id: I3e10bafcf672967e35a7955038cd9285b8697a57 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1604283 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-23 08:28:17 -0400