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Update header path of gk20a.h in files present in common/
to <nvgpu/gk20a.h>
Jira NVGPU-597
Change-Id: I3431dae93ada9bd561454c89a0b99c5292ab4a8d
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832024
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in common directory
by renaming them to follow the convention,
'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition
between file name and directory or 'NVGPU_HEADER-NAME' when there
is repetition.
JIRA NVGPU-1028
Change-Id: Idf10f6b179cfd96bfb8ab8e9e2bf79c26591905d
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809086
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In gk20a_ctrl_ioctl_gpu_characteristics() we right now just calculate
GPC mask in s/w and return to user space
But this could give incorrect result as any GPC could be floorswept
in h/w
Add gops.fuse.fuse_status_opt_gpc() to read GPC floorsweep status
from fuse
Add gops.gr.get_gpc_mask() to get actual GPC mask from h/w
Set these HALs only for dGPUs right now. Fuse register to read GPC
mask is not yet supported in simulation and hence simulation boot fails
These HALs will be set for iGPU once simulation issue is resolved
Use gops.gr.get_gpc_mask() if it is defined in
gk20a_ctrl_ioctl_gpu_characteristics() to send the actual GPC mask
to user space
Jira NVGPUT-132
Change-Id: I3b552de07883328fcfa41d4334ec0d777e04bdd3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822811
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.
JIRA NVGPU-671
Change-Id: I18cf871f2d1296b931d6ab43f1ac668551171dcc
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805076
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule 10.3 states that the value of an expression shall not be
assigned to an object with a narrower essential type or of a
different essential type category.
We have cases where we are converting to/from char and non char types
and this fix 10.3 violations resulting from these conversions.
This also fix violations in conversions between s8 and non-s8 types
as s8 can be typedefed as char.
Jira NVGPU-1010
Change-Id: I150dd633eb7575de9ea2bedd598b7af74d1fcbd9
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801613
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move implementation of fuse HAL to common/fuse. Also implements new
fuse query functions for FBIO, FBP, TPC floorsweeping and security
fuses.
JIRA NVGPU-957
Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797177
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