| Commit message (Collapse) | Author | Age |
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All chips should use the waiting version of BAR1 bind since gm20b.
Change gp10b and gp106 to do that. BAR1 is not used in Volta.
JIRa NVGPU-588
Change-Id: Ib6957ebea4effa7c64f4d71522447fa6245728ed
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730895
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Code touching timer registers was combined with bus code. They're two
logically separate register spaces, so separate the code accordingly.
JIRA NVGPU-588
Change-Id: I40e2925ff156669f41ddc1f2e7714f92a2da367b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730893
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move setting of BAR0_WINDOW to bus HAL. Also moves the usage of spinlock to
common code so that pramin_gk20a.[ch] can be deleted.
JIRA NVGPU-588
Change-Id: I3ceabc56016711b2c93f31fedf07daa778a4873a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730890
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Registers to set priv interrupts are in priv_ring, but the code was
in bus HAL. Move the code and related HALs to priv_ring instead.
JIRA NVGPU-588
Change-Id: I708d11f77405dbba86586a0d1da42f65bcc1de9d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730889
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move implementation of bus HAL to common/bus.
Change-Id: Ia89350f9d94f3ccfd5500a340e6a677cd7d4cfaa
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1726337
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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