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* gpu: nvgpu: prepare MCLK/GPCLK enumeration changeThomas Fleury2017-01-31
| | | | | | | | | | | | | | | | | | GPC2CLK has been replaced with GPCCLK on user API. Remove related definition from kernel API. GPCLCK and MCLK are currently assigned EQU values in kernel API. We want to move to a simple enumeration as used in nvrm_gpu. During the transition, an alias value will be defined for each clock, and kernel will accept both. Jira DNVGPU-210 Jira DNVGPU-211 Change-Id: I944fe78be9f810279f7a69964be7cda9b9c8d40d Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1292593 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: fix round_rate ops for CCF"Srikar Srimath Tirumala2017-01-30
| | | | | | | | | | | | This reverts commit 34d8421ab4e9ecd0af09f7fefe71b9a1d8781061. Bug 200233943 Change-Id: Id03b7922c955d252aff54e6bbd8163926bdc65fb Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com> Reviewed-on: http://git-master/r/1280828 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp106: Generate new gp106 headersTerje Bergstrom2017-01-26
| | | | | | | | | | | | | | Hardware headers have been outdated. Regenerate with newest tool. At the same time correct the incorrect usage of fuse fields. JIRA DNVGPU-172 Change-Id: If190bf0cf2e41d525e6ea374a30efd1f63963e5e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1294267 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Skip checking for null in error pathTerje Bergstrom2017-01-26
| | | | | | | | | | | | | | | | | | clk_prog_construct_1x_master_table() first constructs boardobj and then allocates further structures. If the further allocation fails, it calls exit label. The exit label checks if boardobj is NULL and calls destructor if it is. As there is no path to get to exit label with boardobj NULL, skip the check. Coverity ID 2011367 Change-Id: Ic157397ca42d26b7640f7b28f6a9fb929d517412 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1291684 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Free nvgpu_clk_dev in case of errorTerje Bergstrom2017-01-26
| | | | | | | | | | | | | | | | If nvgpu_clk_arb_install_fd() gets an error from nvgpu_clk_notification_queue_alloc(), it fails to free the nvgpu_clk_dev that it allocated earlier. Direct the error case to call an appropriate fail label. Coverity ID 1862040 Change-Id: I1d804d4f5261ec64831938f997f9efc3f2700b60 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1291683 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Free board_obj_ptr in case of errorTerje Bergstrom2017-01-26
| | | | | | | | | | | | | | | | If construct_clk_prog() gets an error reported in status, it returns NULL instead of the constructed board_obj_ptr. Call a destructor to prevent leaking any possibly constructed board_obj_ptr. Coverity ID 490171 Change-Id: Icf359da6511b108a03dd86d4556c5cbb288e90de Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1291682 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix failures in VF table updateDavid Nieto2017-01-18
| | | | | | | | | | | | | | | | | | | | The variable indicating the size of the buffer for GPC vf points was not reset before the query, thus sporadic failures could happen if the number of available VF points changed on an update Maximum number of points increased to 256. This is the maximum that can fit in the boardobj table bug 200269804 Change-Id: Icb4ae386135a9bb40d4345eb73c5584fecd79147 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1286028 Reviewed-on: http://git-master/r/1287589 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move gp106 HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gp106 HW headers to a new directory specially for them: include/nvgpu/hw/gp106 And change the code to include like so: #include <nvgpu/hw/gp106/hw_fb_gp106.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: I76a4ff2e92021150ce65a8843bc12bb614a0e68a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280327 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Start re-organizing the HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | | | | Reorganize the HW headers of gk20a. The headers are moved to a new directory: include/nvgpu/hw/gk20a And from the code are included like so: #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h> This is the first step in reorganizing all of the HW headers for gm20b, gm206, etc. This is part of a larger effort to re-structure and make the driver more readable and scalable. Bug 1799159 Change-Id: Ic151155cbc2e6f75009f2d9d597b364a1bed2c4c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1244790 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: CPU timestamps for alarmsThomas Fleury2017-01-06
| | | | | | | | | | | | | | | Use sched_clock() for alarm timestamps to return number of nanoseconds since the system was started. Jira DNVGPU-186 Change-Id: Ie16fe5442ea8a5213bf5401a3faedcce387b3d93 Reviewed-on: http://git-master/r/1259026 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> (cherry picked from commit 383601c4d006734e13f0bfa386381573c87209da) Reviewed-on: http://git-master/r/1280888 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add support for alarms in arbiterDavid Nieto2017-01-06
| | | | | | | | | | | | | | | | | Add a queue system to collect alarm notifications and deliver them to user space Add interface for driver to set global alarms JIRA: DNVGPU-189 Change-Id: I24a340283c02d8ea95ad6ea148acdb37157ef69c Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1252475 (cherry picked from commit 5b79c7541066148ce0580d25daad54a8fa82f8be) Reviewed-on: http://git-master/r/1280887 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add read and ioctl for eventsThomas Fleury2017-01-06
| | | | | | | | | | | | | | | Add support for poll/read/ioctl for events in clock arbiter. Jira DNVGPU-186 Change-Id: Id95264fffae2b83a388ff8f186ebe7d723029b7f Reviewed-on: http://git-master/r/1253659 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> (cherry picked from commit 8d652a7313722aab331f82f0841b490ca25cb51d) Reviewed-on: http://git-master/r/1280885 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Do not recursively #include clk.hTerje Bergstrom2017-01-06
| | | | | | | | | | | | | clk.h #includes clk_vin.h, which recursively #includes clk.h without needing anything from clk.h. Remove the #include to improve build time. Bug 200192125 Change-Id: Icab32b7e73a1eaaee8e017367d71b8ebde47c21e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1280350 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Use perf table only if VBIOS supports itTerje Bergstrom2017-01-06
| | | | | | | | | | | | | | | | We retrieve perf table from VBIOS only if respective HAL op is implemented. Later in code we unconditionally dereference a pointer which can lead to NULL pointer access. Fix two new cases by early aborting creation of devinit tables if the perf VBIOS getter is missing. Bug 200192125 Change-Id: I30f20f1829305ecc1117c6301e26ff1b869967eb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1280347 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: free boardobj if construct hits an errVijayakumar2017-01-05
| | | | | | | | | | | | | | | | | | | During construct of some VFE/CLK boardobjs, some data is filled after a boardobj allocation is done. Free up boardobj memory if an error is encountered in the data filling. Coverity ID 490171 Coverity ID 490172 Bug 200192125 Change-Id: I20621f7f9f9e379b8dced4905cd417c2ffa905b0 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1280700 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add GPCCLK on ioctl APIThomas Fleury2017-01-05
| | | | | | | | | | | | | | | Internally we use GPC2CLK in the arbiter, but we should expose GPCCLK on kernel API and in user space. Added GPCCLK on the ioctl API. Arbiter uses GPC2CLK to make queries, then converts to GPCCLK. Jira DNVGPU-210 Change-Id: Id0b8134d0505c1f9bfd655a08e902bdcd03ebd96 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1280316 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Free arb substructures only if arb allocatedTerje Bergstrom2017-01-04
| | | | | | | | | | | | | nvgpu_clk_arb_init_arbiter() allocates master structure arb, and sub-structures which is assigns as members of arb. At failure, there's a single error label, and it tries to free the members of arb without checking that arb was allocated. Change-Id: Ifac7552b05dad17036835eb3ee624eae351ccb7d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1279226 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
* gpu: nvgpu: Fix memory leak in arb installTerje Bergstrom2017-01-04
| | | | | | | | | | | nvgpu_clk_arb_install_fd() leaks dev if it cannot create an fd, and it leaks both dev and fd if it fails to create a file. Change-Id: I65c03401dba44d88be543d3aec2fa3fcd2fb0dcc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1279225 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
* gpu: nvgpu: Include correct boardobjgrp headersTerje Bergstrom2017-01-04
| | | | | | | | | | | clk_prog.h and clk_vin.h refer to boardobjgrp_e32 and boardobjgrp_e255.h. Add explicit #includes for their definition. Change-Id: Ib651b071f3c17bbc30ddaea0ef9bc5437ec9f2f4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1279224 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
* gpu: nvgpu: Use perf table only VBIOS supports itTerje Bergstrom2017-01-04
| | | | | | | | | | | | | | | We retrieve perf table from VBIOS only if respective HAL op is implemented. Later in code we unconditionally dereference the pointer which can lead to NULL pointer access. Fix by early aborting creation of devinit tables if the perf VBIOS getter is missing. Change-Id: If48aa6dac724056dd1feb2ef520e343736d4db85 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1279223 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
* gpu: nvgpu: MSCG supportMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | - update gp106 pg engine init/list/features HALs to support MS engine - Added defines & interface for lpwr tables read from vbios. - lpwr module which reads idx/gr/ms table from vbios to map rppg/mscg support with respective p-state - lpwr module public functions to control lpwr features enable/disable mscg/rppg & mclk-change request whenever change in mclk-change parameters - lpwr public functions to know rppg/mscg support for requested pstate, - added mutex t prevent PG transition while arbiter executes pstate transition - nvgpu_clk_arb_get_current_pstate() of clk arbiter to get current pstate JIRA DNVGPU-71 Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247553 (cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b) Reviewed-on: http://git-master/r/1270989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix CLFC arbiter vf table updateDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | | (1) Adding additional debug in case of VF update failure (2) The length of the tables must be re-initialized prior to requesting the vf table update JIRA: DNVGPU-193 Change-Id: Id5a369359bc5f52ee58da539bfc3ec1ec7887de1 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1252061 (cherry picked from commit dfb6fec02f8e3ff6a22bbea000347923b0306018) Reviewed-on: http://git-master/r/1274547 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: call set volt always during vf switchVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | bug 1845211 clfc is reset during vf switch. it resets delta values stored in pmu structure. if voltage has not changed, delta calculation happens on top of corrected voltage causing volt to keep on increasing in cases where voltage does not change during a vf switch. Change-Id: I9d1a58b6b7652f22c3a7304162bb8ca6f7d1da6f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1266632 (cherry picked from commit 74e2e97d4d149d3eac65b5f65b358b977fba463e) Reviewed-on: http://git-master/r/1273911 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: actions before and after vf changeVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | JIRA DNVGPU-175 1)Add functions to be called before and after vf change 2)Capture noise unaware vmin value and pass it as param to vf change functions 3)Before VF change disable CLFC and update noise unware vmin 4)After VF change is done enable CLFC Change-Id: I4bb59fbe96ec5a792e8930db3ab4a39ec74c9a71 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1248211 (cherry picked from commit cf07892204d7ce11a0d27ecbc1f5826fbabbde61) Reviewed-on: http://git-master/r/1270950 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: fix fll regime checkVijayakumar2016-12-27
| | | | | | | | | | | | | | For target clocks >= FFR cutoff clock use FR, else use FFR. JIRA DNVGPU-180 Change-Id: Iefed871d2acf1552230b066c32e1b3f69d96079e Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1249041 (cherry picked from commit edcb12d8784c62aa857dcab2e27d4e45033fbf11) Reviewed-on: http://git-master/r/1270883 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set p state floor for sys and xbar clkVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | bug 200254784 If XBAR and SYS clocks for a given GPC clock point is lower than minimum value mentioned in P state set the floor to minimum value mentioned in p state. it was set to value based ratio of a GPC clk value in VF table which can give value higher than one mentioned in p state. Ignore ratio and just set to p state value Change-Id: I9f7cd1d5842d057aff6d8243a31ab503ce35a8ca Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1257251 Reviewed-by: Automatic_Commit_Validation_User (cherry picked from commit 5798680286967ff999f674bedd4fc0411615f914) Reviewed-on: http://git-master/r/1270949 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add clock freq controller supportVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-170 1) Add clock frequency controller VBIOS structure definitions 2) Parse VBIOS tables and build boardobj structures for clock frequency controller. 3) send clock frequency controller data structures to PMU 4) implement public function to send load/unload command to pmu to enable/disable clock frequency controller support Change-Id: I2f37f6a94f342b6fcc71bb802e6e440a0a454486 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1248209 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry picked from commit ed3e27933f21e10b3d7a5257f1b751526945bd07) Reviewed-on: http://git-master/r/1270897 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: p-state bound arbiterDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modification of the ARBITER clocks to be P-State aware Up to now the arbiter just considered the whole range of the GPC and MCLK domains, which could end up on illegal combinations of MCLK, GPC2CLK, and set the SYSCLK and XBARCLK domains below their minimum VCO The following has been implemented: (1) Modified VF tables to add which PState are supported on each point. (2) Return and store the current PState on the arbiter state. (3) Modified logic to prevent illegal combinations of MCLK and GPC2CLK. (4) Modified logic to prevent setting VF points for XBAR and SYS domains below VCO limits. (5) Modified voltage calculation to account for increased values of XBAR and SYS on some VF points. (6) Modified arbiter clock target logic to prevent an application that has not requested a particular VF point to set target to default targets. (7) Remove unnecesary mutexes from critical path JIRA DNVGPU-182 JIRA DNVGPU-183 Change-Id: I3d1c30903278f848681b8da833a867835acc99bb Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1247937 (cherry picked from commit b8bcc07eb3b5b70ec1ee19ace237df99d6170138) Reviewed-on: http://git-master/r/1268063 Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: handle vf curve change due to tempVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-129 1)send 150'c as default temperature to PMU so that PMU will start reading temperature from sensor to evaluate VFE equations 2)Send GP106's temp min and max range for GPU sensor so that PMU will read right temperature 3)PMU will send event whenever temperature goes above +ve hysteresis or goes below -ve hysteresis. Call the Arbiter's VF re-evaluation function in the event handler. Change-Id: Iaebc0655f60e17998f0864824095f4fc8bba5b62 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1245392 (cherry picked from commit 7e59d0faa8cee6aace5524c724001e88248b2da7) Reviewed-on: http://git-master/r/1268062 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: prevent hang on failing arbiter initDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | | | | The current code can lead to application hang when opening device on first time if the arbiter fails to set the clocks Also it solves a buffer overrun condition in case the requested frequency is above the maximum range of the VF curve bug 1835042 Change-Id: I385401ea27d5cc4bfa41b7ca2eb3a1db53138418 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1245911 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1268061 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: resolve signed/unsigned mismatchDavid Nieto2016-12-27
| | | | | | | | | | | JIRA DNVGPU-143 Change-Id: I0536aff4f994efc3dbd2db949068f8e1345ece9c Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1268107 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: make clock arbiter locklessDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | | | | | Modification of the arbiter to remove all locking from the arbiter callback and move the callbacks out of the global queue Adding modification to call for updated values of vf table from arbiter init function and on vf table update JIRA: DNVGPU-170 Change-Id: I7a7d34c0590522901e06356c06fd8114ebf10f37 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1243212 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1268009 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gpu: read effective frequence from counterDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | (1) modified counters debug code to export to the driver (2) modified arbiter to read from those functions (3) modified counter for higher accuracy on MHz range JIRA DNVGPU-164 Change-Id: I2bbf7c9be4dc59718d1d91c53028a39020b5aea5 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239467 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1268008
* nvgpu: gpu: Use pstates for MCLK rangeDavid Nieto2016-12-27
| | | | | | | | | | | | | JIRA DNVGPU-168 Change-Id: I7ac05dca745b22b411fc0aa797969b97536dd2e6 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239466 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1267121 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gpu: arbiter for vf switch managementDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-143 The arbiter is charged with selecting the proper frequencies when multiple applications submit simultaneously clock change requests On the current implementation, the arbiter guarantees that the selected frequency will be always higher or equal to the request, as long as the request is in range. The current code is not yet realtime friendly, as requests are not pre-allocated. Summary of changes: (1) pstate/vf switch no longer selects boot frequency (2) changed mclk code change to accept input freq (3) added arbiter (4) now a single session can submit concurrent requests the last request is the one that applies for that session (5) modified locking mechanism to reduce lock contention (6) Added callback to notify the arbiter that the VF table has changed and is no longer valid (PMU/Thermals must call this when VF table is invalid) (7) changed internal API to work with MHz (8) added debugfs for stats Change-Id: I6a7b05c9447761e8536f84ef86b5ab0793164d63 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239461 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1267120 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: clk requests completion and event fdsThomas Fleury2016-12-27
| | | | | | | | | | | | | | | | | | | Install one completion fd per SET request. Notifications on dedicated event fd. Changed frequencies unit to Hz from MHz. Remove sequence numbers from dummy arbiter. Added effective clock type (query frequency from counters). Jira DNVGPU-125 Change-Id: Id5445c6ae1d6bf06f7f59c82ff6c5d3b34e26483 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1230239 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry picked from commit d17083f4ceb69725c661678607a3e43148d38560) Reviewed-on: http://git-master/r/1243106
* gpu: nvgpu: clk arbiter skeletonThomas Fleury2016-12-27
| | | | | | | | | | | | | | | | | | | | Add clock arbiter skeleton with support of clock sessions, notifications on clock changes, request numbering, and asynchronous handling of clock requests. Provides minimum behaviour to allow unit tests implementation. Actual arbitration and clock settings will be done separately. For now, dummy arbiter keeps last requested target mhz. Actual arbiter may move to a lockless implementation. Jira DNVGPU-125 Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1223476 (cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461) Reviewed-on: http://git-master/r/1243105 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Program RX bias currentTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | Hard code RX bias current to 0x2. Bug 1833830 Change-Id: I1107bad52de7b38d311bc5795739777a4bb4239a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1253656 (cherry picked from commit 7e853b0c62043cc53847e3535e05886d574dc779) Reviewed-on: http://git-master/r/1255724 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp106: Expose the boot max freqTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | Expose the currently hard coded boot frequency, which is at the same time the max frequency. We use it for filling in GPU characteristics. Bug 200251486 Change-Id: I3c0abb7a385a83f61b93ddfa857b982c850853e3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1252906 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com> Tested-by: Shreshtha Sahu <ssahu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Fix signed comparison bugsTerje Bergstrom2016-12-27
| | | | | | | | | | | | Fix small problems related to signed versus unsigned comparisons throughout the driver. Bump up the warning level to prevent such problems from occuring in future. Change-Id: Ib7026728ef0e8c3c9e68956fc9794ec3a786a8a2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1252069 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix sram rail volt calculationVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | JIRA DNVGPU-120 SRAM rail voltage needs to be picked up from SRAM index of VF entries in CLK prog table. Change-Id: Iabfff62edeec5aa9c2ead62d6b943fb2ebb952ed Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1227665 (cherry picked from commit 8053260438bc94397b20e74cf18453624ebeb325) Reviewed-on: http://git-master/r/1244664 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: construct/load tabels & set voltageMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | | | - Read voltage tables from VBIOS & construct then send to PMU. - compare & set voltage based on mclk/gpc2clk clk, take higher voltage between two & set. JIRA DNVGPU-122 Change-Id: I23e7b101a3b1c1b6596620fc6b8319c70bd9a488 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1224365 (cherry picked from commit e0055c3ec798b8312df3fa9bf92bde8c57c6f58c) Reviewed-on: http://git-master/r/1244657 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: create function to program coreclkVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | JIRA DNVGPU-123 now a function can be called with GPC2CLK value It will take care calculating slave clock values and calling VF inject to program clock Made programming of boot clock code to use this newly created function. Change-Id: I74de7e9d98e379e94175ed2d9745ce3ab6c70691 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1221976 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1235056
* gpu: nvgpu: add function to retrieve clk pointsVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-123 Function will copy possible clock points for a given master clock domain to pointer passed. pointer with NULL value and count of zero can be passed to query number of clock points for a given domain so that memory can be allocated and function called again to fill clock points Change-Id: Iec6206f23789980036be99793599e934bd221035 Reviewed-on: http://git-master/r/1218912 (cherry picked from commit 9219697bff1e12deb605325055a02a7b387996e9) Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1235055 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: support to parse VF tableVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-123 function was added to retrieve V for F or F for V for a given clock domain. Clock domain can be master or slave. F or V can be intermediate point between two successive V or F values in VF table. VF table should be cached before calling this function. A F value below Fmin will return Vmin. F > Fmax will return error A V value above Vmax wil return F max. A V value below Vmin will return error. Change-Id: I28b4e8647510c6933e9e1204cfff31d74616e11a Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1211234 (cherry-picked from commit 5b83b03f2454fbec8d49a064ed09b09c92d3e9fa) Reviewed-on: http://git-master/r/1235054 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add support to cache VF table from PMUVijayakumar2016-12-27
| | | | | | | | | | | | JIRA DNVGPU-118 Change-Id: I5c6a919d18e6de077e03180ba70441cfc9791350 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1209849 (cherry picked from commit 469f35e3f65964a3402f7e0c49862bd44b68936a) Reviewed-on: http://git-master/r/1233040 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: parse and execute mclk shadow scriptDavid Nieto2016-12-27
| | | | | | | | | | | | | * Parsing of shadow registers from VBIOS * Partial devinit engine interpreter implementation JIRA DNVGPU-117 Change-Id: I42179748889f17d674ad0a986e81c418b3b8df11 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1214956 Reviewed-on: http://git-master/r/1237293 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: MCLK P8/P5 sequences and APIDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | Adds P5/P8 sequences and simple debugfs API to change from P0->P5 JIRA DNVGPU-117 Change-Id: I5811a5bddd0e11074524cce421bff1e3d441228d Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1208655 (cherry picked from commit dd410a86263e2407e043743945cf09a77910d745) Reviewed-on: http://git-master/r/1231035 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Clocks params updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | - Clocks params update as per r370 JIRA DNVGPU-116 Change-Id: I0aaa1e275aaa2027f2839f3fe24c9aee3e14fd8d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1212827 (cherry picked from commit 54df6ad9668d46dffb5b9d03265948a47611ff13) Reviewed-on: http://git-master/r/1227288 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: sequencer-script updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | Update to sequencer script to support SKU without display. Bug 200231242 Change-Id: Ibd983166be823370fc687eb2fe9bae3aa8c0dab7 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1207096 (cherry picked from commit b573a627b3fe7697c90def46eaf83d755c5d2dee) Reviewed-on: http://git-master/r/1227247 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 16:36:33 -0400